JPH01154546A - Open terminal detecting circuit semiconductor device - Google Patents
Open terminal detecting circuit semiconductor deviceInfo
- Publication number
- JPH01154546A JPH01154546A JP62314741A JP31474187A JPH01154546A JP H01154546 A JPH01154546 A JP H01154546A JP 62314741 A JP62314741 A JP 62314741A JP 31474187 A JP31474187 A JP 31474187A JP H01154546 A JPH01154546 A JP H01154546A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- terminals
- alarm signal
- power supply
- alarm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000001514 detection method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 230000001351 cycling effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
端子開放の障害を検出する機能を持った半導体装置に関
し。[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device having a function of detecting an open terminal failure.
並列接続された複数の端子がすべて開放状態になる前に
アラーム信号を出し、半導体装置の完全なフェイルセー
フ対策を可能とすることを目的とし。The purpose is to issue an alarm signal before all of the multiple terminals connected in parallel become open, enabling complete fail-safe measures for semiconductor devices.
アラーム信号端子と、複数の電源端子と、同数の抵抗と
、同数の基準電圧源と、同数の比較器とを有し、各抵抗
は各電源端子と内部回路間に接続され、各比較器は、一
方の入力端子が各電源端子に接続され、他方の入力端子
が各基準電圧源を介して内部回路と各抵抗との接続点に
接続され、出力端子がアラーム信号端子に接続されてい
るように構成する。It has an alarm signal terminal, a plurality of power supply terminals, the same number of resistors, the same number of reference voltage sources, and the same number of comparators, each resistor is connected between each power supply terminal and the internal circuit, and each comparator is connected between each power supply terminal and the internal circuit. , one input terminal is connected to each power supply terminal, the other input terminal is connected to the connection point between the internal circuit and each resistor via each reference voltage source, and the output terminal is connected to the alarm signal terminal. Configure.
本発明は端子開放の障害を検出する機能を持った半導体
装置に関する。The present invention relates to a semiconductor device having a function of detecting an open terminal failure.
車載用集積回路はエンジン制御、走行制御等に使用され
ており、その信頬性は一般の集積回路に比し厳しく要求
されている。In-vehicle integrated circuits are used for engine control, driving control, etc., and their reliability is more strictly required than for general integrated circuits.
特に、振動や温度サイクルに伴う端子開放については初
期段階での発見が難しく、フィールド障害が発生した場
合はフェイルセーフが要求されている。In particular, open terminals due to vibration or temperature cycling are difficult to detect at an early stage, and fail-safe measures are required in the event of a field failure.
他方、端子短絡障害は例えば半田ブリッジ等により起こ
るが、これは初期除去が可能であり、信頼性上端子開放
程問題ではない。On the other hand, terminal short-circuit failures occur due to, for example, solder bridges, but these can be removed initially and are not as problematic as open terminals in terms of reliability.
端子開放対策については、信号の入出力端子の場合は回
路技術により対応できるが、電源端子〔接地（ＧＮＤ）
端子を含む〕については対応はできなかった。Countermeasures against open terminals can be taken using circuit technology in the case of signal input/output terminals, but
(including terminals)] was not possible.
例えば、入力端子が開放しても電源は生きているから、
端子開放の場合は所定の動作をしないように集積回路の
出力をオフ状態にし、フェイルセーフ対策を可能とする
。このように入力端子の開放モードが判明すると、出力
状態を動かすことは回路的に可能である。For example, even if the input terminal is open, the power supply is still alive, so
In the case of an open terminal, the output of the integrated circuit is turned off so as not to perform a predetermined operation, thereby enabling a fail-safe measure. Once the open mode of the input terminal is known in this way, it is possible to change the output state from a circuit perspective.
ところが、電源端子が開放状態になると集積回路内の回
路はすべて動かなくなり、対応が不可能であった。However, if the power supply terminal became open, all the circuits within the integrated circuit stopped working, making it impossible to deal with this problem.
このため１電源端子を複数個設けて、信頼性を向上する
手段が考えられる。For this reason, it is conceivable to provide a plurality of one power supply terminal to improve reliability.
以下の例においては、電源端子としてＧＮＤ端子につい
て説明する。In the following example, a GND terminal will be explained as a power supply terminal.
第２図（１）、 （２１は従来の半導体装置の電源端子
を説明する平面図である。FIGS. 2(1) and (21) are plan views illustrating power supply terminals of a conventional semiconductor device.
第２図（１）はＧＮＤ端子が１個の通常の場合で、パッ
ケージ側のＧＮＤ端子１はチップ側のポンディングパッ
ド２とワイアボンディングで接続され、ポンディングパ
ッド２はチップ内の内部回路に内部配線により接続され
る。Figure 2 (1) shows the normal case where there is only one GND terminal. GND terminal 1 on the package side is connected to bonding pad 2 on the chip side by wire bonding, and bonding pad 2 is connected to the internal circuit inside the chip. Connected by internal wiring.
この場合、製造条件、あるいは使用条件により。In this case, depending on manufacturing conditions or usage conditions.
例えばポンディング不良１半田付不良等により１個のＧ
ＮＤ端子が開放状態になると２集積回路は機能しなくな
る。For example, one G due to poor bonding, one defective soldering, etc.
If the ND terminal becomes open, the two integrated circuits will no longer function.
第２図（２）はＧＮＤ端子が２個の場合で、パッケージ
側のＧＮＤ端子ＬＡ、 ＩＢはチップ側のポンディング
パッド２Ａ、 ２Ｂとワイアボンディングで接続され。Figure 2 (2) shows a case where there are two GND terminals, and the GND terminals LA and IB on the package side are connected to bonding pads 2A and 2B on the chip side by wire bonding.
ポンディングパッド２Ａ、 ２Ｂは相互に接続され、内
部回路に内部配線により接続される。The bonding pads 2A and 2B are connected to each other and to an internal circuit by internal wiring.
この場合の障害発生確率は半減されるが、未だ十分な対
策とはいえない。Although the probability of failure occurring in this case is halved, this is still not a sufficient countermeasure.
（発明が解決しようとする問題点〕
従来の電源端子開放障害対策は、複数並列端子を設ける
程度のもので、集積回路の信頼性を保つ上で十分ではな
かった。(Problems to be Solved by the Invention) Conventional countermeasures against open power supply terminal failures have been limited to providing a plurality of parallel terminals, which has not been sufficient to maintain the reliability of integrated circuits.
上記問題点の解決は、アラーム信号端子と、複数の電源
端子と、同数の抵抗と、同数の基準電圧源と、同数の比
較器とを有し、各抵抗は各電源端子と内部回路間に接続
され１各比較器は、一方の入力端子が各電源端子に接続
され、他方の入力端子が各基準電圧源を介して、内部回
路と各抵抗との接続点に接続され、出力端子がアラーム
信号端子に接続されている端子開放検出回路付半導体装
置により達成される。The solution to the above problem is to have an alarm signal terminal, multiple power supply terminals, the same number of resistors, the same number of reference voltage sources, and the same number of comparators, and each resistor is connected between each power supply terminal and the internal circuit. Each comparator has one input terminal connected to each power supply terminal, the other input terminal connected to the connection point between the internal circuit and each resistor via each reference voltage source, and the output terminal connected to the alarm terminal. This is achieved by a semiconductor device with an open terminal detection circuit connected to a signal terminal.
本発明は複数の電源端子を設け、その内１本でも端子開
放が生じた場合にアラームを外部に出し。The present invention provides a plurality of power terminals, and sends an alarm to the outside if even one of the terminals becomes open.
他の装置でフェイルセーフの処置を行うようにしたもの
である。It is designed to perform fail-safe measures using other devices.
そのために、集積回路の動作に影啓を与えない程度の低
抵抗値（１Ω程度、またはそれ以下）を持つ検知用の抵
抗を各端子と内部回路間に挿入し。To this end, a detection resistor with a low resistance value (about 1Ω or less) that does not affect the operation of the integrated circuit is inserted between each terminal and the internal circuit.
各抵抗の両端の電圧効果を基準電圧と比較することによ
り開放を検知してアラームを出すようにしている。By comparing the voltage effect across each resistor with a reference voltage, an open circuit is detected and an alarm is issued.
第１図は本発明の一実施例を説明する半導体装置の電源
端子部の平面図である。FIG. 1 is a plan view of a power supply terminal portion of a semiconductor device illustrating an embodiment of the present invention.
この場合、 ＧＮＤ端子が２個の場合で、パッケージ側
のＧＮＤ端子１Δ、 ＩＢはチップ例のポンディングパ
ッド２Ａ、 ２Ｂとワイアボンディングで接続され。In this case, there are two GND terminals, and the GND terminals 1Δ and IB on the package side are connected to the bonding pads 2A and 2B of the chip example by wire bonding.
ポンディングパッド２Ａ、 ２Ｂはそれぞれ抵抗Ｒを介
して相互にＰ点で接続され、接続点Ｐより内部回路に接
続される。The bonding pads 2A and 2B are connected to each other via a resistor R at a point P, and are connected to an internal circuit from the connection point P.
比較器（、ｌＰ Ａ 、およびＣＭＰ Ｂは、一方の入
力端子がボンディングパソド２Ａ、 ２Ｂに接続され、
他方の入力端子がそれぞれ基準電圧源Ｖ、を介して前記
接続点Ｐに接続され、各出力端子がアラーム用ボンディ
ングパソド４に接続される。The comparators (1P A, and CMP B have one input terminal connected to the bonding pads 2A and 2B,
The other input terminals are each connected to the connection point P via a reference voltage source V, and each output terminal is connected to the alarm bonding pad 4.
アラーム信号端子３はアラーム用ボンディング≠〒＊バ
ッド４とワイヤボンディングされ、ここより外部にアラ
ーム信号を送り出す。The alarm signal terminal 3 is wire-bonded to the alarm bonding pad 4, from which an alarm signal is sent to the outside.
この場合１各抵抗Ｒに流れる電流をＩとすると。In this case, 1. Let I be the current flowing through each resistor R.
ＶＲ＜ＩＲ。VR<IR.
ｖＲ＞２ｒＲ。vR>2rR.
になるように１基準電圧ＶＲを選ぶ。Select one reference voltage VR so that
いま、 ＧＮＤ端子ＩＡ、またはＩＢのいずれかが開放
状態になると、 ＧＮＤ端子ＩＢ 、または１八側の抵
抗には２ＪＲの電圧効果が生し１比較器ＣＭＰ Ａ 。Now, when either GND terminal IA or IB becomes open, a voltage effect of 2JR occurs on the GND terminal IB or the resistor on the 18 side, and 1 comparator CMP A occurs.
およびＣＭＰ Ｂの出力信号は“Ｈ”より“Ｌ”に反転
し、アラーム信号を出す。The output signal of CMP B is inverted from "H" to "L" and an alarm signal is output.
アラーム信号はマイクロコンピュータに入力され２例え
ばインデイケータランプを点灯するようにする。The alarm signal is input to the microcomputer 2, which causes, for example, an indicator lamp to light up.
車載用集積回路においては、マイクロコンピュータはフ
ェイルセーフになるように使用されているので１本発明
はそのインクフェイス用の集積回路に適用すると制御系
全体の信頼度の向上が期待できる。In automotive integrated circuits, microcomputers are used in a fail-safe manner, so if the present invention is applied to integrated circuits for ink faces, it can be expected to improve the reliability of the entire control system.
以上説明したように本発明によれば、複数個の端子の内
、１個でも開放状態になれば外部にアラーム信号を出す
ことにより、集積回路の完全なフェイルセーフの対策が
可能となる。As explained above, according to the present invention, if even one of the plurality of terminals becomes open, an alarm signal is issued to the outside, thereby making it possible to completely fail-safe the integrated circuit.
第１図は本発明の一実施例を説明する半導体装置の電源
端子部の平面図。
第２図（１）、 （２）は従来の半導体装置の電源端子
を説明する平面図である。
図において。
ＩＡ、 ＩＢはＧＮＤ端子。
２Ａ、 ２ＢはＧＮＤ用ボンディングパノド。
３はアラーム信号端子。
４はアラーム用ポンディングパソド
賞＃！、側め図
第 １ 図
従未介］ｆ）図
第２ 仄FIG. 1 is a plan view of a power supply terminal portion of a semiconductor device illustrating an embodiment of the present invention. FIGS. 2(1) and 2(2) are plan views illustrating power supply terminals of a conventional semiconductor device. In fig. IA and IB are GND terminals. 2A and 2B are bonding panods for GND. 3 is the alarm signal terminal. 4 is the Alarm Ponding Pasodo Award #! , Side view, Figure 1, Figure 2, f) Figure 2,
Claims (1)
と、同数の基準電圧源と、同数の比較器とを有し、 各抵抗は各電源端子と内部回路間に接続され、各比較器
は、一方の入力端子が各電源端子に接続され、他方の入
力端子が各基準電圧源を介して、内部回路と各抵抗との
接続点に接続され、出力端子がアラーム信号端子に接続
されていることを特徴とする端子開放検出回路付半導体
装置。[Claims] It has an alarm signal terminal, a plurality of power supply terminals, the same number of resistors, the same number of reference voltage sources, and the same number of comparators, each resistor being connected between each power supply terminal and the internal circuit. Each comparator has one input terminal connected to each power supply terminal, the other input terminal connected to the connection point between the internal circuit and each resistor via each reference voltage source, and the output terminal connected to the alarm signal. A semiconductor device with an open terminal detection circuit, characterized in that the semiconductor device is connected to a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62314741A JPH01154546A (en) | 1987-12-10 | 1987-12-10 | Open terminal detecting circuit semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62314741A JPH01154546A (en) | 1987-12-10 | 1987-12-10 | Open terminal detecting circuit semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01154546A true JPH01154546A (en) | 1989-06-16 |
Family
ID=18057024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62314741A Pending JPH01154546A (en) | 1987-12-10 | 1987-12-10 | Open terminal detecting circuit semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01154546A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927528A (en) * | 1995-05-19 | 1997-01-28 | Sgs Thomson Microelectron Srl | Electronic device, manufacture of its electronic device and method of testing connectivity of bonding wire of electronicdevice |
| JP2008098889A (en) * | 2006-10-11 | 2008-04-24 | Mitsubishi Electric Corp | Semiconductor device |
| JP2012028786A (en) * | 2010-07-27 | 2012-02-09 | Robert Bosch Gmbh | Method for determining resistance between integrated circuit and contacting device of integrated circuit and corresponding contacting device of printed circuit board |
| JP2015035515A (en) * | 2013-08-09 | 2015-02-19 | 三菱電機株式会社 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5734355A (en) * | 1980-08-06 | 1982-02-24 | Tektronix Inc | Integrated circuit device |
| JPS57180140A (en) * | 1981-04-20 | 1982-11-06 | Control Data Corp | Mutual connecting defect detector for logic circuit |
-
1987
- 1987-12-10 JP JP62314741A patent/JPH01154546A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5734355A (en) * | 1980-08-06 | 1982-02-24 | Tektronix Inc | Integrated circuit device |
| JPS57180140A (en) * | 1981-04-20 | 1982-11-06 | Control Data Corp | Mutual connecting defect detector for logic circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927528A (en) * | 1995-05-19 | 1997-01-28 | Sgs Thomson Microelectron Srl | Electronic device, manufacture of its electronic device and method of testing connectivity of bonding wire of electronicdevice |
| US5909034A (en) * | 1995-05-19 | 1999-06-01 | Sgs-Thomson Microrlectronics S.R.L. | Electronic device for testing bonding wire integrity |
| JP2008098889A (en) * | 2006-10-11 | 2008-04-24 | Mitsubishi Electric Corp | Semiconductor device |
| JP2012028786A (en) * | 2010-07-27 | 2012-02-09 | Robert Bosch Gmbh | Method for determining resistance between integrated circuit and contacting device of integrated circuit and corresponding contacting device of printed circuit board |
| JP2015035515A (en) * | 2013-08-09 | 2015-02-19 | 三菱電機株式会社 | Semiconductor device |
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