JPH01146362A - Manufacture of hetero junction bipolar transistor - Google Patents
Manufacture of hetero junction bipolar transistorInfo
- Publication number
- JPH01146362A JPH01146362A JP30655587A JP30655587A JPH01146362A JP H01146362 A JPH01146362 A JP H01146362A JP 30655587 A JP30655587 A JP 30655587A JP 30655587 A JP30655587 A JP 30655587A JP H01146362 A JPH01146362 A JP H01146362A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- collector
- conductivity type
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 125000005842 heteroatom Chemical group 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 239000000370 acceptor Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 125000002524 organometallic group Chemical group 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はへテロ接合バイポーラトラジスタの製造方法に
関し、特に化合物半導体等のへテロ接合を利用したヘテ
ロ接合バイポーラトランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a heterojunction bipolar transistor, and more particularly to a method for manufacturing a heterojunction bipolar transistor using a heterojunction such as a compound semiconductor.
近年、半導体装置は高積化・高速化に向けて精力的な研
究開発が進められている。特に、化合物半導体等のへテ
ロ接合を利用したヘテロ接合バイポーラトランジスタ（
以降ＨＢＴと称す）は、エミッタ注入効率が高く、高利
得でかつ高速化が期待され、次世代の半導体素子として
注目されている。このＨＢＴは分子線エピタキシャル成
長法、有機金属熱分解気相成長法等による化合物半導体
の薄膜多層結晶成長技術の進展に伴い、その実現が可能
となった。In recent years, vigorous research and development has been carried out on semiconductor devices to increase their density and speed. In particular, we focus on heterojunction bipolar transistors that utilize heterojunctions such as compound semiconductors (
HBTs (hereinafter referred to as HBTs) are expected to have high emitter injection efficiency, high gain, and high speed, and are attracting attention as next-generation semiconductor devices. This HBT has become possible with the advancement of compound semiconductor thin film multilayer crystal growth technology using molecular beam epitaxial growth, organometallic pyrolysis vapor phase epitaxy, and the like.
ＨＢ Ｔにおいて高速・高周波特性を表わす一つの指標
である最大発振周波数ｆ ｆｆ１ａｘは次式で示される
。The maximum oscillation frequency fff1ax, which is one index representing high-speed/high-frequency characteristics in HBT, is expressed by the following equation.
ｆｍａｘ＝μゴ／８πＲａ （Ｃａｃ＋ Ｃｂｅ）
−（１）ここで、それぞれｆＴは電流利得遮断周波数、
Ｒ８はベース抵抗、ＣＢＣはトランジスタの能動領域に
おけるベース・コレクタ接合容量、ｃｂｃはトランジス
タの外部領域におけるベース・コレクタ寄生接合容量で
ある。（１）式で明らかなように、ＨＢＴめ高速動作を
実現する一つの手段として、ベース・コレクタ寄生容量
ｃｂｃあるいはベース抵抗Ｒ８を極力小さくする必要が
ある。これを実現するために、従来はトランジスタが構
成される半絶縁性基板に対し、基板の表面側から外部ベ
ース領域に選択的に高エネルギーで酸素イオン注入し、
ベース・コレクタ接合部を半絶縁化することによりベー
ス・コレクタ寄生接合容量Ｃｂｃを低減するとともに、
更に外部ベース領域に、該ベースと同じ導電型を形成す
るドーパントをイオン注入し、その後の熱処理により該
ドーパントを活性化して、外部ベース層のシート抵抗の
低減と、その後に形成されるベース電極とのコンタクト
抵抗の低減とをはかることによりベース抵抗ＲＢを低減
していた。fmax=μgo/8πRa (Cac+Cbe)
-(1) where fT is the current gain cutoff frequency,
R8 is the base resistance, CBC is the base-collector junction capacitance in the active region of the transistor, and cbc is the base-collector parasitic junction capacitance in the external region of the transistor. As is clear from equation (1), as a means of realizing high-speed operation of the HBT, it is necessary to minimize the base-collector parasitic capacitance cbc or the base resistance R8. To achieve this, conventionally, oxygen ions were selectively implanted at high energy into the external base region from the surface side of the substrate into the semi-insulating substrate on which the transistor was constructed.
By making the base-collector junction semi-insulating, the base-collector parasitic junction capacitance Cbc is reduced, and
Furthermore, a dopant forming the same conductivity type as the base is ion-implanted into the external base region, and the dopant is activated by subsequent heat treatment to reduce the sheet resistance of the external base layer and to form a base electrode that is subsequently formed. The base resistance RB was reduced by reducing the contact resistance.
第２図はへテロ接合としてＧ ａ Ａ ｓ ／ Ａ ｊ
７Ｇ ａＡｓを用いた従来のＨＢＴの一例の断面図であ
る。Figure 2 shows G a A s / A j as a heterojunction.
1 is a cross-sectional view of an example of a conventional HBT using 7G aAs.
半絶縁性基板、１上にｎ型ＧａＡｓから成るコレクタ層
２、ｐ型ＧａＡｓから成るベース層４′、ｎ型ＡｆＧａ
Ａｓから成るエミッタ層６′が形成されている。このエ
ミッタ層６′及びこの直下のベース層４′及びコレクタ
層２は、トランジスタの能動領域を構成し、この部分で
実際のトランジスタ動作を呈する。更に、この能動領域
の外部領域では、基板の表面側から選択的に、酸素イオ
ン及びｐ型の導電性を示すドーパント（例えばＭｇ）を
順次イオン注入し熱処理することにより、イオン注入絶
縁層３′及びｐ型ＧａＡｓから成るコンタクト用のベー
ス層４ａ’が形成されている。かかる構成により、能動
領域の外部領域におけるベース・コレクタ寄生接合容１
ｃｂｃを低減するとともに、コンタクト用のベースＮｉ
４ ａ ’のシート抵抗の低減とベース電極８とのコ
ンタクト抵抗を下げてベース抵抗Ｒａを低減していた。A semi-insulating substrate 1 has a collector layer 2 made of n-type GaAs, a base layer 4' made of p-type GaAs, and an n-type AfGa
An emitter layer 6' made of As is formed. This emitter layer 6' and the base layer 4' and collector layer 2 immediately below it constitute the active region of the transistor, and this portion exhibits actual transistor operation. Further, in a region outside the active region, oxygen ions and a dopant exhibiting p-type conductivity (for example, Mg) are sequentially implanted selectively from the surface side of the substrate and heat-treated to form an ion-implanted insulating layer 3'. A contact base layer 4a' made of p-type GaAs is formed. With such a configuration, the base-collector parasitic junction capacitance 1 in the region outside the active region is
In addition to reducing cbc, base Ni for contact
The base resistance Ra was reduced by reducing the sheet resistance of 4a' and the contact resistance with the base electrode 8.
以上の従来のＨＢＴにおいて、コレクタ層２とコンタク
ト用のベース層４ａ’との間に注入される酸素イオン及
びベース層４ａ’の形成を目的として注入されるｐ型の
ドーパントはベース層４ａ′内に結晶欠陥を誘起する。In the conventional HBT described above, the oxygen ions implanted between the collector layer 2 and the contact base layer 4a' and the p-type dopant implanted for the purpose of forming the base layer 4a' are in the base layer 4a'. induces crystal defects.
この結晶欠陥は、熱処理によって完全に除去するのが困
難であるので、この欠陥よってベース層４ａ′のキャリ
ヤがトラップされて、ベース抵抗Ｒａの充分に低減する
ことが困難であった。しかも、前述の熱処理工程は、能
動領域におけるエミッタ、ベース及びコレクタ層６’
、４’及び２のそれぞれの不純物並びにコンタクト用の
ベース層４ａ’にイオン注入された不純物を隣接する層
に拡散させ、不純物の濃度分布を変化させていた。特に
、ベース層４′及び４ａ’の不純物がエミッタ層６′に
拡散することにより、再結合電流が増加しエミッタ注入
効率を大幅に低下させていた。Since this crystal defect is difficult to completely remove by heat treatment, carriers in the base layer 4a' are trapped by the defect, making it difficult to sufficiently reduce the base resistance Ra. Moreover, the above-mentioned heat treatment process is performed on the emitter, base and collector layers 6' in the active region.
, 4' and 2 as well as the impurities ion-implanted into the contact base layer 4a' are diffused into adjacent layers to change the impurity concentration distribution. In particular, when the impurities in the base layers 4' and 4a' diffuse into the emitter layer 6', recombination current increases and emitter injection efficiency is significantly reduced.
本発明の目的は、ベース抵抗の増加とエミッタ注入効率
の低下とを防止した特性の優れたベテロ接合バイポーラ
トランジスタの製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a betajunction bipolar transistor with excellent characteristics that prevents an increase in base resistance and a decrease in emitter injection efficiency.
本発明のへテロ接合バイポーラトランジスタの製造方法
は、第１導電型のコレクタ層上に該コレクタ層と格子整
合した半絶縁性の半導体層及び該半導体層と格子整合し
た第２導電型の第１ベース層を順次形成する工程、前記
第１ベース層の所定の位置に窓を開口し語意の下に前記
コレクタ層に連らなる第１導電型の能動領域を形成する
工程並びに該能動領域及び前記第１ベース層上にこれら
と格子整合した第２導電型の第２ベース層及び第１導電
型のエミッタ層を順次形成する工程を含み、前記コレク
タ層と前記第１及び第２ベース層との間に半絶縁性の前
記半導体層からなる分離領域を形成する。The method for manufacturing a heterojunction bipolar transistor of the present invention includes a semi-insulating semiconductor layer on a collector layer of a first conductivity type, which is lattice-matched to the collector layer, and a first semiconductor layer of a second conductivity type, which is lattice-matched to the semiconductor layer. a step of sequentially forming a base layer, a step of opening a window at a predetermined position of the first base layer and forming an active region of a first conductivity type connected to the collector layer; The step of sequentially forming a second base layer of a second conductivity type and an emitter layer of a first conductivity type that are lattice-matched on the first base layer; An isolation region made of the semi-insulating semiconductor layer is formed therebetween.
本発明においては、コンタクト用のベース層とコンタク
ト層の間に、これらの各層と格子整合した半絶縁性半導
体材料からなる半絶縁層を設けているため、能動領域以
外のベース・コレクタ寄生接合容量が、該半絶縁層が厚
くなるに応じて大幅に低減できる。更に、能動領域のベ
ース層に接続したコンタクト用のベース層は、その不純
物濃度と厚みをコントロールすることによって抵抗値を
大幅に低減することができる。しかも、コレクタ層の能
動領域の部分を形成した後にエピタキシャル成長法で、
ベース層を形成しているため、イオン注入及びそれにと
もなう熱処理工程が不要となりベース層内の結晶欠陥の
発生やＨＢＴの特性を劣化させる不純物の拡散を防止す
ることができる。In the present invention, a semi-insulating layer made of a semi-insulating semiconductor material that is lattice-matched to each of these layers is provided between the contact base layer and the contact layer, so that the base-collector parasitic junction capacitance outside the active area is reduced. However, this can be significantly reduced as the thickness of the semi-insulating layer increases. Furthermore, the resistance value of the contact base layer connected to the base layer of the active region can be significantly reduced by controlling its impurity concentration and thickness. Furthermore, after forming the active region portion of the collector layer, epitaxial growth is performed.
Since the base layer is formed, ion implantation and the accompanying heat treatment process are unnecessary, and generation of crystal defects in the base layer and diffusion of impurities that degrade the characteristics of the HBT can be prevented.
以下、本発明の実施例をＡ ｅ Ｇ ａ Ａ ｓ ／
Ｇ ａＡｓのｎｐｎ型ＨＢＴを例に取り図面を参照して
説明する。Hereinafter, examples of the present invention will be described as A e Ga As /
A GaAs npn-type HBT will be taken as an example and explained with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を製造工程順
に説明する断面図である。FIGS. 1(a) to 1(d) are cross-sectional views illustrating an embodiment of the present invention in the order of manufacturing steps.
この実施例では、まず、第１図（ａ）に示すように、Ｇ
ａＡｓから成る半絶縁性基板１上に、ドナー（例えばＳ
ｉ）をドープしたｎ型ＧａＡｓから成る厚さ０．５〜１
．０μｍのコレクタ層２、コレクタ層２と同じ材料でし
かもドナーもしくはアクセプタ等の不純物をドープして
いない半絶縁性のＧａＡｓから成る厚さ０．２〜０．５
μｍの半絶縁層３、更に、アクセプタ（例えばＢｅ）を
高濃度にドープしたｎ型ＧａＡｓから成る厚さ数百〜数
千人程度の接続用のベース層４ａを分子線エピタキシャ
ル成長法あるいは有機金属熱分解気相成長法等を用いて
順次成長する。In this example, first, as shown in FIG.
A donor (for example, S) is placed on a semi-insulating substrate 1 made of aAs.
i) consisting of n-type GaAs doped with a thickness of 0.5 to 1
．． 0 μm collector layer 2, made of semi-insulating GaAs made of the same material as the collector layer 2 but not doped with impurities such as donors or acceptors, with a thickness of 0.2 to 0.5
A semi-insulating layer 3 with a thickness of μm, and a base layer 4a for connection several hundred to several thousand thick made of n-type GaAs doped with a high concentration of acceptor (e.g. Be) are formed by molecular beam epitaxial growth or organometallic heat treatment. Growth is performed sequentially using a decomposition vapor phase growth method or the like.
次に、第１図（ｂ）に示すように、Ｓ ｉ ０２やＳｉ
３Ｎ４等の絶縁物からなる所定のパターンの開口部を備
えたマスク層５を形成した後マスク層５を用いて、ベー
ス層４ａの露出部分をウェットエツチングあるいはドラ
イエツチング等の周知の方法で選択的に除去し半絶縁層
３を露出し、更に基板の表面上部から半絶縁層３の露出
部に例えばＳｉをイオン注入すると共にその後の熱処理
によってこの不純物を活性化して、コレクタＭ２に至る
コレクタ層２と同じ導電型のｎ型能動領域２ａを形成す
る。ここで、イオン注入の条件としては、例えば半絶縁
層３の厚みが０．５μｍであれば、Ｓｉイオンをドーズ
量２Ｘ１０１２ｃｍ−２、加速エネルギー２８０ｋｅＶ
で注入し、その後８００℃、５秒間の熱処理を行う。そ
の結果、約５Ｘ１０１６ｃｍ−’のキャリア濃度を有す
るｎ型の能動領域２ａが形成され、この能動領域２ａが
トランジスタのコレクタの能動領域として機能する。Next, as shown in FIG. 1(b), Si 02 and Si
After forming a mask layer 5 with openings in a predetermined pattern made of an insulator such as 3N4, the exposed portions of the base layer 4a are selectively etched using a well-known method such as wet etching or dry etching using the mask layer 5. The semi-insulating layer 3 is removed to expose the semi-insulating layer 3, and ions of, for example, Si are implanted into the exposed portion of the semi-insulating layer 3 from the upper surface of the substrate, and the impurities are activated by subsequent heat treatment to form the collector layer 2 leading to the collector M2. An n-type active region 2a of the same conductivity type is formed. Here, the conditions for ion implantation are, for example, if the thickness of the semi-insulating layer 3 is 0.5 μm, Si ions are implanted at a dose of 2×10 12 cm −2 and an acceleration energy of 280 keV.
After that, heat treatment is performed at 800° C. for 5 seconds. As a result, an n-type active region 2a having a carrier concentration of about 5.times.10.sup.16 cm-' is formed, and this active region 2a functions as the active region of the collector of the transistor.
続いて、第１図（ｃ）に示すように、マスク層５を除去
した後、アクセプタ（例えばＢｅ）をドープしたｎ型Ｇ
ａＡｓから成る厚さ数百人〜数千人程度のベース層４、
ドナー（例えばＳｉ）をドープしたｎ型のＡＩ！ＧａＡ
ｓからなる数千人の厚さのエミッタ層６を順次エピタキ
シャル成長法で形成する。Subsequently, as shown in FIG. 1(c), after removing the mask layer 5, an n-type G doped with an acceptor (for example, Be) is formed.
A base layer 4 made of aAs and having a thickness of several hundred to several thousand layers,
n-type AI doped with a donor (e.g. Si)! GaA
An emitter layer 6 having a thickness of several thousand layers made of S is sequentially formed by epitaxial growth.
最後に、第１図（ｄ）に示すように、周知の方法でエミ
ッタ層６、ベース層４及び４ａ並びに半絶縁層３を順次
エツチングして所定部分を露出し、ｎ型ＧａＡｓに対し
てオーミーツク接触する金属（例えばＡｕＧｅ／Ｎｉ）
がら成るエミッタ電極９及びコレクタ電極７、更にｎ型
ＧａＡｓに対しオーミック接触する金属（例えばＡｕＺ
ｎ。Finally, as shown in FIG. 1(d), the emitter layer 6, base layers 4 and 4a, and semi-insulating layer 3 are sequentially etched using a well-known method to expose predetermined portions and create an ohm-like structure for the n-type GaAs. Metal in contact (e.g. AuGe/Ni)
Emitter electrode 9 and collector electrode 7 consisting of
n.
ＡｕＣｒ、ＡｕＭｎ等）から成るベース電極８を形成し
て本発明の一実施例によるＨＢＴが完成する。A base electrode 8 made of (AuCr, AuMn, etc.) is formed to complete an HBT according to an embodiment of the present invention.
以上説明したように本発明では、コレクタ層と接続用ベ
ース層との間に半絶縁性半導体材料からなる半絶縁層を
設けてこれによって絶縁分漏するため、ベース・コレク
タ寄生容量を大幅に低減でき、しかもすくなくとも従来
方法のようなイオン注入及びその後の熱処理工程に伴う
、ベース層中の結晶欠陥の発生及び不純物の不必要な拡
散によるベース抵抗の増加及びエミッタ注入効率の低下
も防止できるので、高速・高周波特性の非常に良好なＨ
′ＢＴを実現することができるという効果がある。As explained above, in the present invention, a semi-insulating layer made of a semi-insulating semiconductor material is provided between the collector layer and the connection base layer, and this causes insulation leakage, thereby significantly reducing the base-collector parasitic capacitance. Moreover, at least it is possible to prevent an increase in base resistance and a decrease in emitter implantation efficiency due to the generation of crystal defects in the base layer and unnecessary diffusion of impurities, which are caused by ion implantation and subsequent heat treatment steps as in conventional methods. H with very good high speed and high frequency characteristics
'BT can be realized.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの断面図、第２図は従来のＨＢＴの一例の断面図であ
る。
１・・・半絶縁性基板、２・・・コレクタ層、２ａ・・
・能動領域、３・・・半絶縁層、３′・・・絶縁層、４
゜４ａ、４ａ’・・・ベース層、５・・・マスク層、６
゜６′・・・エミッタ層、７・・・コレクタ電極、８・
・・ベース電極、９・・・エミッタ電極。FIGS. 1(a) to 1(d) are cross-sectional views for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional HBT. 1... Semi-insulating substrate, 2... Collector layer, 2a...
- Active region, 3... Semi-insulating layer, 3'... Insulating layer, 4
゜4a, 4a'...Base layer, 5...Mask layer, 6
゜6'... Emitter layer, 7... Collector electrode, 8...
...Base electrode, 9...Emitter electrode.
Claims (1)
した半絶縁性の半導体層及び該半導体層と格子整合した
第２導電型の第１ベース層を順次形成する工程、前記第
１ベース層の所定の位置に窓を開口し該窓の下に前記コ
レクタ層に連らなる第１導電型の能動領域を形成する工
程並びに該能動領域及び前記第１ベース層上にこれらと
格子整合した第２導電型の第２ベース層及び第１導電型
のエミッタ層を順次形成する工程を含み、前記コレクタ
層と前記第１及び第２ベース層との間に半絶縁性の前記
半導体層からなる分離領域を形成することを特徴とする
ヘテロ接合バイポーラトランジスタの製造方法。a step of sequentially forming, on a collector layer of a first conductivity type, a semi-insulating semiconductor layer lattice-matched with the collector layer and a first base layer of a second conductivity type lattice-matched with the semiconductor layer; a step of opening a window at a predetermined position of the window and forming an active region of a first conductivity type connected to the collector layer under the window; a step of sequentially forming a second conductivity type second base layer and a first conductivity type emitter layer, and separating the collector layer and the first and second base layers by the semi-insulating semiconductor layer; A method for manufacturing a heterojunction bipolar transistor, comprising forming a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30655587A JPH01146362A (en) | 1987-12-02 | 1987-12-02 | Manufacture of hetero junction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30655587A JPH01146362A (en) | 1987-12-02 | 1987-12-02 | Manufacture of hetero junction bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01146362A true JPH01146362A (en) | 1989-06-08 |
Family
ID=17958457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30655587A Pending JPH01146362A (en) | 1987-12-02 | 1987-12-02 | Manufacture of hetero junction bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01146362A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61294860A (en) * | 1985-06-21 | 1986-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS6249656A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
-
1987
- 1987-12-02 JP JP30655587A patent/JPH01146362A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61294860A (en) * | 1985-06-21 | 1986-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS6249656A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
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