JPS62221151A - Hetero junction bipolar transistor and manufacture thereof - Google Patents
Hetero junction bipolar transistor and manufacture thereofInfo
- Publication number
- JPS62221151A JPS62221151A JP6412886A JP6412886A JPS62221151A JP S62221151 A JPS62221151 A JP S62221151A JP 6412886 A JP6412886 A JP 6412886A JP 6412886 A JP6412886 A JP 6412886A JP S62221151 A JPS62221151 A JP S62221151A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- type
- emitter
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 125000005842 heteroatom Chemical group 0.000 title description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 69
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 230000005476 size effect Effects 0.000 abstract description 9
- 238000005215 recombination Methods 0.000 description 13
- 230000006798 recombination Effects 0.000 description 13
- 230000003321 amplification Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002609 medium Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000001963 growth medium Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はヘテロ接合バイポーラトランジスタ及びその製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.
エミッタ層またはコレクタ層にベース層よシも禁制帯幅
の大きい半導体全相いるヘテロ接合バイポーラトランジ
スタは大きい電流増幅率、低いベース抵抗、ベース押し
出し効果の抑制等の特長を有するものとして注目されて
いる。エミッタサイズが比較的大きいヘテロ接合バイポ
ーラトランジスタでは、これらの長所が生かされ、大き
い電流増幅率が得られている。ところがエミッタサイズ
が小さくなると電流増幅率が著しく減少する。いわゆる
エミッタサイズ効果が見られ、従来から問題になってい
る。以下にこの問題をエミツタ層にＡｌＧａＡｓ、ベー
ス層とコレクタ層にＧａＡｓを用いた場合上例に挙げて
１図を用いて説明する。Heterojunction bipolar transistors, in which the emitter layer or collector layer is made entirely of semiconductors with large forbidden band widths as well as the base layer, are attracting attention as having features such as a large current amplification factor, low base resistance, and suppressed base extrusion effect. . Heterojunction bipolar transistors with relatively large emitter sizes take advantage of these advantages and achieve large current amplification factors. However, as the emitter size becomes smaller, the current amplification factor decreases significantly. A so-called emitter size effect is observed and has been a problem for some time. This problem will be explained below with reference to FIG. 1, taking as an example the case where AlGaAs is used for the emitter layer and GaAs is used for the base layer and collector layer.
第４図はヘテロ接合バイポーラトランジスタの開発初期
に見られた構造である５ ４１はｎ生型Ｇ ａ Ａ ｓ
基板であり、この上にｎ型Ｇ ａ Ａ ｓコレクタ層４
２、Ｐ型Ｇ ａ Ａ ｓベース庖４３．ｎ型ＡｌＧａＡ
ｓエミツタ層４４が順次成長形成されている。エミツタ
層の外側はメサエッチングされ、霧出したベースＷＩ４
３にベース電極４６が形成されている。Figure 4 shows the structure seen at the early stage of the development of heterojunction bipolar transistors. 5 41 is an n-type Ga As
A substrate, on which an n-type GaAs collector layer 4 is formed.
2. P type Ga As base plate 43. n-type AlGaA
The s-emitter layer 44 is sequentially grown and formed. The outside of the emitter layer is mesa-etched, and the base WI4 is misted out.
A base electrode 46 is formed at 3.
４７はエミッタ電極である。47 is an emitter electrode.
この様な構造では露出したベース層の表面で再結合が盛
んに起り、一定量のベース電流が生じる。In such a structure, recombination occurs actively on the exposed surface of the base layer, and a certain amount of base current is generated.
エミッタサイズが小さくなるとこの表面再結合に起因す
るベース電流の全ベース電流に対する寄与が急激に増加
し、電流増幅率ｈ Ｆ Ｅが減少する。As the emitter size becomes smaller, the contribution of the base current due to this surface recombination to the total base current increases rapidly, and the current amplification factor h FE decreases.
（Ｎａｋａｊ ｉｍａ Ｏ，、Ｎａｇａｔａ Ｋ、 、
Ｉｔｏル、 ｌ５ｈｉｂａｓｈｉ Ｔ。(Nakajima O, Nagata K, ,
Itol, l5hibashi T.
ａｎｄ Ｓｕｇｅｔａ Ｔ、 ” Ｅｍｉ ｔｔｅｒ−
Ｂａｓｅ Ｊｕｎｃｔｉｏｎ Ｓｉ ｊｅＥｆｆｅｃｔ
ｏｎ Ｃｕｒｒｏｎｔ Ｇａ１ｎ Ｈｆｅ ｏｆ Ａ
！Ｊ３ａＡｓ／ＱａＡ５Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ
Ｂｉｐｏｔａｒ Ｔｒａｎｓｉｓｔｏｒｓ ”、 Ｊ
ａｐａｎｅｓｅＪ、 ｏｆ Ａｐｐｔ−Ｐｈｙｏ・、２
４ｐ−Ｌ５９６（１９８５））すなわち、仮りに表面再
結合に起因する一定量のベース電流ｉＩｏとおき、真性
ベース領域で発生するベース電流をＸＪＢ （ただしＸ
はエミッター幅）。and Sugeta T.
Base Junction Si jeEffect
on Current Ga1n Hfe of A
! J3aAs/QaA5Heterojunction
Bipotar Transistors”, J
apaneseJ, of Appt-Phyo・, 2
4p-L596 (1985)) In other words, suppose that a fixed amount of base current iIo due to surface recombination is set, and the base current generated in the intrinsic base region is XJB (where X
is the emitter width).
コレクタ電流をｘＪｃとおくと、電流増幅率ｈ？に−１
゜
の逆数＋＋ｙｌ＝ＪＢ／Ｊｃ＋Ｉｏ／１０Ｃ−Ｊｃ）と
表わされ、エミツタ幅が小さくなるとｈｒ篇は減少する
ことがわかる。If the collector current is xJc, the current amplification factor h? ni-1
It is expressed as the reciprocal of ++yl=JB/Jc+Io/10C-Jc), and it can be seen that the hr decreases as the emitter width becomes smaller.
第５図は最近よく採用されるようになっ之構造で、エミ
ッタ領域の外側にＺｎ拡散やＭｇｔたはＢｅなどのイオ
ン注入により外部ベース領域となる低抵抗のＰ生型層４
９を形成したものである。４５はベース・コレクタ間を
分離する九めの高抵抗層である。エミッタ領域には電極
とのオーミック接触をよくするために表面にｎ生型Ｇａ
Ａｓ層４８ｔ−設けである。、第４図の構造ではベース
電極４６と真性トランジスタ領域の間の寄生抵抗が太き
かつ念ので、これを改善するために第５図の構造が考え
られた。Figure 5 shows a structure that has recently become popular, in which a low-resistance P-type layer 4 is formed outside the emitter region to become an external base region by Zn diffusion or ion implantation of Mgt or Be.
9 was formed. 45 is the ninth high resistance layer separating the base and collector. In the emitter region, there is n-type Ga on the surface to improve ohmic contact with the electrode.
An As layer 48t is provided. In the structure shown in FIG. 4, the parasitic resistance between the base electrode 46 and the intrinsic transistor region is large, so the structure shown in FIG. 5 was devised to improve this problem.
ところでこの構造では外部ベース領域４９ｔ？形成する
。拡散あるいはイオン注入工程でダメージが導入され、
多数の発生・再結合中心が外部ベース領域中に生じるた
めに、一定量のベース−電流が外部ベース領域で発生す
る。従って前述の例と同様にエミッタサイズが小さくな
ると電流増幅率ｈｐｘが減少する。By the way, in this structure, the external base area 49t? Form. Damage is introduced during the diffusion or ion implantation process,
Due to the large number of generation and recombination centers occurring in the extrinsic base region, a certain amount of base-current is generated in the extrinsic base region. Therefore, as in the previous example, as the emitter size decreases, the current amplification factor hpx decreases.
ところで、第５図の構造のヘテロ接合バイポーラトラン
ジスタを２次元シミュレーションで解析した結果次のこ
とが明らかになった。第３図は第５図の１点鎖線に沿っ
てホール濃度、電子濃度。By the way, as a result of analyzing the heterojunction bipolar transistor having the structure shown in FIG. 5 by two-dimensional simulation, the following was clarified. Figure 3 shows the hole concentration and electron concentration along the dashed line in Figure 5.
単位時間あたりの再結合率がどのように変化しているか
をグラフに表わしたものである。ホール濃度は外部ベー
ス領域でほぼ一定で、コレクタ領域で急激に減少する。This graph shows how the recombination rate changes per unit time. The hole concentration is approximately constant in the extrinsic base region and decreases rapidly in the collector region.
電子濃度は外部ベース領域のＡ Ｌ Ｇ ａ Ａ ｓ層
では小さいが、外部ベース領域のＧａＡｓ層で急激に増
加し、コレクタ層でさらに増加する。ところで単位時間
あたシの再結合率Ｕは次式で表わされる。ただし４Ｔｐ
とＴｎはそれぞれホールと電子の寿命、ｐはホール濃度
ｎは電子濃度、ｎｉは真性電子濃度、ｎｏとｐｏはそれ
ぞれ捕獲中心準位に換算した熱平衡電子・ホール濃度で
ある。この式からＴｐ（！−Ｔｎが小さく。The electron concentration is small in the A L Ga As layer of the extrinsic base region, but increases rapidly in the GaAs layer of the extrinsic base region, and further increases in the collector layer. By the way, the recombination rate U per unit time is expressed by the following equation. However, 4Tp
and Tn are the lifetimes of holes and electrons, respectively, p is the hole concentration, n is the electron concentration, ni is the intrinsic electron concentration, and no and po are the thermal equilibrium electron and hole concentrations converted to the trap center level, respectively. From this equation, Tp(!-Tn is small.
Ｐｎ積が大きいほど単位時間あたｐの再結合率が大きい
ことがわかる。計算した結果は第３図の［Ｃ）であり、
外部ベース領域にあるＧ ａ Ａ ｓ層で主に再結合が
生じていることがわかった。It can be seen that the larger the Pn product, the higher the recombination rate of p per unit time. The calculated result is [C] in Figure 3,
It was found that recombination mainly occurred in the Ga As layer in the external base region.
以上の結果から、ダメージが導入されている外部ベース
領域中にあるＧ ａ Ａ ｓ層の体積が少ないほどエミ
ッタサイズ効果が減少することが期待される。From the above results, it is expected that the emitter size effect decreases as the volume of the GaAs layer in the external base region into which damage is introduced decreases.
本発明の目的は上述したような従来の問題点を解決し、
エミッタサイズ効果が小さいヘテロ接合バイポーラトラ
ンジスタ及びその製造方法を提供することを目的とする
。The purpose of the present invention is to solve the above-mentioned conventional problems,
It is an object of the present invention to provide a heterojunction bipolar transistor with a small emitter size effect and a method for manufacturing the same.
本発明によるヘテロ接合バイポーラトランジスタの概要
を図面を用いて説明する。The outline of the heterojunction bipolar transistor according to the present invention will be explained using the drawings.
第１Ｍは本発明の構造の代表的な例を模式的に表わした
ものである。図中１１はたとえば半絶縁性Ｇ ａ Ａ
ｓ基板のような基板、１２はたどえばｎ＋型ＧａＡｓ層
、１３はたとえばｎ型Ｇ ａ Ａ ｓ層でこれら２つの
層がコレクタとなる第１導電型の第１半導体層である。1M schematically represents a typical example of the structure of the present invention. In the figure, 11 is, for example, a semi-insulating G a A
A substrate such as an s-substrate, 12 is an n+ type GaAs layer, and 13 is, for example, an n-type GaAs layer, and these two layers are a first conductivity type first semiconductor layer serving as a collector.
１４はたとえばＰ十型ＧａＡｓ層のようなベースとなる
第２導電型の第２半導体層。14 is a second semiconductor layer of a second conductivity type serving as a base, such as a P-type GaAs layer.
１５はたとえばｎ型ＡｌＧａＡｓ、１６はたとえばｎ＋
型ＧａＡｓでこれら２つの層がエミッタとなる第１導電
型の第３半導体層である。Ｊ７はＰ中型外部ベース領域
で、１４のＰ中型Ｇ ａ Ａ ｓ層にかろうじて達っす
るように形成されている。１８はベース電極でＡ Ｌ
Ｇ ａ Ａ ｓ層に接している。１９はベース・コレク
タ間を分離するための高抵抗層１２０はエミッタ電極、
２１はコレクタ電極である。15 is, for example, n-type AlGaAs, and 16 is, for example, n+
These two layers are the third semiconductor layer of the first conductivity type, which is GaAs type and serves as an emitter. J7 is a P medium-sized external base region, which is formed so as to barely reach the 14 P medium-sized Ga As layers. 18 is the base electrode A L
It is in contact with the GaAs layer. 19 is a high resistance layer 120 for separating the base and collector, an emitter electrode;
21 is a collector electrode.
このようなヘテロ接合バイポーラトランジスタを製造す
る本発明の方法は半絶縁性基板１１にｎ＋型Ｇ ａ Ａ
ｓ層１２．ｎ型ＧａＡｓ層１３．Ｐ中型Ｇ ａ Ａ
ｓ層１４．ｎ型Ａ ｔ Ｇ ａ Ａ ｓ層１５．ｎ＋−
ＧａＡｓ層１６１”順次エピタキシャル成長したウェー
ハを用いる。エミッタ領域の周囲のｎ ＋ Ｇ ａ Ａ
ｓ層１６を除去（、り（７）ち、ｎ −Ａ ｔＧ ａ
Ａ ｓ層１７上から不純物ｔ＝ｐ＋−′−ＧａＡｓ層
１４にちょうど達つするようにイオン注入して、イオン
注入外部ベース領域１７全形成し、ｎ Ａ ｔＧ ａ
Ａ ｓから成る外部ベース領域上にベース電極１８を
設ける。The method of the present invention for manufacturing such a heterojunction bipolar transistor includes an n+ type Ga A on a semi-insulating substrate 11.
s layer 12. n-type GaAs layer 13. P medium size G a A
s layer 14. n-type AtGaAs layer 15. n+-
A wafer is used in which a 161" GaAs layer is epitaxially grown sequentially. n + Ga A around the emitter region.
Removal of the s layer 16 (, Ri (7), n -A tG a
Ions are implanted from above the A s layer 17 so as to just reach the impurity t=p+-'-GaAs layer 14 to form the entire ion-implanted external base region 17.
A base electrode 18 is provided on the external base region consisting of As.
次に本発明による効果全第２図を参照して説明する。第
２図は第１図の構造のヘテロ接合バイポーラトランジス
タを２次元シミュレーシ冒ンで解析し、第１図の１点鎖
線に沿ってホール濃度、電子濃度、単位時間あたりの再
結合率をグラフに表わしたものである。従来構造につい
て同様のプロット？し之結果、第３図と比較すると、ホ
ール濃度と電子濃度はほぼ同様の変化をしているが、単
位時間あたりの再結合率は非常に異った変化をしている
ことがわかる５発生再結合中心が大量に存在しているイ
オン注入外部ベース領域は主にｋＡＧ ａ Ａ ｓ層内
に限られているので％巣位時間あたりの再結合率が大き
いのは、イオン注入外部ベース領域中にわずかに存在す
るＧ ａ Ａ ｓ層内のみである。従って、外部ベース
領域で発生する一定量のベース電流ＩＯがほぼ消滅しエ
ミッタサイズ効果は著しく低減する。Next, the effects of the present invention will be explained with reference to FIG. Figure 2 is a graph of the hole concentration, electron concentration, and recombination rate per unit time along the dashed-dotted line in Figure 1, using a two-dimensional simulation to analyze the heterojunction bipolar transistor with the structure shown in Figure 1. This is expressed in Similar plot for conventional structure? As a result, when compared with Figure 3, it can be seen that the hole concentration and electron concentration change in almost the same way, but the recombination rate per unit time changes very differently. The ion-implanted extrinsic base region where a large number of recombination centers exist is mainly limited to the kAG a As layer, so the recombination rate per % position time is large in the ion-implanted extrinsic base region. It exists only in the GaAs layer, which is slightly present in the . Therefore, a certain amount of base current IO generated in the external base region is almost eliminated, and the emitter size effect is significantly reduced.
以下、本発明の詳細な説明する。第６図はＡｚＧａＡｓ
−ＧａＡｓヘテロ接合を用いた一実施例のバイポーラト
ランジスタの製造工程を示したものである。まず半絶縁
性Ｇ ａ Ａ ｓ基板６１上にコレクタとなる第１半導
体層としてｎ生型Ｇ ａ Ａ ｓ層６２、続いてｎ凰Ｇ
ａ Ａ ｓ層６３をエピタキシャル成長させる。続い
てベースとなる第２半導体層としてＰ中型ＧａＡｓ層１
６１４ピタキシャル成長させ、更にエミッタとなる第３
半導体層として。The present invention will be explained in detail below. Figure 6 shows AzGaAs
- This figure shows the manufacturing process of an embodiment of a bipolar transistor using a GaAs heterojunction. First, an n-type GaAs layer 62 is placed on a semi-insulating GaAs substrate 61 as a first semiconductor layer which becomes a collector, and then an n-type GaAs layer 62 is placed on a semi-insulating GaAs substrate 61.
The a As layer 63 is epitaxially grown. Next, a P medium-sized GaAs layer 1 is formed as a second semiconductor layer to serve as a base.
614 pitaxially grown, and a third layer that becomes an emitter.
As a semiconductor layer.
ｎ型Ｇａｘ−ｘＡｔｘＡｓでｘｉ−ｏから０．３まで連
続的に変化させ念いわゆるグレーディング層６５゜ｎ型
ＧａＱ、７Ａｔ０．３Ａｓ６６ 、ｎ生型Ｇ ａ Ａ
ｓ層６７ｔ−−’−ビタキシャル成長させる。この実施
例では各半導体４ｔ−ＭＢＥ法によシエビタキシャル成
長させているが、ＭＯＣＶＤ法を用いることも可能であ
る。各層の厚さはｎ十型ＧａＡｓ層６２が０．５μｍ、
ｎ型ＧａＡｓ層６３が０．５ Ａ ｍ 、 Ｐ中型Ｇ
ａ Ａ ｓ層６４が０． ＩＪｉｍ、ｎ型Ｇａｔ−ｘＡ
ｔｘＡｓグレーディング層６５が０．０３μｍ 、 ｎ
型Ｇａ０１７ＡｔＱ、３ＡＳ／白６６が０．１μｍ。The so-called grading layer 65°n-type GaQ, 7At0.3As66, n-type GaA is continuously changed from xi-o to 0.3 with n-type Gax-xAtxAs.
The s-layer 67t--' is grown bitaxially. In this example, the semiconductors are grown in a shear bitaxial manner by the 4t-MBE method, but it is also possible to use the MOCVD method. The thickness of each layer is 0.5 μm for the n-type GaAs layer 62;
The n-type GaAs layer 63 is 0.5 A m, P medium G
aAs layer 64 is 0. IJim, n-type Gat-xA
The txAs grading layer 65 has a thickness of 0.03 μm, n
Type Ga017AtQ, 3AS/white 66 is 0.1 μm.
ｎ生型Ｇ ａ Ａ ｓ層６２でＳ ｉ ７ｊＥ ２Ｘ
１０１８ｍ−３、ｎ型ＧａＡｓ層６３でＳｉが５×１０
１６．−３．Ｐ＋型ＧａＡｓ層６４でＢｅが５Ｘ１０１
”ｍ−３，ｎ型Ｇａ１−ｘＡ ｔ ｘ Ａ ｓグレーデ
ィング層６５で、Ｓｉが３ｘｔｏＬ７ｍ−３，ｎ生型Ｇ
ａ Ａ ｓ層６７でＳｉが５ ×Ｉ Ｏ１８ｃｍ−３
テある。次にエミッタ領域となる部分にホトリソグラフ
ィーにより酸化膜（Ｓ ｉ Ｏ２）マスク６８を形成し
、これを用いて最上層のｎ生型ＧａＡｓ層６７をエツチ
ングしてｎ型Ｇ ａ ０．７ Ａ Ｌ ｏ、 ｓ Ａ
ｓ層６６を露出させた。この状態が第６図（ａ）である
。S i 7jE 2X in n-type Ga As layer 62
1018m-3, n-type GaAs layer 63 with Si of 5×10
16. -3. Be is 5×101 in the P+ type GaAs layer 64
"m-3, n-type Ga1-xA t x As grading layer 65, Si is 3xtoL7m-3, n-type G
In the a As layer 67, Si is 5 × I O18 cm-3
There is. Next, an oxide film (S i O 2 ) mask 68 is formed by photolithography in the portion that will become the emitter region, and using this, the uppermost n-type GaAs layer 67 is etched to form an n-type Ga 0.7 A L o, s A
The s-layer 66 was exposed. This state is shown in FIG. 6(a).
次に酸化膜マスク６８を残し友ままＺｎとＡｓをそれぞ
れ加速電圧１００ ｋｅＶ、ドーズ量１×１ｏ１５ｃｆ
Ｒ−２Ｃイオン注入し、赤外線ランプで８５０℃２秒の
アニールを行った。その結果、Ｐ生型Ｇ ａ Ａ ｓ層
６４にちょうど接触するようにＰ中型外部ベース領域６
９が形成され、第７図に示すような表面濃度１×１０”
３−３の急峻なキャリアプロファイルが得られた。この
時、イオン注入によるダメージｋ Ｇ ａＡｓ層内に導
入しないために、なるべくＰ＋型ＧａＡｓ層６４の上に
ちょうど接触し、Ｐ生型Ｇ ａ Ａ ｓ層６４の内部に
は侵入しないようなイオン注入条件を選ぶことが望まし
い、ｌ続いて、エミッタ領域から外部ベース領域の一部
をおおうマスクを形成し、Ｂ’ｉ加速電圧１５０ ｋｅ
Ｖドーズ量５Ｘ １０ ”ｅｙｎ−２及び７０ ｋｅＶ
、 ２ｘ １０−１２ｃＷ１−２ テ二重イオン注入
し、アニール全行ってベースとコレクタを分離するため
の高抵抗層７０を形成した。この状態が第６図［ｂ）で
ある。Next, leaving the oxide film mask 68, Zn and As are each deposited at an acceleration voltage of 100 keV and a dose of 1×1o15cf.
R-2C ions were implanted, and annealing was performed at 850° C. for 2 seconds using an infrared lamp. As a result, the P medium external base region 6 is in contact with the P green Ga As layer 64.
9 is formed, and the surface concentration is 1×10” as shown in FIG.
A steep carrier profile of 3-3 was obtained. At this time, in order to prevent damage caused by the ion implantation from being introduced into the GaAs layer, the ion implantation should be carried out so as to contact exactly on the P+ type GaAs layer 64 and not to penetrate into the inside of the P+ type GaAs layer 64. It is desirable to select the conditions, then form a mask covering part of the extrinsic base region from the emitter region, and apply a B'i acceleration voltage of 150 ke.
V dose 5X 10”eyn-2 and 70 keV
, 2x 10-12 cW1-2 Te double ion implantation was performed, and annealing was performed to form a high resistance layer 70 for separating the base and collector. This state is shown in FIG. 6 [b].
次に、Ｐ串型外部ベース領域上にＡ ｕ Ｚ ｎ合金を
蒸着、アロイしてベース電＠７１を形成した。Next, an A u Z n alloy was deposited and alloyed on the P-shaped external base region to form a base electrode @71.
この時の接触抵抗は５Ｘ１０−７０・−程度であった。The contact resistance at this time was approximately 5X10-70.
さらに、素子分離用の高抵抗層７２をプロトンのイオン
注入により形成し、コレクタ電極数９出しの次めのエツ
チングを行っ之のち、ＡｕＧｅ合金膜を蒸着してエミッ
タ電極７３．コレクタ電極７４を形成した。完成し次状
態は第６図ＴＣ）である。Furthermore, a high-resistance layer 72 for element isolation is formed by ion implantation of protons, and after etching is performed to form nine collector electrodes, an AuGe alloy film is deposited to form emitter electrodes 73. A collector electrode 74 was formed. Once completed, the next state is shown in Figure 6 (TC).
エミツタ幅Ｘが２０μｍから０．８μｍの素子を製作し
た。念だし、もう一方のエミツタ幅は２０μｍに固定し
である。電流増幅率ｈｒｚのエミツタ幅依存性は第８図
の実線のようになり、すべてのサイズの素子で３００程
度の値が得られ友。Elements with an emitter width X of 20 μm to 0.8 μm were manufactured. Just to be sure, the width of the other emitter is fixed at 20 μm. The dependence of the current amplification factor hrz on the emitter width is as shown by the solid line in Figure 8, and a value of about 300 can be obtained for all sizes of elements.
従来構造、たとえば第５図のようにイオン注入で形成し
たＰ中型外部ベース領域が、Ｐ型Ｇ ａ Ａ ｓ層４３
をつき抜けて１ｎ型Ｇ ａ Ａ ｓ層４２へ侵入してい
る場合には、その侵入の深さがｎ型ＧａＡｓ４２とＰ生
型Ｇ ａ Ａ ｓ層４３の界面からαｌμｗ程度の時、
第８図の破線のようであった。すなわち、エミツタ幅Ｘ
が２０μｍの時ｈ１罵は２５０程度であったのが、Ｘが
０．８μｍになると１０程度にまで著しく減少していた
。従って、本発明にょフエミッタサイズ効果が著しく改
善されていることは明らかである。In the conventional structure, for example, as shown in FIG.
When the penetration depth is about αlμw from the interface between the n-type GaAs 42 and the P-type GaAs layer 43,
It looked like the broken line in Figure 8. In other words, the emitter width
When X was 20 μm, h1 was about 250, but when X became 0.8 μm, it significantly decreased to about 10. Therefore, it is clear that the emitter size effect of the present invention is significantly improved.
本発明の他の実施例を第９図に示す。半絶縁性ＧａＡｓ
基板９１上にコレクタ層となるｎ生型ＧａＡｓ９１とｎ
型ＧａＡｓ層９３をエピタキシャル成長し次のちベース
層となるＰ＋型ＧａＡｓ層９４．さらにエミツタ層とな
るｎ型ＡｌＧａＡｓ層９５．ｎ型Ｇ ａ Ａ ｓ層９６
及び、ｎ中型’Ｇ ａ Ａ ｓ層９７を順次エピタキシ
ャル成長した５次に、エミッタ領域を残して最上部のｎ
生型ＧａＡｓ層９７ｔ″除去し、ｎ型ＧａＡｓ層９８を
露出させる。Another embodiment of the invention is shown in FIG. Semi-insulating GaAs
On the substrate 91 are n-type GaAs 91 and n
A type GaAs layer 93 is epitaxially grown, and then a P+ type GaAs layer 94 which becomes a base layer is formed. Further, an n-type AlGaAs layer 95 serving as an emitter layer. n-type GaAs layer 96
Then, an n-medium sized GaAs layer 97 is epitaxially grown in sequence, and then the uppermost n layer is formed, leaving an emitter region.
The raw GaAs layer 97t'' is removed to expose the n-type GaAs layer 98.
次にＺｎとＡｓ＝ｊＨイオン注入して、Ｐ生型の外部ベ
ース領域９８をＰ生型Ｇ ａ Ａ ｓ層９４に達し。Next, Zn and As=jH ions are implanted to extend the P-type external base region 98 to the P-type GaAs layer 94.
ｎ型ＧａＡｓ層９３には達っしない深さに形成し念。さ
らにＢのイオン注入でベース・コレクタ間に高抵抗領域
９９ｔ−形成したのち、外部ベース９８上にベース電極
１００をＡ ｕ Ｚ ｎ合金を蒸着することにより形成
した。従来がらＡｌＧａＡｓはＡｔを含むために酸化し
やすく、電極形成の再現性もよくないという問題点があ
ったが、この構造では、素子の最上部はすべてＧ ａ
Ａ ｓでおおわれ、かつ電極もＧａＡｓ上に設けられる
ようになっているので、この問題点をとり除くことがで
きる。ただし、この構造では真性トランジスタ領域の他
に５表面部でＧ ａ Ａ ｓホモ接合が形成されるため
、このホモ接合をなくす意味で、エミッタ領域とベース
電極の間にＢｔ−イオン注入して高抵抗層１０１Ｔｈ形
成している。なお１０２はエミッタ電極である。It should be formed at a depth that does not reach the n-type GaAs layer 93. Furthermore, after forming a high resistance region 99t between the base and collector by ion implantation of B, a base electrode 100 was formed on the external base 98 by vapor depositing an AuZn alloy. Conventionally, AlGaAs contains At, so it easily oxidizes, and the reproducibility of electrode formation is poor.
Since it is covered with As and the electrodes are also provided on GaAs, this problem can be eliminated. However, in this structure, in addition to the intrinsic transistor region, a GaAs homojunction is formed on the 5th surface, so in order to eliminate this homojunction, Bt- ions are implanted between the emitter region and the base electrode. A resistance layer 101Th is formed. Note that 102 is an emitter electrode.
この実施例ではエミツタ幅Ｘが２０μｍの場合。In this example, the emitter width X is 20 μm.
ｈＩＰ！！！は３００．Ｘが０．８ ＩＩ ｍの場合に
１００であッｆｃ、。hIP! ! ! is 300. If X is 0.8 II m, then 100 is fc.
前記の実施例（第８図実線）に比べると、エミッタサイ
ズ効果が大きいが、これは、イオン注入で形成したＰ生
型外部領域が、前記の実施例では。The emitter size effect is larger than in the previous embodiment (solid line in FIG. 8), but this is because the P-type external region formed by ion implantation is in the above embodiment.
Ｐ生型ＧａＡｓ層（第６図６４）の上部までしか達っし
ていないのに対し、この実施例ではＰ生型ＧａＡｓ層（
第９図９４）の内部まで達しておシ。In this example, the P-type GaAs layer (Fig. 6, 64) reaches only the top of the P-type GaAs layer (Fig. 6, 64).
It reached the inside of Figure 9 (94).
イオン注入領域中にあるＣａＡｓ層内で再結合電流が発
生しているためである。This is because a recombination current is generated within the CaAs layer in the ion implantation region.
しかしながら従来構造の場合（第８図破線）に比べれば
著しくエミッタサイズ効果が改善されているのは明らか
である。However, it is clear that the emitter size effect is significantly improved compared to the conventional structure (broken line in FIG. 8).
以上実施例はＡ４ＧａＡｓ／ＧａＡｓによるヘテロ接合
バイポーラトランジスタの場合であるが１本発明は他の
半導体材料を用い九場合にも適用することができる。ま
た、上記実施例では外部ベース領域をイオン注入により
形成したが、Ｚｎ等の拡散などの他の方法により、外部
ベース領域を形成する場合にも、外部ベース形成工程で
電子゛やホールの拡散長が減少する場合には本発明は有
効である。Although the embodiment described above is a case of a heterojunction bipolar transistor made of A4GaAs/GaAs, the present invention can also be applied to cases using other semiconductor materials. Further, in the above embodiment, the external base region was formed by ion implantation, but when forming the external base region by other methods such as diffusion of Zn, etc., the diffusion length of electrons and holes may be changed in the external base forming process. The present invention is effective when .
第１図は本発明の構造の代表的な例を模式的に表わし念
もので、１１は半絶縁性Ｇ ａ Ａ ｓ基板、１２はｎ
生型Ｇ ａ Ａ ｓ層（第１半導体層）％１３はｎ型Ｇ
ａＡｓ層（第１半導体層）１１４はＰ＋型Ｇ ａ Ａ
ｓ層（第２半導体層）、１５はｎ型ＡｌＧａＡｓ層（第
３半導体ｒｖ１）、１６はｎ串型ＧａＡｓ層（第３半導
体層）、１７はＰ生型外部ベース領域、１８はベース電
極、１９は高抵抗層。
２０はエミッタ電極、２１はコレクタ電極である。
第２図及び第３図は本発明と従来のヘテロ接合バイポー
ラトランジスタを２次元シミュレーションで解析した結
果を示す図である。第４図及び第５図は従来のヘテロ接
合バイポーラトランジスタを示す図である。第６図及び
第７図は本発明の一実施例のヘテロ接合バイポーラトラ
ンジスタの構造及び爬造工徨を示す図で、６１は半絶縁
性ＧａＡｓ基板、６２！ｆ：、ｎ＋型ＧａＡｓ層（第１
半導体層）。
６３はｎ型ＧａＡｓ層（第１半導体層）、６４はＰ＋Ｇ
ａＡｓ層（第２半導体Ｊｔり、６５はｎ型Ｇ ａ ｈＡ
ｔｘｋｓグレーディング層（第３半導体層）、６６はｎ
型ＧａｏｙｙＡｚｏ、ａＡｓ層（第３半導体層）、６７
はｎ串型ＧａＡｓ層（第３半導体層）、６８は酸化Ｈ（
Ｓ ｉ Ｏ２）マスク、６９はＰ生型外部ベース領域、
７０は高抵抗層、７１はベース？電極、７２は高抵抗層
、７３はエミッタ電極、７４はコレクタ電極である。
第８図は上記実施例のバイポーラトランジスタの電流増
幅率のエミツタ幅依存性を従来例と比較して示す図であ
る。
第９図は本発明の他の実施例のヘテロバイポーラトラン
ジスタの構造を示す図で、９１は半絶縁性Ｇ ａ Ａ
ｓ基板、９２Ｕｎ＋型ＧａＡｓ層（第１半導体層）９３
はｎ型Ｇ ａ Ａ ｓ屓（第１半導体層）９４はＰ生型
Ｇ ａ Ａ ｓ Ｎ （第２半導体層）９５はｎ型Ａｌ
ＧａＡｓ層（第３半導体層）、９６はｎ型ＧａＡｓ層（
第３半導体層）、９７はｎ ＋ 型Ｇ ａ Ａ ｓ層（
第３半導体層）、９８はＰ生型外部ベース領域、９９は
高抵抗層、１００はベース電極、１０１は高抵抗層、１
０２はエミッタ電極である。
第１図
第 ４ 図
第 ５ 図
第６図
第７図
工し、り暢 （）４％）
第 ８ 図
第 ９ 図FIG. 1 schematically shows a typical example of the structure of the present invention, in which 11 is a semi-insulating GaAs substrate, 12 is an n
Raw Ga As layer (first semiconductor layer) %13 is n-type G
The aAs layer (first semiconductor layer) 114 is P+ type Ga A
s layer (second semiconductor layer), 15 is an n-type AlGaAs layer (third semiconductor rv1), 16 is an n-shaped GaAs layer (third semiconductor layer), 17 is a P-type external base region, 18 is a base electrode, 19 is a high resistance layer. 20 is an emitter electrode, and 21 is a collector electrode. FIGS. 2 and 3 are diagrams showing the results of two-dimensional simulation analysis of the present invention and conventional heterojunction bipolar transistors. FIGS. 4 and 5 are diagrams showing conventional heterojunction bipolar transistors. 6 and 7 are diagrams showing the structure and structure of a heterojunction bipolar transistor according to an embodiment of the present invention, in which 61 is a semi-insulating GaAs substrate, 62! f:, n+ type GaAs layer (first
semiconductor layer). 63 is an n-type GaAs layer (first semiconductor layer), 64 is P+G
aAs layer (second semiconductor Jt layer, 65 is n-type Ga hA
txks grading layer (third semiconductor layer), 66 is n
Type GaoyyAzo, aAs layer (third semiconductor layer), 67
68 is an n-shaped GaAs layer (third semiconductor layer), and 68 is an oxidized H (
S i O2) mask, 69 is a P-type external base region,
Is 70 the high resistance layer and 71 the base? The electrodes 72 are high resistance layers, 73 are emitter electrodes, and 74 are collector electrodes. FIG. 8 is a diagram showing the emitter width dependence of the current amplification factor of the bipolar transistor of the above embodiment in comparison with that of the conventional example. FIG. 9 is a diagram showing the structure of a hetero bipolar transistor according to another embodiment of the present invention, in which 91 is a semi-insulating G a A
s substrate, 92 Un+ type GaAs layer (first semiconductor layer) 93
is n-type GaAs (first semiconductor layer) 94 is P-type GaAsN (second semiconductor layer) 95 is n-type Al
GaAs layer (third semiconductor layer), 96 is an n-type GaAs layer (
97 is an n + type Ga As layer (
3rd semiconductor layer), 98 is a P-type external base region, 99 is a high resistance layer, 100 is a base electrode, 101 is a high resistance layer, 1
02 is an emitter electrode. Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Construction (4%) Figure 8 Figure 9
Claims (1)
スとなる第２導電型の第２半導体層及びエミッタとなる
第１導電型の第３半導体層が順次積層され、第３半導体
層の少なくとも第２半導体層に接する部分の禁制帯幅が
第２半導体層のそれより大きいウエーハを用いて構成さ
れたヘテロ接合バイポーラトランジスタにおいて、前記
第３半導体層にエミッタ領域を取り囲むように前記第２
半導体層に達し、かつ前記第１半導体層には達っしない
深さの第２導電型外部ベース領域が設けられ、この外部
ベース領域中の第３半導体層に接してベース電極が形成
されていることを特徴とするヘテロ接合バイポーラトラ
ンジスタ。（２）半絶縁性ＧａＡｓ基板に、第１導電型
の第１半導体層としてｎ＾＋型ＧａＡｓ層が形成され、
第１導電型の第３半導体層としてｎ型ＡｌＧａＡｓ層及
びｎ＾＋型ＧａＡｓ層が形成されている特許請求の範囲
第１項記載のヘテロ接合バイポーラトランジスタ。 （３）基板に、コレクタとなる第１導電型の第１半導体
層、ベースとなる第２導電型の第２半導体層、及びこの
第２半導体層と接する部分の禁制帯幅が第２半導体層の
それより大きい、エミッタとなる第１導電型の第３半導
体層を順次エピタキシャル成長させる工程と、エミッタ
領域を取り囲むように不純物をドープして前記第２半導
体層に達し、かつ前記第１半導体層には達しない深さの
外部ベース領域を形成する工程と、前記外部ベース領域
中の第３半導体層に接してベース電極を形成する工程と
を備えたことを特徴とするヘテロ接合バイポーラトラン
ジスタの製造方法。 （４）基板として、半絶縁性ＧａＡｓ基板を用い、第１
半導体層としてｎ＾＋型ＧａＡｓ層とｎ型ＧａＡｓ層、
第２半導体層としてＰ＾＋型ＧａＡｓ層、第３半導体層
としてｎ型ＡｌＧａＡｓ層とｎ＾＋型ＧａＡｓ層を順次
エピタキシャル成長させる特許請求の範囲第３項記載の
ヘテロ接合バイポーラトランジスタの製造方法。[Claims] (1) A first semiconductor layer of the first conductivity type that serves as a collector, a second semiconductor layer of the second conductivity type that serves as a base, and a third semiconductor layer of the first conductivity type that serves as an emitter are sequentially laminated. In a heterojunction bipolar transistor configured using a wafer in which a forbidden band width of at least a portion of the third semiconductor layer in contact with the second semiconductor layer is larger than that of the second semiconductor layer, an emitter region is provided in the third semiconductor layer. said second so as to surround
A second conductivity type external base region is provided with a depth that reaches the semiconductor layer but does not reach the first semiconductor layer, and a base electrode is formed in contact with the third semiconductor layer in the external base region. A heterojunction bipolar transistor characterized by: (2) An n^+ type GaAs layer is formed as a first conductivity type first semiconductor layer on a semi-insulating GaAs substrate,
2. The heterojunction bipolar transistor according to claim 1, wherein an n-type AlGaAs layer and an n^+-type GaAs layer are formed as the third semiconductor layer of the first conductivity type. (3) The substrate includes a first semiconductor layer of a first conductivity type that serves as a collector, a second semiconductor layer of a second conductivity type that serves as a base, and a second semiconductor layer that has a forbidden band width of a portion in contact with the second semiconductor layer. a step of sequentially epitaxially growing a third semiconductor layer of the first conductivity type that is larger than that of the emitter, and doping impurities so as to surround the emitter region to reach the second semiconductor layer and to the first semiconductor layer. A method for manufacturing a heterojunction bipolar transistor, comprising: forming an external base region with a depth that does not reach the same depth; and forming a base electrode in contact with a third semiconductor layer in the external base region. . (4) Using a semi-insulating GaAs substrate as the substrate, the first
As a semiconductor layer, an n^+ type GaAs layer and an n type GaAs layer,
4. The method of manufacturing a heterojunction bipolar transistor according to claim 3, wherein a P^+ type GaAs layer is epitaxially grown as the second semiconductor layer, and an n type AlGaAs layer and an n^+ type GaAs layer are sequentially grown as the third semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6412886A JPS62221151A (en) | 1986-03-24 | 1986-03-24 | Hetero junction bipolar transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6412886A JPS62221151A (en) | 1986-03-24 | 1986-03-24 | Hetero junction bipolar transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62221151A true JPS62221151A (en) | 1987-09-29 |
Family
ID=13249122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6412886A Pending JPS62221151A (en) | 1986-03-24 | 1986-03-24 | Hetero junction bipolar transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62221151A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5053346A (en) * | 1990-01-12 | 1991-10-01 | Texas Instruments Incorporated | Method for making a high speed gallium arsenide transistor |
| US5340755A (en) * | 1989-09-08 | 1994-08-23 | Siemens Aktiegensellschaft | Method of making planar heterobipolar transistor having trenched isolation of the collector terminal |
-
1986
- 1986-03-24 JP JP6412886A patent/JPS62221151A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5340755A (en) * | 1989-09-08 | 1994-08-23 | Siemens Aktiegensellschaft | Method of making planar heterobipolar transistor having trenched isolation of the collector terminal |
| US5053346A (en) * | 1990-01-12 | 1991-10-01 | Texas Instruments Incorporated | Method for making a high speed gallium arsenide transistor |
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