JPH01144670A - Complementary mos semiconductor device - Google Patents
Complementary mos semiconductor deviceInfo
- Publication number
- JPH01144670A JPH01144670A JP62195567A JP19556787A JPH01144670A JP H01144670 A JPH01144670 A JP H01144670A JP 62195567 A JP62195567 A JP 62195567A JP 19556787 A JP19556787 A JP 19556787A JP H01144670 A JPH01144670 A JP H01144670A
- Authority
- JP
- Japan
- Prior art keywords
- cell
- channel region
- power supply
- cells
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000000295 complement effect Effects 0.000 title claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000002699 waste material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は相捕型ＭＯＳ半導体集積回路に関し、特にスタ
ンダードセル方式の自動レイアウトを良好に行なう半導
体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOS semiconductor integrated circuit, and more particularly to a structure of a semiconductor device that satisfactorily performs standard cell type automatic layout.
近年、半導体集積回路装置において、スタンダードセル
を用いた自動レイアウト手法が実用化されつつある。こ
の種のレイアウト手法を用いる場合、プログラムの性能
とスタンダードセル自体の内部をどの様に構成するかに
よって集積度が大きく興なってくるなめ、そのセルの内
部の設計が重要な問題となっている。In recent years, automatic layout methods using standard cells have been put into practical use in semiconductor integrated circuit devices. When using this type of layout method, the internal design of the cell is an important issue because the degree of integration greatly depends on the program performance and how the internal structure of the standard cell itself is configured. .
従来用いられているセルのレイアウト方法について説明
する。A conventional cell layout method will be explained.
このセルを設計する場合の基本的制限は次のとおりであ
る。The basic limitations when designing this cell are:
（１）各セルの入出力端子は、ブロックの上下に定義し
なければならない。(1) The input/output terminals of each cell must be defined above and below the block.
（２）電源グランド配線は、各セルの左右方向に配線さ
れ、かつ隣り合うセルが隣接できるように、セル原点に
対し、電源グランド配線が一定の位置になければならな
い。(2) The power ground wiring must be wired in the left-right direction of each cell, and must be located at a constant position with respect to the cell origin so that adjacent cells can be adjacent to each other.
（３）インバータ、ＮＯＲゲート、ＮＡＮＤゲートなど
の同一機能をもつセルにおいて、トランジスタの駆動能
力が異なる複数個のセルを用意する必要があらる。(3) Among cells having the same function, such as an inverter, a NOR gate, and a NAND gate, it is necessary to prepare a plurality of cells with different transistor driving capabilities.
この制限を満足するように設計したセルレイアウトの一
例を第２図（ａ）、（ｂ）に示す。この場合、単位セル
外形７の中に、一対の拡散パターン１と、この拡散パタ
ーン１とコンタクトパターン２を介して接続する第１．
第２アルミパターン４．６と、ポリシリコンパターン３
と、スルーホール５とか設けられている。第２図（ａ）
のように駆動能力の小さいインバータ回路のセルの場合
、コンタクトパターン２の数が少なく、第２図（ｂ）の
ように駆動能力の大きいインバータ回路のセルの場合、
コンタクトパターン２の数が多くなっている。An example of a cell layout designed to satisfy this restriction is shown in FIGS. 2(a) and 2(b). In this case, the unit cell outline 7 includes a pair of diffusion patterns 1 and a first diffusion pattern 1 connected to the diffusion patterns 1 via the contact pattern 2.
2nd aluminum pattern 4.6 and polysilicon pattern 3
There is also a through hole 5. Figure 2(a)
In the case of a cell of an inverter circuit with a small driving capacity as shown in FIG. 2(b), the number of contact patterns 2 is small;
The number of contact patterns 2 is increased.
上述した従来のインバータ回路のセルレイアウトは、第
２図（ａ）の駆動能力の小さいセルにおいて、点線部Ａ
、Ａ’のように、コンタクトパターン２のない空領域と
なる領域が生ずる。この従来例は、インバータ回路を示
したが、ＮＯＲ。In the cell layout of the conventional inverter circuit described above, in the cell with small driving capacity shown in FIG. 2(a), the dotted line A
, A', empty areas without the contact pattern 2 are generated. Although this conventional example shows an inverter circuit, it is a NOR circuit.
ＮＡＮＤ等他の基本ゲートにおいても、同しように空領
域が存在し、チップ全体を考えた場合、自動レイアウト
プログラムの性能がよくなっても、セル内に存在する空
領域によって集積度を劣化させてしまう欠点がある。Other basic gates such as NAND also have empty areas, and even if the performance of the automatic layout program improves when considering the entire chip, the empty areas that exist within the cell will degrade the integration density. There is a drawback.
本発明の目的は、このような欠点を除き、セル内部に空
領域を含まずに最適なセルに設計できる相捕型ＭＯＳ半
導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a compensating type MOS semiconductor device that eliminates such drawbacks and can be designed into an optimal cell without including an empty area inside the cell.
本発明の構成は、複数個のゲート単位の基本セルで形成
され、これら各基本セル内にＰチャネル領域およびＮチ
ャネル領域を備えた相捕型ＭＯＳ半導体装置において、
前記各基本セル内に設けられる電源および接地の各配線
を前記Ｐチャネル領域とＮチャネル領域との間に配線し
たことを特徴とする。The structure of the present invention is a compensating type MOS semiconductor device formed of a plurality of basic cells in units of gates, each of which has a P channel region and an N channel region.
The device is characterized in that power supply and ground wiring provided in each of the basic cells are routed between the P channel region and the N channel region.
次に本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第１図（ａ＞、（ｂ）は本発明の一実施例の駆動能力の
小さいおよび大きいインバータ回路のセルレイアウト図
である。第１−図（ａ）の駆動能力の小さいインバータ
回路のセルは、拡散パターン１からなるＰチャネル領域
とＮチャネル領域の間に第１アルミパターン４からなる
電源、接地配線を配線したものである。この場合、セル
内に第２図（ａ）に示したような空領域Ａ、Ａ’がなく
、設計することか可能である。FIGS. 1(a) and 1(b) are cell layout diagrams of inverter circuits with small and large driving capacities according to an embodiment of the present invention.The cells of the inverter circuit with small driving capacities shown in FIG. , the power supply and ground wirings made of the first aluminum pattern 4 are wired between the P channel region and the N channel region made of the diffusion pattern 1. In this case, as shown in FIG. There are no empty areas A, A', and it is possible to design.
第１図（ｂ）の駆動能力の大きいインバータ回路のセル
は、第１図（ａ）と同様Ｐチャネル領域とＮチャネル領
域の間に電源、接地配線を配線したセルパターンである
。The cell of the inverter circuit with high driving capacity shown in FIG. 1(b) has a cell pattern in which power supply and ground wirings are wired between the P channel region and the N channel region, as in FIG. 1(a).
このように第１図（ａ）、（ｂ）の各セルが隣接する場
合、セル原点８が水平成分の座標で同じになるようにセ
ルが配置されると、２つのセルがブロック外形７で接す
るように配置することが可能となり、パターンレイアウ
トの無駄がなく、チップの有効利用が図られる。In this way, when the cells in FIGS. 1(a) and 1(b) are adjacent to each other, if the cells are arranged so that the cell origin 8 has the same horizontal component coordinates, the two cells will have the block outline 7. It becomes possible to arrange the chips so that they are in contact with each other, so there is no waste in pattern layout, and the chips can be used effectively.
以上説明したように本発明は、スタンダード方式の相捕
型ＭＯＳ半導体装置のセルレイアウトにおいて、セル内
で、電源グランド配線をＰチャネル領域とＮチャネル領
域の間に電源、グランドを配線することにより、セル内
に空領域を全くなしに、セル設計時の基本的制限をすべ
て満足したセルを設計することができ、チップを高密度
に実装することができる。As explained above, in the cell layout of a standard type compensating type MOS semiconductor device, the present invention provides power supply and ground wiring between the P channel region and the N channel region within the cell. It is possible to design a cell that satisfies all the basic limitations when designing a cell without having any empty space within the cell, and it is possible to mount chips at high density.
第１図（ａ）、（ｂ）は本発明の一実施例の駆動能力の
小さいおよび大きいインバータ回路のセルパターン図、
第２図（ａ）、（ｂ）は従来の駆動能力の小さいおよび
大きいインバータ回路のセルパターン図である。FIGS. 1(a) and 1(b) are cell pattern diagrams of inverter circuits with small and large driving capacities according to an embodiment of the present invention,
FIGS. 2(a) and 2(b) are cell pattern diagrams of conventional inverter circuits with small and large driving capacities.
Claims (1)
基本セル内にＰチャネル領域およびＮチャネル領域を備
えた相捕型ＭＯＳ半導体装置において、前記各基本セル
内に設けられる電源および接地の各配線を前記Ｐチャネ
ル領域とＮチャネル領域との間に配線したことを特徴と
する相捕型ＭＯＳ半導体装置。In a complementary MOS semiconductor device formed of a plurality of basic cells in units of gates and each of these basic cells having a P channel region and an N channel region, each wiring for power supply and ground provided in each of the basic cells. A compensating type MOS semiconductor device characterized in that: is wired between the P channel region and the N channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62195567A JPH01144670A (en) | 1987-08-04 | 1987-08-04 | Complementary mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62195567A JPH01144670A (en) | 1987-08-04 | 1987-08-04 | Complementary mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01144670A true JPH01144670A (en) | 1989-06-06 |
Family
ID=16343270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62195567A Pending JPH01144670A (en) | 1987-08-04 | 1987-08-04 | Complementary mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01144670A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60123042A (en) * | 1983-12-08 | 1985-07-01 | Toshiba Corp | Semiconductor integrated circuit |
-
1987
- 1987-08-04 JP JP62195567A patent/JPH01144670A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60123042A (en) * | 1983-12-08 | 1985-07-01 | Toshiba Corp | Semiconductor integrated circuit |
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