JPH0823096A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0823096A
JPH0823096A JP6157108A JP15710894A JPH0823096A JP H0823096 A JPH0823096 A JP H0823096A JP 6157108 A JP6157108 A JP 6157108A JP 15710894 A JP15710894 A JP 15710894A JP H0823096 A JPH0823096 A JP H0823096A
Authority
JP
Japan
Prior art keywords
gate
gate electrode
trench
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6157108A
Other languages
Japanese (ja)
Inventor
Tatsuo Yoneda
辰雄 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6157108A priority Critical patent/JPH0823096A/en
Publication of JPH0823096A publication Critical patent/JPH0823096A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To avoid concentrating a field to a trench corner and prevent the insulation gate withstanding power from dropping by avoiding forming a channel forming layer at term grooves connecting gate electrodes to a gate electrode extraction part. CONSTITUTION:A p-base region 3 is diffusion-formed on the surface of a low concn. n<->-Si substrate 2 formed on a high concn. n<+>-Si substrate 1 of a MOSFET. An n<+>-source region 4 is diffusion-formed partly on the surface of the region 3. Trenches 5 are so formed as to longitudinally pass through the region 3 from a central part of the surface of the region 4, gate electrodes 7 are formed through a gate oxide film 6 in the trenches 5 whereby they couple with a gate electrode extraction part 6. The base region 3 is not formed at corresponding regions of the substrate 2 to terminals of the trenches 5 by masking them. Thus, the field concentration on trench corners 8a and 8b of the terminals 8 of the trenches 5 is avoided to improve the gate withstanding value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、主として電力用に使用
され、トレンチゲート構造を有するＭＯＳ型トランジス
タ等の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a MOS transistor having a trench gate structure which is mainly used for electric power.

【０００２】[0002]

【従来の技術】一般に、トレンチゲート構造を有するＭ
ＯＳＦＥＴは、チャネルがトレンチ（溝）に沿って縦方
向に形成されるため、プレーナ構造のＭＯＳＦＥＴに対
して、ゲート電極の幅を大幅に縮小できるので、セルの
高集積化が可能となり単位面積当たりのチャネル幅を増
大することができるなど、優れた特徴を有している。2. Description of the Related Art Generally, an M having a trench gate structure.
In the OSFET, since the channel is formed vertically along the trench (groove), the width of the gate electrode can be significantly reduced as compared with the planar structure MOSFET, which enables high integration of the cell and per unit area. It has an excellent feature such that the channel width can be increased.

【０００３】しかし、このトレンチゲートＭＯＳＦＥＴ
は、プレーナ型に比べてゲート耐量が低下するといった
問題が知られている。これは、トレンチコーナー部のゲ
ート酸化膜の膜厚がトレンチ側面及びシリコン表面に成
長するゲート酸化膜の膜厚に比べ、極端に薄くなってい
るため、トレンチコーナー部での絶縁ゲート耐量が低下
することが原因とされている。However, this trench gate MOSFET
Is known to have a lower gate withstand capability than the planar type. This is because the film thickness of the gate oxide film at the trench corner portion is extremely smaller than the film thickness of the gate oxide film grown on the trench side surface and the silicon surface, so that the insulated gate withstand capability at the trench corner portion decreases. It is said that the cause.

【０００４】この問題の一般的な解決方法としては、Ｆ
ＥＴ部分において、ゲート電極をエッチング後退させて
トレンチ内にのみ充填することで、トレンチコーナー部
での電界集中を回避する方法が知られている。As a general solution to this problem, F
In the ET portion, there is known a method of avoiding the electric field concentration at the corner portion of the trench by retreating the gate electrode by etching to fill the trench only.

【０００５】従来、この種の縦型トレンチＭＯＳＦＥＴ
としては、例えば図９（ａ），（ｂ）に示すようなもの
があった。Conventionally, this type of vertical trench MOSFET has been used.
For example, there are those as shown in FIGS. 9 (a) and 9 (b).

【０００６】図９（ａ），（ｂ）は、従来の縦型トレン
チＭＯＳＦＥＴの構造を示す立体斜視図であり、同図
（ａ）はＦＥＴ領域の立体斜視図、及び同図（ｂ）はゲ
ート電極引出し部の立体斜視図である。9A and 9B are three-dimensional perspective views showing the structure of a conventional vertical trench MOSFET. FIG. 9A is a three-dimensional perspective view of a FET region, and FIG. It is a three-dimensional perspective view of a gate electrode lead-out part.

【０００７】このＭＯＳＦＥＴは、ゲート工程直後の構
成を示しており、高濃度（Ｎ＋）シリコン基板１０１と
低濃度（Ｎ−）シリコン基板１０２とが順次形成され、
そのＮ−シリコン基板１０２の表面にはＰベース領域１
０３が拡散形成されている。そして、そのＮ＋シリコン
基板１０１とＮ−シリコン基板１０２とによってドレイ
ン領域が形成されている。This MOSFET shows a structure immediately after the gate process, in which a high concentration (N + ) silicon substrate 101 and a low concentration (N − ) silicon substrate 102 are sequentially formed,
A P base region 1 is formed on the surface of the N-silicon substrate 102.
03 is diffused. The N + silicon substrate 101 and the N− silicon substrate 102 form a drain region.

【０００８】さらに、Ｐベース領域１０３の表面には部
分的にＮ＋型のソース領域１０４が拡散形成され、その
ソース領域１０４の表面中央部から縦方向に、Ｎ−シリ
コン基板１０２に達する複数のトレンチ１０５がストラ
イブ状に形成されている。また、各トレンチ１０５の内
壁面及び底面を被うようにゲート酸化膜１０６が形成さ
れ、そのトレンチ１０５内のゲート酸化膜１０６上には
ゲート電極１０７が形成されている。Further, an N + type source region 104 is partially diffused and formed on the surface of the P base region 103, and a plurality of N + type silicon substrate 102 is vertically formed from the center of the surface of the source region 104. The trench 105 is formed in a stripe shape. A gate oxide film 106 is formed so as to cover the inner wall surface and the bottom surface of each trench 105, and a gate electrode 107 is formed on the gate oxide film 106 in the trench 105.

【０００９】そして、ゲート電極１０７が各トレンチ１
０５の終端部１０８を越えて前記Ｐベース領域１０３上
のゲート酸化膜１０６表面に引出されて、ゲート電極引
出し部１０９が形成されている。The gate electrode 107 is formed in each trench 1
A gate electrode lead-out portion 109 is formed by extending over the end portion 108 of No. 05 to the surface of the gate oxide film 106 on the P base region 103.

【００１０】このように構成される縦型トレンチＭＯＳ
ＦＥＴの製造工程を図１０〜図１１を用いて説明する。A vertical trench MOS having the above structure
The manufacturing process of the FET will be described with reference to FIGS.

【００１１】図１０（ａ），（ｂ）は、従来の拡散層形
成工程後のチップの構成を示す図であり、同図（ａ）は
その平面図、及び同図（ｂ）は図（ａ）のＡ−Ａ´断面
図である。図１１（ａ），（ｂ）は、従来のゲート形成
工程後のチップの構成を示す図であり、同図（ａ）はそ
の平面図、同図（ｂ）は図（ａ）のＡ−Ａ´断面図であ
る。また、図１２（ａ），（ｂ），（ｃ）は、従来のゲ
ート配線工程後のチップの構成を示す図であり、同図
（ａ）はその平面図、図（ｂ）は同図（ａ）のＡ−Ａ´
断面図、及び同図（ｃ）は図（ａ）のＢ−Ｂ´断面図で
ある。10 (a) and 10 (b) are views showing the structure of the chip after the conventional diffusion layer forming step. FIG. 10 (a) is its plan view, and FIG. 10 (b) is a drawing ( It is an AA 'sectional view of a). 11A and 11B are diagrams showing the structure of a chip after a conventional gate formation process, in which FIG. 11A is a plan view thereof and FIG. 11B is a view of A- of FIG. It is an A'sectional view. 12 (a), (b), and (c) are diagrams showing the structure of a chip after a conventional gate wiring process, in which FIG. 12 (a) is its plan view and FIG. 12 (b) is the same. (A) A-A '
A cross-sectional view and the same figure (c) are BB 'cross-sectional views of FIG.

【００１２】まず、図１０（ａ），（ｂ）に示すよう
に、拡散層形成工程として、Ｎ＋シリコン基板１０１上
のＮ−シリコン基板１０２の表面にチャネル層としての
Ｐベース領域１０３をＦＥＴの動作領域全面に拡散形成
する。さらに、所望のパターニング後にＰ型ベース領域
の主面側にＮ＋型のソース領域１０４を拡散形成する。First, as shown in FIGS. 10A and 10B, in a diffusion layer forming step, a P base region 103 as a channel layer is formed on the surface of an N− silicon substrate 102 on an N + silicon substrate 101 to form a FET. Diffusion is formed over the entire operating region. Further, after desired patterning, an N + type source region 104 is diffused and formed on the main surface side of the P type base region.

【００１３】次いで、図１１（ａ），（ｂ）に示すよう
に、ゲート形成工程では、ソース領域１０４の中央部か
ら異方性エッチング（例えば反応性イオンエッチング：
ＲＩＥ）を行い、Ｐベース領域１０３を貫く深さでスト
ライブ状の卜レンチを形成する。このトレンチ１０５形
成後に、チップ全表面に熱酸化によりゲート酸化膜１０
６を形成し、ゲート電極１０７をＣＶＤ法によって形成
する。Next, as shown in FIGS. 11A and 11B, in the gate forming step, anisotropic etching (for example, reactive ion etching: from the central portion of the source region 104) is performed.
RIE) is performed to form a striped wrench with a depth that penetrates the P base region 103. After forming the trench 105, the gate oxide film 10 is formed on the entire surface of the chip by thermal oxidation.
6 is formed, and the gate electrode 107 is formed by the CVD method.

【００１４】ゲート電極１０７を形成した後のゲート配
線工程では、図１２（ａ），（ｂ），（ｃ）に示すよう
に、所望のパターニングを行い、ＲＩＥ等の異方性エッ
チングによって、ゲート電極引出し部１０９及びトレン
チ１０５内のみにゲート電極１０７を残す。これによっ
て、図１２（ｂ）に示すＦＥＴ領域のトレンチコーナー
部１１０での電界集中を回避することができる。In the gate wiring process after forming the gate electrode 107, as shown in FIGS. 12A, 12B, and 12C, desired patterning is performed and the gate is formed by anisotropic etching such as RIE. The gate electrode 107 is left only in the electrode lead-out portion 109 and the trench 105. As a result, electric field concentration at the trench corner portion 110 in the FET region shown in FIG. 12B can be avoided.

【００１５】このようにして、図９に示す構造のトレン
チ型ＦＥＴが得られた後は、図示はしないが、絶縁膜形
成工程を行い、ゲート電極引出し部１０９のゲート電極
１０７とゲート金属、及びソース領域１０４とソース金
属配線とを接触させるコンタクトホール形成工程を行
う。加えて、金属メタルの蒸着工程、パッシベーション
工程を経て、最終的に縦型トレンチＭＯＳＦＥＴが得ら
れる。After the trench type FET having the structure shown in FIG. 9 is obtained in this way, although not shown, an insulating film forming step is performed to form the gate electrode 107 of the gate electrode lead portion 109, the gate metal, and A contact hole forming step of contacting the source region 104 with the source metal wiring is performed. In addition, a vertical trench MOSFET is finally obtained through a metal metal vapor deposition process and a passivation process.

【００１６】[0016]

【発明が解決しようとする課題】しかしながら、上記従
来の縦型トレンチＭＯＳＦＥＴでは、トレンチ１０５に
充填されたゲート電極１０７がシリコン表面へ引出され
るため、このゲート電極引出し部１０９でのトレンチコ
ーナー部１０８ａ，１０８ｂを回避することができな
い。However, in the above-mentioned conventional vertical trench MOSFET, the gate electrode 107 filled in the trench 105 is drawn out to the silicon surface, so that the trench corner portion 108a at the gate electrode lead-out portion 109 is formed. , 108b cannot be avoided.

【００１７】さらに、ドレイン−ソース間耐圧のバラツ
キ抑制及びパターンの簡略化を図るため、Ｐベース領域
１０３をＦＥＴ動作領域全面に形成した後、トレンチゲ
ートを形成している。このため、ゲート酸化膜１０６形
成時にシリコン面が後退し、それによってシリコン上面
に形成されるゲート酸化膜１０６中にＰベース領域１０
３の不純物（ボロン）が取り込まれ、ゲート耐量を低下
させるという問題もあった。Further, in order to suppress variations in the breakdown voltage between the drain and the source and to simplify the pattern, the P base region 103 is formed over the entire surface of the FET operating region, and then the trench gate is formed. For this reason, the silicon surface recedes during the formation of the gate oxide film 106, whereby the P base region 10 is formed in the gate oxide film 106 formed on the silicon upper surface.
There is also a problem that the impurity (boron) of 3 is taken in and the gate withstand capability is lowered.

【００１８】この現象は、不純物濃度の高いシリコン表
面、つまりトレンチコーナー部１０８ａ，１０８ｂにお
いて顕著となる。これは、上記縦型トレンチＭＯＳＦＥ
Ｔ（図９）の試作品のゲート破壊がゲート電極引出し部
１０９のトレンチコーナー部１０８ａ，１０８ｂに集中
することからも、実験的に追認されている。This phenomenon becomes remarkable on the silicon surface having a high impurity concentration, that is, on the trench corner portions 108a and 108b. This is the vertical trench MOSFE
It is experimentally confirmed that the gate breakdown of the prototype of T (FIG. 9) is concentrated in the trench corner portions 108a and 108b of the gate electrode lead-out portion 109.

【００１９】このように、ゲート電極１０７をトレンチ
１０５内にのみ充填してトレンチコーナー部１０８ａ，
１０８ｂでの絶縁ゲート耐量の低下を回避しようとした
上記縦型トレンチＭＯＳＦＥＴであっても、ゲート電極
引出し部１０９でのトレンチコーナー部１０８ａ，１０
８ｂにおいては、依然として電界集中が発生するばかり
か、ゲート酸化膜１０６中への不純物の取り込まれ現象
も生じ、絶縁ゲート耐量の低下を十分に回避することが
できなかった。As described above, the gate electrode 107 is filled only in the trench 105 so that the trench corner portion 108a,
Even in the above-mentioned vertical trench MOSFET which is intended to avoid the deterioration of the withstand voltage of the insulated gate in 108b, the trench corner portions 108a, 10a in the gate electrode leading portion 109 are formed.
In 8b, not only electric field concentration still occurred, but also a phenomenon of impurities being taken into the gate oxide film 106 occurred, and it was not possible to sufficiently avoid the reduction of the insulated gate withstand voltage.

【００２０】本発明は、上述の如き従来の問題点を解決
するためになされたもので、その目的は、絶縁ゲート耐
量のばらつきを抑制した半導体装置を提供することであ
る。またその他の目的は、絶縁ゲート耐量の向上を可能
にした半導体装置を提供することである。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device in which variations in withstand voltage of an insulated gate are suppressed. Another object of the present invention is to provide a semiconductor device capable of improving the withstand voltage of the insulated gate.

【００２１】[0021]

【課題を解決するための手段】上記目的を達成するため
に、本発明の特徴は、第１導電型の半導体基板と、該半
導体基板の主面に形成された第１導電型の低濃度層と、
この低濃度層の上面に設けられた第２導電型第１半導体
不純物から成るチャネル形成層と、該チャネル形成層の
表面に部分的に設けられた第１導電型高濃度拡散第２半
導体不純物からなるソース領域と、前記ソース領域内に
表面より縦方向に前記チャネル形成層を貫いて前記低濃
度層に達する周期的に形成された複数の溝と、該各溝の
内壁面及び底面を被うゲート酸化膜と、該ゲート酸化膜
を介して前記各溝の内部に設けられたゲート電極と、該
ゲート電極が前記溝の終端部を越えて前記低濃度層上に
引き出されるゲート電極引き出し部とを備えた半導体装
置において、前記ゲート電極引き出し部に繋がる前記溝
の終端部に、前記チャネル形成層を形成しない構造とし
たことにある。In order to achieve the above object, a feature of the present invention is that a first conductivity type semiconductor substrate and a first conductivity type low concentration layer formed on a main surface of the semiconductor substrate. When,
From the channel formation layer formed of the second conductivity type first semiconductor impurity provided on the upper surface of the low concentration layer and the first conductivity type high concentration diffusion second semiconductor impurity partially provided on the surface of the channel formation layer. Covering the inner wall surface and the bottom surface of each source region, a plurality of periodically formed trenches that penetrate the channel forming layer in the source region in the longitudinal direction from the surface to reach the low concentration layer. A gate oxide film, a gate electrode provided inside each of the trenches via the gate oxide film, and a gate electrode lead-out portion where the gate electrode extends beyond the end of the trench and is drawn out onto the low-concentration layer. In the semiconductor device including, the channel forming layer is not formed at the terminal end of the groove connected to the gate electrode lead portion.

【００２２】また、上記発明において、前記ゲート電極
引き出し部に繋がる前記溝の終端部のみに、前記チャネ
ル形成層を形成しないようにしてもよい。Further, in the above invention, the channel forming layer may not be formed only in the terminal end portion of the groove connected to the gate electrode lead portion.

【００２３】また、上記発明において、前記ゲート電極
引き出し部に繋がる前記複数の溝の各終端部を全て含む
低濃度層の領域に、前記チャネル形成層を形成しないよ
うにしてもよい。Further, in the above invention, the channel forming layer may not be formed in the region of the low concentration layer including all the end portions of the plurality of trenches connected to the gate electrode lead portion.

【００２４】[0024]

【作用】上述の如き構成によれば、ゲート電極引き出し
部に繋がる溝の終端部にチャネル形成層を形成しないよ
うにしたので、該溝の終端部のコーナー部において、電
界集中が回避され、しかもゲート酸化膜中への不純物の
取り込まれ現象の発生が防げる。これにより、絶縁ゲー
ト耐量のばらつきが抑制され、絶縁ゲート耐量を向上さ
せることができる。According to the above-mentioned structure, since the channel forming layer is not formed at the terminal end of the groove connected to the gate electrode lead portion, electric field concentration is avoided at the corner of the terminal end of the groove, and It is possible to prevent impurities from being taken into the gate oxide film from occurring. As a result, variations in the withstand voltage of the insulated gate are suppressed, and the withstand voltage of the insulated gate can be improved.

【００２５】さらに、ゲート電極を溝内のみに形成する
ことにより、絶縁ゲート耐量のばらつき、及び絶縁ゲー
ト耐量が一層改善される。Furthermore, by forming the gate electrode only in the groove, the variation in the withstand voltage of the insulated gate and the withstand voltage of the insulated gate are further improved.

【００２６】[0026]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１は、本発明の半導体装置の第１実施例に係る
縦型トレンチＭＯＳＦＥＴの要部構成を示す立体斜視図
である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a three-dimensional perspective view showing the configuration of the main part of a vertical trench MOSFET according to the first embodiment of the semiconductor device of the present invention.

【００２７】このＭＯＳＦＥＴは、ゲート工程直後の構
成を示しており、高濃度（Ｎ＋）シリコン基板１と低濃
度（Ｎ−）シリコン基板２とが順次形成され、そのＮ−
シリコン基板２の表面にはＰベース領域３が拡散形成さ
れている。そして、そのＮ＋シリコン基板１とＮ−シリ
コン基板２とによってドレイン領域が形成され、Ｎ＋シ
リコン基板１の裏面側にはドレイン電極（図示省略）が
形成される。This MOSFET shows a structure immediately after the gate process, in which a high concentration (N + ) silicon substrate 1 and a low concentration (N − ) silicon substrate 2 are sequentially formed, and the N−
A P base region 3 is diffused and formed on the surface of the silicon substrate 2. A drain region is formed by the N + silicon substrate 1 and the N− silicon substrate 2, and a drain electrode (not shown) is formed on the back surface side of the N + silicon substrate 1.

【００２８】さらに、Ｐベース領域３の表面には部分的
にＮ＋型のソース領域４が拡散形成され、そのソース領
域４の表面中央部から縦方向に、Ｐベース領域３を貫い
て前記Ｎ−シリコン基板２に達する複数のトレンチ５が
ストライブ状に形成されている。また、Ｐベース領域３
の表面から各溝の内壁面及び底面を被うようにゲート酸
化膜６が形成され、そのトレンチ５内のゲート酸化膜６
上には多結晶シリコンからなるゲート電極７が形成され
ている。Further, an N + type source region 4 is partially formed on the surface of the P base region 3 by diffusion, and the N region is penetrated through the P base region 3 in the vertical direction from the center of the surface of the source region 4. -A plurality of trenches 5 reaching the silicon substrate 2 are formed in a stripe shape. In addition, the P base region 3
A gate oxide film 6 is formed so as to cover the inner wall surface and the bottom surface of each groove from the surface of the trench, and the gate oxide film 6 in the trench 5 is formed.
A gate electrode 7 made of polycrystalline silicon is formed on the top.

【００２９】そして、ゲート電極７が各トレンチ５の終
端部８を越えて前記Ｐベース領域３上のゲート酸化膜６
表面に引出されて、ゲート電極引出し部９が形成されて
いる。ここで、ゲート電極引出し部９に繋がる前記トレ
ンチ５の終端部８には、Ｐベース領域３が形成されない
ようにされている。すなわち、このトレンチ５の終端部
８における終端面及び側壁面のトレンチコーナー部８
ａ，８ｂには、Ｐベース領域３が形成されていない。Then, the gate electrode 7 crosses over the end portion 8 of each trench 5 and the gate oxide film 6 on the P base region 3 is formed.
The gate electrode lead-out portion 9 is formed by being led out to the surface. Here, the P base region 3 is not formed in the terminal portion 8 of the trench 5 connected to the gate electrode lead-out portion 9. That is, the trench corner portion 8 of the termination surface and the side wall surface of the termination portion 8 of the trench 5 is formed.
The P base region 3 is not formed in a and 8b.

【００３０】次に、このように構成される本実施例のＭ
ＯＳＦＥＴの製造工程を図２〜図６を用いて説明する。Next, the M of the present embodiment configured as described above
The manufacturing process of the OSFET will be described with reference to FIGS.

【００３１】図２（ａ），（ｂ）は、本実施例の拡散層
形成工程後のチップの構成を示す図であり、同図（ａ）
はその平面図、及び同図（ｂ）は図（ａ）のＣ−Ｃ´断
面図である。2 (a) and 2 (b) are views showing the structure of the chip after the diffusion layer forming step of this embodiment, and FIG.
Is a plan view thereof, and FIG. 6B is a sectional view taken along line CC ′ of FIG.

【００３２】同図に示すように、まず、Ｎ＋シリコン基
板１及びＮ−シリコン基板２をドレインとして形成した
後、拡散層形成工程として、Ｎ−シリコン基板２の表面
にチャネル層としてのＰベース領域３（ボロン）を拡散
形成する。この際、後に形成するゲート電極引出し部９
に繋がるトレンチ５の終端部８のみに対応するＮ−シリ
コン基板２の領域には、発明パターン１１によるマスキ
ングによりＰベース領域３を形成しない。As shown in the figure, first, the N + silicon substrate 1 and the N- silicon substrate 2 are formed as drains, and then in the diffusion layer forming step, a P base region as a channel layer is formed on the surface of the N- silicon substrate 2. 3 (boron) is formed by diffusion. At this time, the gate electrode lead-out portion 9 to be formed later
The P base region 3 is not formed in the region of the N-silicon substrate 2 corresponding to only the end portion 8 of the trench 5 connected to the P base region 3 by masking with the inventive pattern 11.

【００３３】さらに、拡散層形成工程として、所望のパ
ターニング後にＰ型ベース領域の主面側の所定領域にＮ
＋型のソース領域４を拡散形成する。但し、後にトレン
チ５の終端部８となる図２（ａ）のＣ−Ｃ´面は、通常
ＦＥＴ領域として活用しないため、ソース領域４を形成
しない。このようにして拡散層を形成した後は、ゲート
形成工程を行う。Further, as a diffusion layer forming step, after the desired patterning, N is formed in a predetermined region on the main surface side of the P-type base region.
The + type source region 4 is formed by diffusion. However, the CC ′ plane of FIG. 2A, which will be the terminal portion 8 of the trench 5 later, is not used as a normal FET region, and thus the source region 4 is not formed. After forming the diffusion layer in this manner, a gate forming step is performed.

【００３４】図３（ａ），（ｂ），（ｃ）は、本実施例
のゲート形成工程後のチップの構成を示す図であり、同
図（ａ）はその平面図、同図（ｂ）は図（ａ）のＡ−Ａ
´断面図、及び同図（ｂ）は同図（ａ）のＣ−Ｃ´断面
図である。FIGS. 3A, 3B and 3C are views showing the structure of the chip after the gate forming step of the present embodiment. FIG. 3A is its plan view and FIG. ) Is A-A in FIG.
′ Sectional view and FIG. 2B are sectional views taken along the line CC ′ of FIG.

【００３５】同図に示すように、ゲート形成工程では、
ソース領域４中央部に対して選択的に異方性エッチング
（例えばＲＩＥ）を行い、Ｐベース領域３を貫いてエッ
チングの底部がＮ−シリコン基板２内の所定の深さに達
するまでエッチングを進めてストライブ状の複数の卜レ
ンチを形成する。As shown in the figure, in the gate forming step,
Anisotropic etching (for example, RIE) is selectively performed on the central portion of the source region 4, and the etching is advanced until it penetrates the P base region 3 and the bottom of the etching reaches a predetermined depth in the N-silicon substrate 2. To form a plurality of striped wrenches.

【００３６】その際、トレンチ５の終端部８を、前記Ｐ
ベース領域３が形成されていないＮ−シリコン基板２の
領域（発明パターン１１）に形成する。これによって、
該トレンチ５の終端部８の終端面及び側壁面のトレンチ
コーナー部８ａ，８ｂにはＰベース領域３が形成されて
いないことになる。At this time, the end portion 8 of the trench 5 is connected to the P
It is formed in a region (invention pattern 11) of the N-silicon substrate 2 where the base region 3 is not formed. by this,
This means that the P base region 3 is not formed at the end surface of the end portion 8 of the trench 5 and the trench corner portions 8a and 8b of the side wall surface.

【００３７】引き続いて、例えばチップを酸化性雰囲気
で１０００℃程度に熱して、卜レンチの側壁及び底部全
面を含むチップ表面にゲート酸化膜６（ＳｉＯ2 ）を形
成する。その結果、Ｐベース領域３が形成されていない
前記トレンチコーナー部８ａ，８ｂに形成されるゲート
酸化膜６中には不純物が取り込まれることがない。Subsequently, for example, the chip is heated to about 1000.degree. C. in an oxidizing atmosphere to form a gate oxide film 6 (SiO.sub.2) on the surface of the chip including the side wall and the entire bottom surface of the wrench. As a result, impurities are not taken into the gate oxide film 6 formed in the trench corner portions 8a and 8b where the P base region 3 is not formed.

【００３８】さらに、ゲート酸化膜６の表面上に、例え
ばＳｉＨ4 の熱分解反応による減圧ＣＶＤ法（６００〜
６５０℃）によりゲート電極７を形成する。このような
ゲート形成工程の後にゲート配線工程を行う。Further, on the surface of the gate oxide film 6, for example, a low pressure CVD method (600-600) by a thermal decomposition reaction of SiH4.
The gate electrode 7 is formed at 650 ° C.). After such a gate forming process, a gate wiring process is performed.

【００３９】図４は、本実施例のゲート配線工程後のチ
ップの構成を示す平面図である。また、図５（ａ），
（ｂ），（ｃ）はその断面図であり、同図（ａ）は図４
のＡ−Ａ´断面図、同図（ｂ）は図４のＢ−Ｂ´断面
図、及び同図（ｃ）は図４のＣ−Ｃ´断面図である。FIG. 4 is a plan view showing the structure of the chip after the gate wiring process of this embodiment. In addition, FIG.
4B and 4C are cross-sectional views thereof, and FIG.
4A is a sectional view taken along the line A-A ', FIG. 4B is a sectional view taken along the line BB' in FIG. 4, and FIG. 4C is a sectional view taken along the line CC 'in FIG.

【００４０】ゲート電極７を形成した後のゲート配線工
程では、所望のパターニングを行い、ＲＩＥ等の異方性
エッチングによって、ゲート電極引出し部９及びトレン
チ５内のみにゲート電極７を残す。その際、図５
（ｂ），（ｃ）に示すように、ゲート電極７引き出し部
に繋がる前記トレンチ５の終端部８にはＰベース領域３
が形成されていないので、トレンチ５の終端部８のトレ
ンチコーナー部８ａ，８ｂでの電界集中が回避でき、ゲ
ート耐量を向上させることができる。In the gate wiring process after the gate electrode 7 is formed, desired patterning is performed and the gate electrode 7 is left only in the gate electrode lead-out portion 9 and the trench 5 by anisotropic etching such as RIE. At that time,
As shown in (b) and (c), the P base region 3 is formed in the terminal portion 8 of the trench 5 connected to the lead portion of the gate electrode 7.
Is not formed, it is possible to avoid electric field concentration at the trench corner portions 8a and 8b of the terminal end portion 8 of the trench 5 and improve the gate withstand capability.

【００４１】このようにして、図１に示す構造のトレン
チ型ＦＥＴが得られた後は、図示はしないが、チップの
表面に例えばリンガラス膜（ＰＳＧ）の層間絶縁膜を被
覆した後，エッチハック法等を用いて層間絶縁膜を平坦
化する絶縁膜形成工程を行う。After the trench type FET having the structure shown in FIG. 1 is obtained in this manner, although not shown, the surface of the chip is covered with an interlayer insulating film of, for example, phosphorus glass film (PSG), and then etched. An insulating film forming step of flattening the interlayer insulating film is performed by using a hack method or the like.

【００４２】次いで、フォトエッチング技術を用いて、
ゲート電極引出し部９のゲート電極７とゲート金属、及
びソース領域４とソース金属配線とを接触させるコンタ
クトホール形成工程を行う。さらに、Ａｌ等からなるソ
ース電極を選択的に形成すると共に、前記高濃度シリコ
ン基板の裏面にドレイン電極を形成する。さらにパッシ
ベーション工程を経て、最終的に縦型トレンチＭＯＳＦ
ＥＴが得られる。Then, using a photoetching technique,
A contact hole forming step of bringing the gate electrode 7 of the gate electrode lead-out portion 9 into contact with the gate metal and the source region 4 with the source metal wiring is performed. Further, a source electrode made of Al or the like is selectively formed, and a drain electrode is formed on the back surface of the high concentration silicon substrate. After a passivation process, the vertical trench MOSF is finally obtained.
ET is obtained.

【００４３】図６は、本発明の半導体装置の第２実施例
に係る縦型トレンチＭＯＳＦＥＴのゲート形成工程後の
チップの構成を示す平面図である。FIG. 6 is a plan view showing the structure of the chip after the gate forming step of the vertical trench MOSFET according to the second embodiment of the semiconductor device of the present invention.

【００４４】上記第１実施例と同様に、Ｎ＋シリコン基
板１及びＮ−シリコン基板２をドレインとして形成した
後、拡散層形成工程として、Ｎ−シリコン基板２の表面
にチャネル層としてのＰベース領域３を拡散形成する。
この際、図６に示すように、ゲート電極引出し部９に繋
がる全てのトレンチ５の終端部８を含むＮ−シリコン基
板２の領域を、発明パターン１１ａによるマスキングで
覆い、この領域にはＰベース領域３を形成しない。Similar to the first embodiment, after the N + silicon substrate 1 and the N− silicon substrate 2 are formed as drains, a P base region as a channel layer is formed on the surface of the N− silicon substrate 2 as a diffusion layer forming step. 3 is formed by diffusion.
At this time, as shown in FIG. 6, the region of the N-silicon substrate 2 including the end portions 8 of all the trenches 5 connected to the gate electrode lead-out portion 9 is covered by masking with the inventive pattern 11a, and the P base is formed in this region. Region 3 is not formed.

【００４５】そして、Ｐベース領域３形成後は、上記第
１実施例と同じ方法により、最終的に図５（ａ）〜
（ｃ）に示す断面構造と同一の構造を持つ縦型トレンチ
ＭＯＳＦＥＴを得ることができる。After the P base region 3 is formed, the same method as in the first embodiment is used to finally obtain the structure shown in FIGS.
A vertical trench MOSFET having the same structure as the sectional structure shown in (c) can be obtained.

【００４６】本実施例では、パターンの簡略化、リソグ
ラフィー工程での合わせずれマージン等に効果がある。The present embodiment is effective in simplifying the pattern, margin of misalignment in the lithography process, and the like.

【００４７】なお、本発明は上記実施例に限定されず種
々の変形が可能である。例えばその変形例として、上記
第１及び第２実施例では、周期的なトレンチ形成パター
ンとしてストライブ形状を用いたが、例えば図７
（ａ），（ｂ），（ｃ）に示すようなメッシュ形状のト
レンチ５ａであってもよい。この場合においても、ＦＥ
Ｔ部分のＡ−Ａ´の断面構造（図７（ｂ））、発明パタ
ーン１１のＢ−Ｂ´断面構造（図７（ｃ））、及び発明
パターン１１のＣ−Ｃ´断面構造（図７（ａ））は、上
記図５（ａ）〜（ｃ）に示すものと同一となり、上記第
１実施例と同様の効果が得られる。The present invention is not limited to the above embodiment, and various modifications can be made. For example, as a modification thereof, in the first and second embodiments described above, the stripe shape is used as the periodic trench formation pattern.
It may be a mesh-shaped trench 5a as shown in (a), (b) and (c). Even in this case, FE
Sectional structure A-A 'of the T portion (Fig. 7 (b)), BB' sectional structure of the invention pattern 11 (Fig. 7C), and CC 'sectional structure of the invention pattern 11 (Fig. 7). 5A is the same as that shown in FIGS. 5A to 5C, and the same effect as that of the first embodiment can be obtained.

【００４８】また、上述の実施例ではゲート電極が、ト
レンチ終端部から引出されているゲート電極引出しパタ
ーンについて説明したが、終端部ではなくトレンチの長
手方向（トレンチ側壁）から引出される、ゲート電極引
出し部パターンに関しても本発明を適用できる。Further, in the above-mentioned embodiments, the gate electrode lead-out pattern in which the gate electrode is led out from the trench end portion has been described. However, the gate electrode lead-out pattern is led out not in the end portion but in the longitudinal direction of the trench (trench side wall). The present invention can be applied to the drawer portion pattern.

【００４９】図８に上記トレンチ長手方向から引出され
るゲート電極引出し部パターンに本発明を適用した場合
の実施例を示す。ここで、図８（ａ）は平面図であり、
（ｂ）は（ａ）のＡ−Ａ´断面図であり、（ｃ）は
（ａ）のＢ−Ｂ´断面図であり、（ｄ）はＣ−Ｃ´断面
図である。FIG. 8 shows an embodiment in which the present invention is applied to the gate electrode lead-out portion pattern drawn out in the trench longitudinal direction. Here, FIG. 8A is a plan view,
(B) is an AA 'sectional view of (a), (c) is a BB' sectional view of (a), (d) is a CC 'sectional view.

【００５０】また、ここで、前記第１実施例と同じ要素
には同じ番号を付して詳しい説明は省略する。Here, the same elements as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

【００５１】このパターンは、Ｓｉ表面に引き出される
ゲート電極用ＰｏｌｙＳｉが覆うトレンチコーナーの数
を３から１ないし２に減少させ、最も電界の集中する終
端部コーナーを回避する様にしている。そして、ゲート
電極引出し下部にベース層を設けない技術を用いている
ことで、ゲート耐量の安定性をより向上させている。This pattern reduces the number of trench corners covered by the gate electrode PolySi for the Si surface from 3 to 1 or 2, and avoids the end corner where the electric field is most concentrated. The stability of the gate resistance is further improved by using a technique in which the base layer is not provided under the gate electrode lead-out portion.

【００５２】また、上記実施例では、トレンチ５の終端
部８となる図２（ａ）のＣ−Ｃ´面は、通常ＦＥＴ領域
として活用しないため、ソース領域４を形成しないよう
にしたが、ＦＥＴ領域として活用するのであれば、図１
０（ｂ）に示すような断面構造でＰベース領域３表面上
にソース領域４が形成されることになる。Further, in the above embodiment, the CC 'plane of FIG. 2A, which is the termination portion 8 of the trench 5, is not used as a normal FET region, so the source region 4 is not formed. If it is used as a FET area,
The source region 4 is formed on the surface of the P base region 3 with a sectional structure as shown in 0 (b).

【００５３】また、上記実施例では、便宜上Ｎチャネル
ＭＯＳＦＥＴを用いて説明したが、ＰチャネルＭＯＳＦ
ＥＴやＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）
等の他のトレンチゲートＭＯＳ型トランジスタ全般につ
いても、同様に本発明が適用されることはいうまでもな
い。In the above embodiment, the N-channel MOSFET is used for convenience, but the P-channel MOSF is used.
ET and IGBT (insulated gate bipolar transistor)
Needless to say, the present invention is similarly applied to other trench gate MOS type transistors in general.

【００５４】[0054]

【発明の効果】以上詳細に説明したように本発明によれ
ば、ゲート電極引き出し部に繋がる溝の終端部に、チャ
ネル形成層を形成しないようにしたので、絶縁ゲート耐
量のばらつきが抑制され、絶縁ゲート耐量を向上させる
ことができる。さらに、ゲート電極を溝内のみに形成す
ることにより、絶縁ゲート耐量のばらつき、及び絶縁ゲ
ート耐量を一層改善することが可能となる。As described in detail above, according to the present invention, since the channel forming layer is not formed at the terminal end portion of the groove connected to the gate electrode lead portion, the variation in the withstand voltage of the insulated gate is suppressed, The withstand voltage of the insulated gate can be improved. Furthermore, by forming the gate electrode only in the groove, it is possible to further improve the variation in the withstand voltage of the insulated gate and the withstand voltage of the insulated gate.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置の第１実施例に係る縦型ト
レンチＭＯＳＦＥＴの要部構成を示す立体斜視図であ
る。FIG. 1 is a three-dimensional perspective view showing a main configuration of a vertical trench MOSFET according to a first embodiment of a semiconductor device of the present invention.

【図２】第１実施例の拡散層形成工程後のチップの構成
を示す図である。FIG. 2 is a diagram showing a configuration of a chip after a diffusion layer forming step of the first embodiment.

【図３】第１実施例のゲート形成工程後のチップの構成
を示す図である。FIG. 3 is a diagram showing a configuration of a chip after a gate forming step of the first embodiment.

【図４】第１実施例のゲート配線工程後のチップの構成
を示す平面図である。FIG. 4 is a plan view showing the structure of the chip after the gate wiring process of the first embodiment.

【図５】第１実施例のゲート配線工程後のチップの構成
を示す断面図である。FIG. 5 is a cross-sectional view showing the structure of the chip after the gate wiring process of the first embodiment.

【図６】本発明の半導体装置の第２実施例に係る縦型ト
レンチＭＯＳＦＥＴのゲート形成工程後のチップの構成
を示す平面図である。FIG. 6 is a plan view showing the configuration of a chip after a gate forming step of a vertical trench MOSFET according to a second embodiment of the semiconductor device of the present invention.

【図７】本発明の変形例を示す図である。FIG. 7 is a diagram showing a modified example of the present invention.

【図８】本発明の半導体装置の第３実施例に係る縦型ト
レンチＭＯＳＦＥＴのゲート形成後の構成を示す図であ
る。FIG. 8 is a diagram showing a structure of a vertical trench MOSFET according to a third embodiment of the present invention after a gate is formed.

【図９】従来の縦型トレンチＭＯＳＦＥＴの構造を示す
立体斜視図である。FIG. 9 is a perspective view showing a structure of a conventional vertical trench MOSFET.

【図１０】従来の拡散層形成工程後のチップの構成を示
す図である。FIG. 10 is a diagram showing a configuration of a chip after a conventional diffusion layer forming step.

【図１１】従来のゲート形成工程後のチップの構成を示
す図である。FIG. 11 is a diagram showing a configuration of a chip after a conventional gate forming step.

【図１２】従来のゲート配線工程後のチップの構成を示
す図である。FIG. 12 is a diagram showing a configuration of a chip after a conventional gate wiring process.

【符号の説明】[Explanation of symbols]

１ Ｎ＋シリコン基板 ２ Ｎ−シリコン基板 ３ Ｐベース領域 ４ ソース領域 ５ トレンチ ６ ゲート酸化膜 ７ ゲート電極 ８ トレンチ５の終端部 ８ａ，８ｂ トレンチコーナー部 ９ ゲート電極引出し部 1 N + Silicon Substrate 2 N- Silicon Substrate 3 P Base Region 4 Source Region 5 Trench 6 Gate Oxide 7 Gate Electrode 8 End of Trench 5 8a, 8b Trench Corner 9 Gate Electrode Extraction

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型の半導体基板と、該半導体基
板の主面に形成された第１導電型の低濃度層と、この低
濃度層の上面に設けられた第２導電型第１半導体不純物
から成るチャネル形成層と、該チャネル形成層の表面に
部分的に設けられた第１導電型高濃度拡散第２半導体不
純物からなるソース領域と、前記ソース領域内に表面よ
り縦方向に前記チャネル形成層を貫いて前記低濃度層に
達する周期的に形成された複数の溝と、該各溝の内壁面
及び底面を被うゲート酸化膜と、該ゲート酸化膜を介し
て前記各溝の内部に設けられたゲート電極と、該ゲート
電極が前記溝の終端部を越えて前記低濃度層上に引き出
されるゲート電極引き出し部とを備えた半導体装置にお
いて、 前記ゲート電極引き出し部に繋がる前記溝の終端部に、
前記チャネル形成層を形成しない構造としたことを特徴
とする半導体装置。1. A first-conductivity-type semiconductor substrate, a first-conductivity-type low-concentration layer formed on the main surface of the semiconductor substrate, and a second-conductivity-type first substrate provided on the upper surface of the low-concentration layer. A channel forming layer made of a semiconductor impurity, a source region made of a first conductivity type high concentration diffusion second semiconductor impurity partially provided on a surface of the channel forming layer, and a source region in the source region in a vertical direction from the surface. A plurality of periodically formed grooves that penetrate the channel forming layer to reach the low concentration layer, a gate oxide film that covers the inner wall surface and the bottom surface of each groove, and a gate oxide film that covers each groove through the gate oxide film. A semiconductor device comprising: a gate electrode provided inside; and a gate electrode lead-out portion where the gate electrode extends beyond the end portion of the groove and is led out onto the low-concentration layer, wherein the groove connected to the gate electrode lead-out portion At the end of
A semiconductor device having a structure in which the channel formation layer is not formed. 【請求項２】 前記ゲート電極引き出し部に繋がる前記
溝の終端部のみに、前記チャネル形成層を形成しないこ
とを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the channel forming layer is not formed only on the terminal end portion of the groove connected to the gate electrode lead portion. 【請求項３】 前記ゲート電極引き出し部に繋がる前記
複数の溝の各終端部を全て含む低濃度層の領域に、前記
チャネル形成層を形成しないことを特徴とする請求項１
記載の半導体装置。3. The channel formation layer is not formed in a region of a low concentration layer including all end portions of the plurality of trenches connected to the gate electrode lead portion.
13. The semiconductor device according to claim 1.
JP6157108A 1994-07-08 1994-07-08 Semiconductor device Pending JPH0823096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6157108A JPH0823096A (en) 1994-07-08 1994-07-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6157108A JPH0823096A (en) 1994-07-08 1994-07-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0823096A true JPH0823096A (en) 1996-01-23

Family

ID=15642411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6157108A Pending JPH0823096A (en) 1994-07-08 1994-07-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0823096A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999012214A1 (en) * 1997-08-29 1999-03-11 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method for manufacturing the same
US6004888A (en) * 1996-07-16 1999-12-21 Teijin Limited Fibrous sheet for structure reinforcement and structure reinforced with same
JP2003282870A (en) * 2002-03-20 2003-10-03 Fuji Electric Co Ltd Semiconductor device and its fabricating method
KR100486349B1 (en) * 1997-09-30 2006-04-21 페어차일드코리아반도체 주식회사 Trench power mosfet
JP2006294713A (en) * 2005-04-07 2006-10-26 Fuji Electric Holdings Co Ltd Semiconductor device
JP2007059459A (en) * 2005-08-22 2007-03-08 Fuji Electric Device Technology Co Ltd Mos semiconductor device
JP2007234850A (en) * 2006-03-01 2007-09-13 Mitsubishi Electric Corp Semiconductor device
JP2009141149A (en) * 2007-12-06 2009-06-25 Denso Corp Insulated gate transistor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004888A (en) * 1996-07-16 1999-12-21 Teijin Limited Fibrous sheet for structure reinforcement and structure reinforced with same
WO1999012214A1 (en) * 1997-08-29 1999-03-11 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method for manufacturing the same
EP1009035A1 (en) * 1997-08-29 2000-06-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method for manufacturing the same
US6285058B1 (en) 1997-08-29 2001-09-04 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method of manufacturing the same
EP1009035A4 (en) * 1997-08-29 2003-01-08 Mitsubishi Electric Corp Insulated gate semiconductor device and method for manufacturing the same
KR100486349B1 (en) * 1997-09-30 2006-04-21 페어차일드코리아반도체 주식회사 Trench power mosfet
JP2003282870A (en) * 2002-03-20 2003-10-03 Fuji Electric Co Ltd Semiconductor device and its fabricating method
JP2006294713A (en) * 2005-04-07 2006-10-26 Fuji Electric Holdings Co Ltd Semiconductor device
JP2007059459A (en) * 2005-08-22 2007-03-08 Fuji Electric Device Technology Co Ltd Mos semiconductor device
JP2007234850A (en) * 2006-03-01 2007-09-13 Mitsubishi Electric Corp Semiconductor device
JP2009141149A (en) * 2007-12-06 2009-06-25 Denso Corp Insulated gate transistor

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