JPH01138788A - Through-hole circuit substrate and manufacture thereof - Google Patents
Through-hole circuit substrate and manufacture thereofInfo
- Publication number
- JPH01138788A JPH01138788A JP62296120A JP29612087A JPH01138788A JP H01138788 A JPH01138788 A JP H01138788A JP 62296120 A JP62296120 A JP 62296120A JP 29612087 A JP29612087 A JP 29612087A JP H01138788 A JPH01138788 A JP H01138788A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- hole
- circuit board
- insulating layer
- solidus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 title abstract description 6
- 229910000679 solder Inorganic materials 0.000 claims abstract description 126
- 238000000034 method Methods 0.000 claims abstract description 51
- 230000004907 flux Effects 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000007787 solid Substances 0.000 claims description 7
- 238000005553 drilling Methods 0.000 claims description 6
- 239000002245 particle Substances 0.000 abstract description 19
- 238000007650 screen-printing Methods 0.000 abstract description 9
- 238000005476 soldering Methods 0.000 abstract description 7
- 239000004020 conductor Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 15
- 239000000956 alloy Substances 0.000 description 15
- 239000000203 mixture Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000011135 tin Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- BOSAWIQFTJIYIS-UHFFFAOYSA-N 1,1,1-trichloro-2,2,2-trifluoroethane Chemical compound FC(F)(F)C(Cl)(Cl)Cl BOSAWIQFTJIYIS-UHFFFAOYSA-N 0.000 description 5
- -1 amine hydrochloride Chemical class 0.000 description 5
- 239000011133 lead Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000004506 ultrasonic cleaning Methods 0.000 description 5
- 239000004698 Polyethylene Substances 0.000 description 4
- 230000005496 eutectics Effects 0.000 description 4
- 229920000573 polyethylene Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 3
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012190 activator Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002529 flux (metallurgy) Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007373 indentation Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011038 discontinuous diafiltration by volume reduction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000025 natural resin Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 210000001215 vagina Anatomy 0.000 description 1
- 239000004034 viscosity adjusting agent Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
〔産業上の利用分野〕
本発明は、低コストで生産性・信頼性の高いスルーホー
ル回路基板、およびその製造方法に関するものである。
〔従来の技術〕
従来、スルーホール回路基板は主にサブトラクティブ法
により作成されていた。つまり、両面銅張積層板にスル
ーホール用の穴あけを行い、次に化学めっきのための活
性化処理および化学めっき処理を行い、次いで電気めっ
きによシ必要な膜厚分をつけ、その後にスルーホール部
および回路導体部のところをレジストでマスキングし、
不要部全エツチング除去する方法である。この方法によ
り、高信頼性のスルーホール回路を形成することができ
るが、特に化学めっき工程において、その処理工程数お
よび使用薬液が多いために処理時間が長く、また材料費
が高価になるため、生産性および経済性に問題があった
○
よシ生産性を向上したスルーホール回路の製造方法とし
て、導電性接着剤を用いる方法がある。
これはスルーホール用の穴あけを行った後、その穴にス
クリーン印刷法あるいはデイスペンサを用いた方法など
により導電性接着剤を流し込み、加熱硬化させて両面導
体の導通をとる方法である。
この方法は生産性には優れるものの、経済性・信頼性に
多少の問題があり、また導電性接着剤の比抵抗が銅に比
べて１〜２桁高いこと、および導−電性接着剤と銅との
界面で接触抵抗が生ずることによシ、形成されたスルー
ホール抵抗は上述のサブトラクティブ法によるものより
かなり高くなる。
なお、上述と同じ方法で、経済性・信頼性の点から導電
性接着剤の代わりにはんだペーストラ用いる方法も考え
られる。第５図は従来の共晶はんだペースト（Ｓｎ／Ｐ
ｂ ＝ ６３／３７ ） ｆ使用しタスルーホール回路
基板の断面図である。図において、１は積層体で絶縁層
２と導電層３，３′からなっている。らはスルーホール
用の穴、７はリフローされたはんだ、８ははんだリフロ
ー時にフラックスが活性化することにより発生したガス
によって形成され次空間である。このように従来の共晶
はんだペーストを用いる方法ではガスの発生や、はんだ
特有の表面張力の高さのために導電層３．３”ｉ結ぶは
んだのブリッジが起こらず、両導電層間の導通をとるの
が困難であった。
〔発明が解決しようとする問題点〕
このように従来のスルーホール回路基板およびその製造
方法にお′ｂては、工程が複雑でかつ使用薬品の種類が
多いために高価格を招いたり、導電層間の接続不良や接
続強度の不足または接合部の高抵抗化など信頼性にかけ
たりする欠点があった。
本発明はこのような従来の欠点を解消し、低価格でかつ
信頼性の高いスルーホール回路基板およびその製造方法
を提供することを目的とする。
〔問題点を解決するための手段〕
すなわち本発明は、絶縁層を挾んでその両面にそれぞれ
導電層が積層された部分を有する積層体を用いたスルー
ホール回路基板において、絶縁層の両面に積層された導
電層が、異なる固相線と液相＋ｇｉｌヲ持つはんだ合金
により接続されていることを特徴とするスルーホール回
路基板である。
また本発明は、絶縁層金挾んでその両面にそれぞれ導電
層が積層された部分を有する積層体を用いたスルーホー
ル回路基板の製造方法において、少なくとも積層体にス
ルーホール用の穴をあける工程と、該穴に１固相線と液
相線とが異なるはんだ粒とフラックスとから成るはんだ
ペーストを充填する工程と、はんだペーストを、はんだ
粒の固相線温度以上に加熱してはんだ粒の少なくとも一
部分をリフローさせる工程とを含むこと全特徴とするス
ルーホール回路基板の１３ｉ造法である。
〔作 用〕
本発明によれば、絶縁層の両面にそれぞれｉ層され九導
？ｌ［ｊがはんだ按よって接続されるので、接続部にお
ける電気抵抗が小さく、接合の強度が高い。さらにリフ
ロー工程において溶融はんだ中に固体のけんだ粒が分散
された状態を経るので、導１！層間のはんだのブリッジ
発生が容易になり導通不良を生じることがなく、導電層
間の導通を確実に行うことができる。従って簡単な方法
で信頼性の高いスルーホール回路基板を低価格で得るこ
とができる。
〔実施例〕
以下に図面′ｆＣ参照して本発明の詳細な説明する。
第１図は本発明のスルーホール回路基板の一実施例の断
面図である。図において１は積層体で、絶縁層２および
それぞれ絶縁層２を挾んで設けられた例えば銅、銀など
からなる導電層３，３′からなっている。５は積層体１
を貫通する穴である。
４．４′は穴５を埋め、導電層３と３′とを導通させる
はんだであるが、各々のはんだの合金組成は異なってい
る。
第１図に示した実施例の作製法を第２図（Ａ） −（Ｃ
）を参照して説明する。
工程（１）：まず絶縁層２を挾んで両側に導電層３，３
′が設けられている積層体１にスルーホール用の穴５′
ｆｔあける（第２図（Ａ））。
工程（２）：次にはんだ粒４Ａとフラックス６を混合し
たはんだペーストをスクリーン印刷法あるいはデイスペ
ンサその他を用いる方法によって穴５内に充填する（第
２図中））。
工程（３）：そしてはんだ粒の固相線以下の温度で予備
加熱した後、はんだ粒の固相線温度以上に加熱してす７
０−させ冷却して凝固させる。この工程によってはんだ
粒の少なくとも一部分が溶融し、導電層３，３′を電気
的に導通させるはんだブロック４および４′となる。（
第２図Ｃ）、第１図）このようにして得られたスルーホ
ール回路基板は、その製造工程がｆ７ｄ単であるにもか
かわらず、１ノア０−時に発生するガスやはんだ自体の
表面張力の高さのためによる導通不良を生ずることなく
、確実に導通をとることができる。また導電層とはんだ
との接合強度が高く、また接合部の比抵抗全署しく低く
することができる。
積層体１はどのような方法によって製造されたものでも
よく、ｔた導電層、絶縁層、導電層からなる連続した３
層を含んでいれば、他の層がさらに積層されていても差
し支えない。
絶縁層２の厚みはあまり大きすぎると絶縁層を挾んだ２
つの導電層の導通が困難となるので２ｗ２以下、さらに
は５００μｍ以下、さらには１００μｍ以下が好ましい
。
積層体のスルーホール部の断面構造は第１図に示した形
状に限られず、スルーホール用穴の形成方法及びはんだ
ペーストの組成、充填量充填形態などによって異な９第
３図（４）ｋ示すように、スルーホール部の壁面５Ａに
のみ、全周にわ九ってはんだ４および４′が形成されて
導電層３．３′を導通させる構造、第３図の）のように
１スル一ホール部の壁面５Ａの一部にはんだ４および４
′が形成されて導電層３，３′を導通させる構造、第３
図Ｃ）の↓うにスルーホール用の穴が導電層３と絶縁層
２のみに設けられ、はんだ４および４′が導電層３′上
に載って導電層３と３′とを導通させる構造、第３図（
Ｄ）に示すように、はんだ４および４′が積層体の表側
にまで出つばって形成されて導電層３，３′ を導通さ
せる構造、あるいは以上の混合型など種々の構造が可能
である。
以下に本発明の細部について、詳細に説明する。
導電層の材質は、溶融はんだとの濡れ性が良いことが必
要である。実際には導電層との濡れ性の良いはんだ全選
択することにより＼銅、銀、金、白金、鉛、錫、鉄、ニ
ッケル、インジウム、アルミニウム、ステンレスおよび
上記２種以上の金属から成る合金が４Ｍ１層として使用
できるが一般的には銅、銀、金が好ましく、経済性の点
からは特に銅が好ましい。
はんだの材質としては、導電層との濡れ性が良く、且つ
異なる固相線と液相線が異なる組成のものであれば何で
も良い。
前者の条件を満たすものとしては、はんだの少なくとも
一部分が導電層と合金組織を形成する必要があり、例え
ば導電層が銅の場合では特に銅と合金を作りやす騒すず
を含むはんだが好ましい。
具体例としては、鉛、ビスマス、インジウム、銀、カド
ミウム、水銀、亜鉛、アンチモンのうちの少なくとも一
種を含むすす合金が挙げられる。また後者の条件につｂ
ては、溶融はんだ中に存在する固体状のはんだ粒の割合
が、極端に少ない、共晶組成に近いはんだは導電層３と
３′のブリッジが起こりにぐくなるので好ましくない。
具体的には、固相線温度における固体状のはんだ粒の割
合が体積比ではんだ全体の０．５％以上、更には３チ以
上、更には５チ以上となるような組成のはんだが好まし
い。以上の２条件に加え、リフロー時の積層体の耐熱性
を考慮してはんだ材質全決定すれば良い。
なお、本発明下いうはんだとは導電層と合金組織を形成
可能な金属を含む合金を指す。
はんだ粒の粒径はスルーホール用穴の直径より小さなこ
とが当然必要であるが、はんだペーストの印刷・塗布性
を考慮すると１５０μｍ以下、さらには７５μｍ以下が
好ましい。１＋、粘度偏析ｆ、避けるためには均一の粒
径のものを使用した方が好ましい。またはんだ粒の形状
も印刷・塗布性を考慮して選定されるが、一般にはメタ
ルマスクを使用する場合及び後述の押し込み法の場合は
不定形、メツシュスクリーン・デイスペンサを使用する
場合は球形の方が好ましい。
フラックスは、樹脂系フラックス、特に活性化樹脂フラ
ックスが好ましい。これはロジン系天然樹脂ま１ヒはそ
の変性樹脂を主成分とし、これに活性剤・有機溶剤・粘
度調整剤・その他の添加剤が添加されたものである。一
般に、変性樹脂には重合ロジン、フェノール樹脂変性ロ
ジンなど、活性剤には無機系および有機系フラックス、
その中でも特にアミン塩酸塩や有機酸系のフラックス、
有機溶剤はカルピトール系、エーテル系のものが用いら
れる。
フラックス量については、少なくとも一部かリフローし
たはんだ粒間の一体化を引き起こすのに充分な量が必要
であり、はんだ粒の５ ｗｔ％以上、さらには７ ｗｔ
％以上、さらにはｔ ｏ ｗｔ ％ 以上が好ましいが
印刷・塗布性及びす７０−後の体積減少率を考慮して適
宜決定すればよい。
穴あけは、ばり、かす等が発生せず穴の周囲の導電層が
絶縁層から剥離しなければ、いかなる方法によっても良
く、例えばドリル・パンチ等が使用さ在る。また穴は第
２図（４）のような貫通穴に限らず絶縁層全快んだ２つ
の導電層が導通可能であれば良く、第３図（Ｃ）のよう
な穴でもよい。穴径については特に限定はしないが、第
２図Φ）に示すようにはんだペーストラ充填する場合で
は穴径が大きすぎると充填が困難となるので直径で３Ｉ
ＩＪＩ以下、さらには２貼以下、さらには１藺以下が望
ましい。
上述のはんだ粒、フラックスで構成され之はんだペース
トは、スクリーン印刷法あるいはデイスペンサなどを用
いた方法あるいは後述の押し込み法などによりスルーホ
ール用穴に塗布されるが、生産性の点からスクリーン印
刷法あるいは押し込み法の方がより好ましい。
スクリーン印刷法には、スルーホール部以外に乳剤ヲ張
つ念メツシュスクリーンやスルーホール部のみに貫通穴
をあけたメタルマスクを用いる方式などがあり、いずれ
も使用できる。なお、基板とスクリーン・マスクの相対
位置のズレによりスルーホール導通不良が発生するＦ４
ｊ合には、穴あけ工程の前に積層体の少なくとも片面に
導電層金被覆する膜全形成し７た後、膜全形成ｌ−友面
側からスルーホール穴６ ケ’ｃ行い、スクリーン番マ
スク全用いずに直接、膜を形成し次面（ｔｉｌｌからは
んだペーストをスルー・ホール用ン′（：に光填り、で
も良い。充填方法としては通附のスクリーン印刷法と同
様のスキージ等を用い素手法が生産性の点では好ましい
（押し込み法）０また前記被覆膜はスルーホール用穴へ
のはんだペースト充填工程以降で剥離しても良いし、剥
離せずに製品に残しても良い。なお、塗布形態は第２図
（Ｂ）に示し友形態に限らず、絶縁層を挾んだ２つの導
電層が導通可能な状態であれば良く、例えば第４図のよ
うに穴５の壁面５Ａに塗布した形態でもよい。これは、
スルーホール径が大きい場合により有効であり、メツシ
ュスクリーンを用い念場合に特に実現容易である。
予備加熱は、リフロー時の急激な温度上昇による基板へ
の熱応力を緩和するためと同時に１．フラックス中の揮
発成分を完全に放散させリフロー時のガス発生を抑える
効果があり、行うことが好まし、い。加熱温度ははんだ
粒の固相線[Industrial Application Field] The present invention relates to a low-cost, highly productive and reliable through-hole circuit board, and a method for manufacturing the same. [Prior Art] Conventionally, through-hole circuit boards have been mainly produced by a subtractive method. In other words, holes are drilled for through holes in double-sided copper-clad laminates, then activation treatment and chemical plating treatment are performed for chemical plating, then electroplating is applied to the required film thickness, and then through-holes are formed. Mask the hole part and circuit conductor part with resist,
This method removes all unnecessary parts by etching. Although this method makes it possible to form highly reliable through-hole circuits, it requires a long processing time and high material costs, especially in the chemical plating process due to the large number of processing steps and the large number of chemicals used. There were problems with productivity and economic efficiency ○ There is a method of manufacturing through-hole circuits that improves productivity by using a conductive adhesive. This method involves drilling holes for through-holes, then pouring a conductive adhesive into the holes using a screen printing method or a method using a dispenser, and heating and hardening the adhesive to establish continuity between the double-sided conductors. Although this method has excellent productivity, there are some problems with economy and reliability, and the specific resistance of the conductive adhesive is one to two orders of magnitude higher than that of copper. Due to the contact resistance created at the interface with the copper, the resistance of the formed through-hole is much higher than with the subtractive method described above. Note that, in the same manner as described above, a method of using solder pastera instead of the conductive adhesive from the viewpoint of economy and reliability may also be considered. Figure 5 shows the conventional eutectic solder paste (Sn/P
b = 63/37) f is a cross-sectional view of a through-hole circuit board using TAS. In the figure, numeral 1 denotes a laminate consisting of an insulating layer 2 and conductive layers 3 and 3'. are holes for through holes, 7 is reflowed solder, and 8 is a space formed by gas generated by activation of flux during solder reflow. In this way, in the conventional method using eutectic solder paste, a solder bridge connecting the conductive layer 3.3"i does not occur due to the generation of gas and the high surface tension peculiar to solder, and the conduction between both conductive layers is prevented. [Problems to be solved by the invention] As described above, conventional through-hole circuit boards and their manufacturing methods have complicated processes and use many types of chemicals. However, the present invention solves these conventional drawbacks, resulting in low cost and low cost. It is an object of the present invention to provide a through-hole circuit board that is large and highly reliable, and a method for manufacturing the same. A through-hole circuit board using a laminate having laminated parts, characterized in that conductive layers laminated on both sides of an insulating layer are connected by a solder alloy having different solidus and liquid phases. The present invention also provides a method for manufacturing a through-hole circuit board using a laminate having conductive layers laminated on both sides of an insulating layer sandwiched between two insulating layers. A step of drilling a hole for a hole, a step of filling the hole with a solder paste consisting of solder grains and a flux whose solidus line and liquidus line are different, and a step of filling the hole with a solder paste consisting of solder grains and a flux that are equal to or higher than the solidus temperature of the solder grains. This is a 13i manufacturing method for a through-hole circuit board, which is characterized in that it includes a step of reflowing at least a portion of the solder grains by heating the solder grains to a temperature of 13i. Since the solder is connected by rolling the solder, the electrical resistance at the connection part is low and the strength of the joint is high.Furthermore, solid solder particles are dispersed in the molten solder in the reflow process. Therefore, solder bridges between conductive layers can easily occur, preventing conduction defects and ensuring conduction between conductive layers.Therefore, it is possible to easily create a highly reliable through-hole circuit board with low cost. [Embodiment] The present invention will be described in detail below with reference to drawing 'fC. Fig. 1 is a sectional view of an embodiment of the through-hole circuit board of the present invention. Reference numeral 1 denotes a laminate, which is composed of an insulating layer 2 and conductive layers 3 and 3' made of copper, silver, etc., each sandwiching the insulating layer 2. 5 is a laminate 1.
It is a hole that passes through. 4.4' is a solder that fills the hole 5 and connects the conductive layers 3 and 3', but the alloy composition of each solder is different. The manufacturing method of the example shown in FIG. 1 is shown in FIGS.
). Step (1): First, conductive layers 3, 3 are placed on both sides of the insulating layer 2.
A hole 5' for a through hole is formed in the laminate 1 in which a hole 5' is provided.
ft open (Figure 2 (A)). Step (2): Next, solder paste containing solder grains 4A and flux 6 is filled into the holes 5 by screen printing or a method using a dispenser or the like (see FIG. 2). Step (3): Then, after preheating at a temperature below the solidus line of the solder particles, the solder particles are heated to a temperature above the solidus line7.
Cool to 0 and solidify. This process melts at least a portion of the solder grains, forming solder blocks 4 and 4' which electrically connect the conductive layers 3 and 3'. (
Figure 2 C), Figure 1) The through-hole circuit board obtained in this way is manufactured by a simple f7d manufacturing process, but the surface tension of the gas generated at 1 nore and the solder itself is Conductivity can be ensured without causing conduction failure due to the height of the cap. Further, the bonding strength between the conductive layer and the solder is high, and the specific resistance of the bonded portion can be completely reduced. The laminate 1 may be manufactured by any method, and may be made of three consecutive layers consisting of a conductive layer, an insulating layer, and a conductive layer.
There is no problem even if other layers are further laminated. If the thickness of the insulating layer 2 is too large, the thickness of the insulating layer 2 may be too large.
Since it becomes difficult to conduct two conductive layers, the thickness is preferably 2w2 or less, more preferably 500 μm or less, and even more preferably 100 μm or less. The cross-sectional structure of the through-hole portion of the laminate is not limited to the shape shown in Fig. 1, but may vary depending on the method of forming the through-hole hole, the composition of the solder paste, the filling amount, and the filling form, etc. 9 Fig. 3 (4) k As shown in FIG. Solders 4 and 4 are placed on a part of the wall surface 5A of the hole.
' is formed to make the conductive layers 3 and 3'conductive;
As shown in Figure C), holes for through holes are provided only in the conductive layer 3 and the insulating layer 2, and the solders 4 and 4' are placed on the conductive layer 3' to connect the conductive layers 3 and 3', Figure 3 (
As shown in D), various structures are possible, such as a structure in which the solders 4 and 4' extend to the front side of the laminate to provide electrical continuity between the conductive layers 3 and 3', or a mixed structure of the above. . The details of the present invention will be explained in detail below. The material of the conductive layer needs to have good wettability with molten solder. In reality, by selecting all solders that have good wettability with the conductive layer, copper, silver, gold, platinum, lead, tin, iron, nickel, indium, aluminum, stainless steel, and alloys consisting of two or more of the above metals are available. Although it can be used as a 4M1 layer, copper, silver, and gold are generally preferred, and copper is particularly preferred from the economic point of view. Any material may be used for the solder as long as it has good wettability with the conductive layer and has a composition with different solidus lines and liquidus lines. In order to satisfy the former condition, at least a portion of the solder must form an alloy structure with the conductive layer. For example, in the case where the conductive layer is copper, a solder containing tin, which is particularly easy to form an alloy with copper, is preferable. Specific examples include soot alloys containing at least one of lead, bismuth, indium, silver, cadmium, mercury, zinc, and antimony. Also, regarding the latter condition b
Specifically, a solder having an extremely low proportion of solid solder grains in the molten solder, which is close to a eutectic composition, is not preferable because bridging between the conductive layers 3 and 3' is less likely to occur. Specifically, it is preferable to use a solder having a composition such that the proportion of solid solder grains at the solidus temperature is 0.5% or more of the total solder in terms of volume ratio, furthermore, 3 parts or more, and still more preferably 5 parts or more. . In addition to the above two conditions, all solder materials may be determined in consideration of the heat resistance of the laminate during reflow. Note that the solder in the present invention refers to an alloy containing a metal capable of forming an alloy structure with a conductive layer. Although it is naturally necessary that the particle size of the solder particles be smaller than the diameter of the through hole, it is preferably 150 μm or less, more preferably 75 μm or less, considering the printing and coating properties of the solder paste. 1+, it is preferable to use particles with uniform particle size in order to avoid viscosity segregation f. The shape of the solder particles is also selected taking printability and applicability into consideration, but in general, they are irregular when using a metal mask or the indentation method described below, and spherical when using a mesh screen dispenser. is preferable. The flux is preferably a resin-based flux, particularly an activated resin flux. This is mainly composed of a rosin-based natural resin or a modified resin thereof, to which an activator, an organic solvent, a viscosity modifier, and other additives are added. In general, modified resins include polymerized rosin and phenolic resin-modified rosin, and activators include inorganic and organic fluxes,
Among them, amine hydrochloride and organic acid fluxes,
The organic solvent used is carpitol type or ether type. Regarding the amount of flux, it is necessary to have a sufficient amount to cause integration between at least some of the reflowed solder particles, and it is 5 wt% or more of the solder particles, or even 7 wt%.
% or more, more preferably t wt % or more, but it may be determined as appropriate in consideration of printing/applying properties and volume reduction rate after 70%. The holes may be formed by any method as long as no burrs, debris, etc. are generated and the conductive layer around the hole does not peel off from the insulating layer, such as using a drill or punch. Further, the hole is not limited to a through hole as shown in FIG. 2(4), but may be a hole as shown in FIG. 3(C) as long as the two conductive layers having completely recovered insulating layers can be electrically connected. There is no particular limitation on the hole diameter, but as shown in Figure 2 Φ), if the hole diameter is too large, it will be difficult to fill it with solder paste, so the diameter should be 3I.
IJI or less, preferably 2 or less, even 1 or less is desirable. The solder paste, which is composed of the solder grains and flux mentioned above, is applied to the through-holes by the screen printing method, a method using a dispenser, or the pushing method described below. However, from the viewpoint of productivity, the screen printing method or The indentation method is more preferred. Screen printing methods include a mesh screen in which the emulsion is applied in areas other than the through-hole areas, and a metal mask in which through-holes are formed only in the through-hole areas, and any of these methods can be used. In addition, in F4, through-hole conduction failure occurs due to misalignment of the relative position of the board and screen mask.
In this case, before the hole-drilling step, after forming a conductive layer on at least one side of the laminate, a through-hole hole 6 is formed from the opposite side of the layer, and a screen number mask is formed. It is also possible to directly form a film without using the solder paste on the next surface (till) and fill it with light into the through-holes.As a filling method, use a squeegee or the like similar to the screen printing method described in the accompanying article. The bare method used is preferable in terms of productivity (pushing method)0 Also, the coating film may be peeled off after the process of filling the solder paste into the through hole, or it may be left on the product without being peeled off. Note that the application form is not limited to the one shown in Fig. 2(B), but may be any state in which two conductive layers sandwiching an insulating layer can be electrically conductive.For example, as shown in Fig. 4, It may also be applied to the wall surface 5A.
This method is more effective when the diameter of the through hole is large, and is particularly easy to implement when a mesh screen is used. Preheating is performed at the same time as 1. to relieve thermal stress on the substrate due to the rapid temperature rise during reflow. It is preferable to do this because it has the effect of completely dissipating the volatile components in the flux and suppressing gas generation during reflow. The heating temperature is the solidus line of the solder grains.
【温度以下であることが必要であるが、基板
の耐熱温度と合わせて決定すれば良い。はんだ材質が例
えばＳｎ−・Ｐｈ＝六合金合金合では１３０℃〜】６０
℃付近が好腟しい。こス・１．より高すぎるとフラック
スが硬化し、はんだ付性が悪くなり、また低すぎるとフ
ラックスの揮発成分の放散が不充分でガスの滞留ケ起こ
し、はんだ子連れの原因となる。加熱時間も基板の熱容
量、はんだペーストの量、フラックスの量・種類、加熱
方式などにより異なるが、基板の表面が規定の温度に達
してから１〜３分間程度が好ましい。
す７０−温度は、用いるはんだ粒の固相線温度以上であ
ることが最低限必要である。リフロー温度は基板の耐熱
性及びスルーホール接続の信頼性に応じて決定すれば良
いが、はんだの組成によっては設定温度が低すぎると溶
融はんだの割合が少なくはんだ粒間の合体が起こらない
場合がある。
この友め溶融はんだの割合が体積比で元の全部のはんだ
粒の１０％以上さらには２０％以上となるような温度で
リフローすることが好ましい。なお、スルーホール導通
は前述の合金組成のはんだ粒を用いる限り、リフロー工
程で一部溶融したはだが残りの固体はんだ粒同士を合体
させることにより起こり、−庇上下導電層間のはんだブ
リッジが起こればその後完全にはんだを溶融させた状態
にしても、またその後冷却凝固させてもスルーホール導
通は保定れる。
すなわち、スルーホール導通は上述のりフロー温度条件
を満足する限り、用いるはんだ粒の合金組成、導電層・
絶縁層の厚み等によって一義的に決定するので、用いる
はんだ粒の固相線−液相線間及び液相線以上のいずれの
温度でリフローさせてもよい。
上限温度は主に基板の耐熱性によって決するが、あまり
高すぎるとフラックスが炭化し活性作用がなくなるので
注意が必要である。時間の設定は予備加熱の場合と同様
であるが、数秒以上あれば良い０
加熱方法としては、熱風乾燥オープン、赤外線加熱、ペ
ーパー７エーズソルダリング、レーザ加熱、ホットプレ
ート、抵抗加熱など何でも良い。
リフロー後の形態は、はんだペーストの組成・充填量及
びリフロー温度などによって異なるが例えばはんだペー
ストを第２図（Ｂ）のように充填した場合は同図（Ｃ）
、第３図（Ｂ）・の）、ま友第４図のように塗布した場
合は第３図（４）のようになる。
なお、第３図り）のように積層体の表側にはんだが出つ
ばりとして残り表面に絶縁層を形成してもスルーホール
部の絶縁が取れない場合には、前述リフロー工程直後の
はんだ凝固が始まらないうちに積層体を板状体で押しあ
てるか、または積層体を板状体で押し当てた状態でリフ
ローさせてはんだを凝固させ、積層体表側のはんだ出っ
ばりを抑えることも好ましい。
リフロー後、はんだおよび基板の表面にフラックス残留
物が生成されるが、必要に応じて洗浄を行う。洗浄剤と
して、トリクロロトリフルオロエタンに代表されるフロ
ン系溶剤や１−１−４−トリクロルエタンなどの塩素系
溶剤を用いてシャワー洗浄・超音波洗浄などを行えば良
い。
なお、工程（１）の前に、例えばソルダーレジストのよ
うにはんだ耐熱全もち、かつはんだとの濡れ性が悪い材
料を導電層表面のスルーホール用穴周辺部に塗布あるい
は貼付することにより、す７０−後のはんだを導電層表
面に流れ出さないようにすることは好ましいことである
。これにより、スルーホール部ランドに回路パターンが
接近している場合にはランドと回路パターンとのブリッ
ジ発生が抑えられ、ま念導通不良の発生が抑えられる。
次に本発明のスルーホール回路基板の具体例を示すが、
本発明はかかる実施例にのみ限定されるものではない。
実施例１
既知の方法により絶縁層を挾んでその両面にそれぞれ導
電層が積層された積層体企作製した。絶縁層の厚みは５
０μｍ１導電層の厚みは片面当り１４０μｍ であった
。次にスルーホール形成部にドリルで第２図（Ａ）のよ
うな０．４５．φの穴テあけた後、メタルマスク（０，
１４藺ｔ ）を用いたスクリーン印刷法にてはんだ粒が
Ｓｎ／Ｐｂ ＝ ３０ ／ ７０合金（固相線１８３℃
、液相線２５８℃）のけんだペースト（日本スベリア製
、Ｓｎ ３０ ＲＭＡＡＭ ） ’ｆ−第２図（Ｂ）の
ように穴に埋め込んだ。
その後、１３０℃の熱風オープン中で２０分間予備加熱
した少、ｚｚｏ℃の熱風オープン中で５分間リフローさ
せ、表面のフラックス残留分とトリクロロトリフルオロ
エタンで超音波洗浄し除去した。
形成されたスルーホール部の断面を観察したところ、第
５図のようなはんだの分１：、’＋Ｌは起こらずテスト
した１０００穴は全て第２図（Ｂ）のようにリフローし
たはんだがスルーホール用穴の内部にまで充填されてお
り、導通がとれていた。なお−穴当りのスルーホール抵
抗は１ｍΩ以下であった。またヒート・サイクルテスト
として８０℃×３０分間軽−３０℃×３０分間を２００
サイクル繰り返しても抵抗値に±１％以上の変動はみら
れなかった。
実施例２
実施例１と同様にして得られた導電層１４０μｍ１絶縁
層５０μｍの積層体の片面にポリエチレン製フィルム（
厚み６０μｍ）を貼付後ドリルで０゜４５Ｕφの穴をあ
けた。
次に前記フィルム貼付側からスキージを押しあてながら
穴に直接、はんだ粒がＳｎ／Ｐｂ／Ｂｉ ＝ ４３／４
３／１４合金（固相線１３５℃、液相線１６７℃）のは
んだペースト（千住金属製、５ＰＴ−５５−１６ｓ ）
をすりきりに埋め込んだ。
次に前記ポリエチレンフィルム？ａ械的に剥離しｆｃｏ
後、１００℃の熱風オープン中で２０分間予備加熱した
後、２００℃の熱風オーブン中で５分間リフローさせ、
表面のフラックス残留分全トリクロロトリフルオロエタ
ンで超音波洗浄して除去し友。
形成されたスルーホール部の断面を観察したところ、テ
ストした１０００穴は全て第３図（Ｂ）のようにリフロ
ーし之はんだがスルーホール用穴の３分の２程度（体積
比）充填されており、導通がとれてい友。またスルーホ
ールの抵抗は低く、−穴当りのスルー・ホール抵抗は１
ｍΩ以下であった。まｔヒート・サイクルテストどして
８０℃Ｘ３０分間神−３０℃×３０分間を２００サイク
ル繰り返しても抵抗値に±１％以上の変動は見られなか
った。
実施例３
実施例１と同様にして得られた絶縁層５０μｍ１導電層
１４０μｍの積層体にドリルで０．４５ ｙφの穴をあ
け次。
次に基板の裏側からスルーホール部を吸引しなカラメツ
シュスクリーン（ｔ６ｓＭ）ｅ用いて、実施例２で使用
したはんだペーストを第４図のように埋め込んだ。
その後、１００℃の熱風オーブン中で２０分間予備加熱
した後、１５０℃の熱風オーブン中で５分間リフローさ
せ、表面のフラックス残留分ヲトリクロロトリフルオロ
エタンで超音波洗浄して除去した。
形成されたスルーホール部の断面を観察１．たところ、
テストした１０００穴は全て第３図（Ａ）のようにリフ
ローしたはんだがスルーホール内壁に沿って充填されて
おり、導通がとれていた。、またスルーホールの抵抗は
低く、−穴当りのスルーホール抵抗は１７ｒＬΩ以下で
あった。またと−ト・サイクルテストとして８０℃Ｘ３
０分間−−３０℃Ｘ３０分間を２００サイクル繰り返し
ても抵抗値に±１係以上の変動は見られなかった。
実施例４
実施例１と同様にして得られた絶縁層５０μｍ１導電層
５０μｍ（１）積層体の両面にソルダーレジスト（タム
ラ製作所製ＵＳＲ−１１Ｇ ）を塗布・硬化させ、さら
に片面のみに厚さ６０μｍのポリエチレンフィルム貼付
しドリルで０．４５ ｗφの穴をあけた。
次に前記フィルム貼付側からスキージを押しあてながら
穴に直接、はんだ粒がＳｎ／Ｐｂ ＝ ４０／ ６０合
金（固相線１８３℃、液相線２３８℃）のはんだペース
ト（千住金属製、５ＰＴ−５５−４０）’ｉすりきりに
埋め込んだ。
次に前記ポリエチレンフィルムを機械的に剥離し次後、
１３０℃の熱風オーブン中で２０分間予備加熱した。そ
の後、板状体としてＰＴＦＥシート（１ｗｔ）に挾み、
２５０℃の加熱状態にある熱プレスに入れ、ＩＫｇｌ−
の加圧加熱を５分間行い、次いで加圧状態のままヒータ
ーの電源を切り、自然冷却し几。その後、表面のフラッ
クス残留分をトリクロロトリフルオロエタンで超音波洗
浄して除去した。
成形されたスルーホール部の断面を観察したところテス
トした１０００穴は全て、第３図（Ｂ）のようにリフロ
ーしたはんだがスルーホール用穴の３分の２程度（体積
比）充填されており、導通がとれてい比。スルーホール
部の積層体表面よシの高さを１００個測定したところ、
すべて５μｍ以下であった０ま次スルーホールの抵抗は
低く、−大当たりのスルーホール抵抗は１ｍΩ以下であ
った。
またヒート・サイクルテストとして８０’ＣＸ３０分間
軸−３０℃Ｘ３０分間を２００サイクル繰り返しても抵
抗値に±１％以上の変動は見られなかった０
また、作製したスルーホール回路基板の表面に更に、ス
クリーン印刷法によシ前記ソルダーレジストヲ塗布し、
紫外線を照射し硬化させたところ、スルーホール上の絶
Ｒ層の表面絶縁抵抗は、５０ｍΩ （２５０Ｖ）以上で
あった。
〔発明の効果〕
本発明によれば、導電性接着剤と比べ導電層との接合強
度で１０倍、比抵抗で１０分の１の値をもち、接合剤自
体が導電性であり、またコストが約１０分の１という特
徴を兼ね備えているはんだを用いているので、低コスト
で高信頼性、かつ生産性の高いスルーホール回路基板が
得られる。[It needs to be below the temperature, but it can be determined in conjunction with the allowable temperature limit of the board. For example, if the solder material is a Sn-/Ph=6 alloy alloy, the temperature is 130℃ ~ ]60
I like the vagina around ℃. This 1. If the temperature is too high, the flux will harden, resulting in poor solderability, and if it is too low, the volatile components of the flux will not be sufficiently dissipated, causing gas to remain, causing solder particles to be entrained. The heating time also varies depending on the heat capacity of the board, the amount of solder paste, the amount and type of flux, the heating method, etc., but is preferably about 1 to 3 minutes after the surface of the board reaches a specified temperature. The minimum required temperature is the solidus temperature of the solder grains used. The reflow temperature can be determined according to the heat resistance of the board and the reliability of through-hole connections, but depending on the composition of the solder, if the set temperature is too low, the proportion of molten solder may be too small and coalescence between solder particles may not occur. be. It is preferable to perform reflow at a temperature such that the proportion of this molten solder becomes 10% or more, and even 20% or more, of the total original solder grains in terms of volume ratio. In addition, as long as solder grains with the above-mentioned alloy composition are used, through-hole conduction occurs when the solder grains, which are partially melted during the reflow process, coalesce with the remaining solid solder grains, resulting in a solder bridge between the upper and lower conductive layers on the eaves. Even if the solder is then completely melted, or even if it is cooled and solidified afterwards, the through-hole continuity is maintained. In other words, as long as the through-hole conduction satisfies the above-mentioned solder flow temperature conditions, the alloy composition of the solder grains used, the conductive layer and
Since it is uniquely determined by the thickness of the insulating layer, etc., reflow may be performed at any temperature between the solidus line and the liquidus line of the solder grains used or above the liquidus line. The upper limit temperature is determined mainly by the heat resistance of the substrate, but care must be taken because if it is too high, the flux will carbonize and lose its activation effect. The time setting is the same as in the case of preheating, but a few seconds or more is sufficient. Any heating method may be used, including hot air dry open, infrared heating, paper 7Aze soldering, laser heating, hot plate, and resistance heating. The shape after reflow varies depending on the composition, filling amount, and reflow temperature of the solder paste, but for example, if the solder paste is filled as shown in Figure 2 (B), the shape will be as shown in Figure 2 (C)
, Fig. 3 (B)), and when applied as shown in Fig. 4, the result will be as shown in Fig. 3 (4). In addition, if solder sticks out on the front side of the laminate and insulation cannot be removed from the through-hole area even if an insulating layer is formed on the surface, as shown in Figure 3), the solder solidification immediately after the reflow process described above may occur. It is also preferable to press the laminate with a plate before it starts, or to solidify the solder by reflowing the laminate with the plate pressed against it, to suppress the protrusion of solder on the front side of the laminate. After reflow, flux residue is generated on the solder and substrate surfaces, which can be cleaned if necessary. Shower cleaning, ultrasonic cleaning, etc. may be performed using a chlorofluorocarbon solvent such as trichlorotrifluoroethane or a chlorine solvent such as 1-1-4-trichloroethane as a cleaning agent. In addition, before step (1), for example, by applying or pasting a material such as solder resist that is completely resistant to solder heat and has poor wettability with solder to the area around the through-hole hole on the surface of the conductive layer. It is preferable to prevent the solder after 70° from flowing out onto the surface of the conductive layer. As a result, when the circuit pattern is close to the through-hole land, the occurrence of bridging between the land and the circuit pattern is suppressed, and the occurrence of poor conduction is suppressed. Next, specific examples of the through-hole circuit board of the present invention will be shown.
The present invention is not limited only to such embodiments. Example 1 A laminate was prepared by a known method in which conductive layers were laminated on both sides of an insulating layer sandwiched between them. The thickness of the insulation layer is 5
The thickness of the 0 μm 1 conductive layer was 140 μm per side. Next, drill the through-hole forming part with a 0.45 mm diameter as shown in Figure 2 (A). After drilling a hole of φ, use a metal mask (0,
Solder grains were formed using a screen printing method using Sn/Pb = 30/70 alloy (solidus line: 183°C).
, liquidus line: 258° C.) (manufactured by Nippon Suberia, Sn 30 RMAAM) was embedded in the hole as shown in FIG. 2 (B). Thereafter, it was preheated for 20 minutes in an open hot air oven at 130°C, and then reflowed for 5 minutes in an open hot air oven at zzo°C, and the residual flux on the surface was removed by ultrasonic cleaning with trichlorotrifluoroethane. When we observed the cross section of the formed through-hole section, we found that the reflowed solder did not pass through the 1,000 holes tested, as shown in Figure 2 (B). It was filled to the inside of the hole, and continuity was established. Note that the through-hole resistance per hole was 1 mΩ or less. In addition, as a heat cycle test, 80℃ x 30 minutes and -30℃ x 30 minutes were heated for 200 minutes.
No fluctuation of more than ±1% in resistance value was observed even after repeated cycles. Example 2 A polyethylene film (
After pasting the film (60 μm thick), a hole of 0°45Uφ was drilled using a drill. Next, while pressing a squeegee from the film pasting side, solder grains are directly inserted into the holes at Sn/Pb/Bi = 43/4.
3/14 alloy (solidus 135℃, liquidus 167℃) solder paste (Senju Metal, 5PT-55-16s)
I embedded it into the slot. Next is the polyethylene film? a Mechanically peel off fco
After that, it was preheated for 20 minutes in a 100°C hot air oven, and then reflowed for 5 minutes in a 200°C hot air oven.
Remove any flux residue on the surface by ultrasonic cleaning with trichlorotrifluoroethane. When we observed the cross section of the formed through-hole section, all of the 1000 holes tested were filled with about two-thirds (volume ratio) of the reflowed solder as shown in Figure 3 (B). There, there is continuity. Also, the resistance of through holes is low, -through hole resistance per hole is 1
It was less than mΩ. Also, in a heat cycle test, even after repeating 200 cycles of 80°C x 30 minutes and -30°C x 30 minutes, no fluctuation of more than ±1% in the resistance value was observed. Example 3 A hole of 0.45 yφ was drilled in a laminate having an insulating layer of 50 μm and a conductive layer of 140 μm obtained in the same manner as in Example 1. Next, the solder paste used in Example 2 was embedded in the through-holes from the back side of the board using a suction screen (t6sM) as shown in FIG. After that, it was preheated for 20 minutes in a hot air oven at 100°C, and then reflowed for 5 minutes in a hot air oven at 150°C, and the residual flux on the surface was removed by ultrasonic cleaning with trichlorotrifluoroethane. Observing the cross section of the formed through hole part1. However,
All of the 1000 holes tested were filled with reflowed solder along the inner walls of the through holes, as shown in FIG. 3(A), and were electrically conductive. In addition, the resistance of the through holes was low, and the through hole resistance per hole was 17 rLΩ or less. In addition, as a toto cycle test, 80℃
Even after repeating 200 cycles of 0 minute to -30°C for 30 minutes, no fluctuation of more than ±1 factor was observed in the resistance value. Example 4 A 50 μm insulating layer and 50 μm conductive layer obtained in the same manner as in Example 1 (1) A solder resist (USR-11G manufactured by Tamura Seisakusho) was applied and cured on both sides of the laminate, and a 60 μm thick layer was applied on only one side. A hole of 0.45 wφ was made using a drill to attach a polyethylene film. Next, while pressing a squeegee from the film pasting side, apply solder paste (Senju Metal Co., Ltd., 5PT-) whose solder grains are Sn/Pb = 40/60 alloy (solidus 183°C, liquidus 238°C) to the hole. 55-40)'i It was embedded in the slot. Next, after mechanically peeling off the polyethylene film,
It was preheated for 20 minutes in a hot air oven at 130°C. After that, it was sandwiched between PTFE sheets (1wt) as a plate-shaped body,
Place it in a heat press heated to 250°C, and
Heat under pressure for 5 minutes, then turn off the heater while keeping it under pressure and let it cool naturally. Thereafter, residual flux on the surface was removed by ultrasonic cleaning with trichlorotrifluoroethane. When we observed the cross section of the formed through-hole part, all of the 1,000 holes tested were filled with about two-thirds (volume ratio) of the reflowed solder, as shown in Figure 3 (B). , non-conducting ratio. When we measured the height of the laminate surface of 100 through holes,
The resistance of the zero-order through holes, which were all 5 μm or less, was low, and the jackpot through hole resistance was 1 mΩ or less. In addition, even after repeating 200 cycles of -30°C x 30 minutes at 80'C for 30 minutes as a heat cycle test, no fluctuation of more than ±1% in the resistance value was observed. Applying the solder resist by screen printing method,
When cured by irradiation with ultraviolet rays, the surface insulation resistance of the absolute R layer on the through hole was 50 mΩ (250 V) or more. [Effects of the Invention] According to the present invention, the bonding strength with the conductive layer is 10 times that of a conductive adhesive, and the specific resistance is 1/10, the adhesive itself is conductive, and the cost is low. Since the solder is used, which has the characteristics of approximately 1/10 of the solder, it is possible to obtain a through-hole circuit board that is low cost, highly reliable, and highly productive.
第１図は本発明のスルーホール回路基板の実１１例を示
す断面図。
第２図囚からＣ）は本発明のスルーホール回路基板の製
造工程の実施例を説明する断面図。
第３図（４）からの）及び第４図は本発明の他のスルー
ホール回路基板の実施例を説明する断面図。
第５図は従来のはんだペースト（共晶）を用いたスルー
ホール回路基板の断面図である。
ｌ・・・ｉ屠体、２−・絶縁層、３，３Ｃ・・導電Ｊ帝
、４．４’−・・はんだ、５・・・穴、６・・・フラッ
クス、７−・・はんだ、８・・・ガスによって形成され
た空間特許出願人 旭化成工業株式会社内
第１図 第３図
第４図 第５図
手続補正書
昭和６３年２月１６日
特許庁長官 小 川 邦 夫 殿
１、事件の表示
昭和６２年特許願第２９６１２０号
２、発明の名称
スルーホール回路基板およびその製造方法３、補正をす
る者
事件との関係 特許出願人
大阪府大阪市北区堂島浜１丁目２番６号（００３）７１
！！、イＬ成１業株式会社 、、′ｉデ１１．；′、、
’）代表取締役社長 世 古 真 臣゛−５５、補正の
内容
（１１明細書の特許請求の範囲を別紙の通り補正する。
（２）明細書の発明の詳細な説明の欄を下記の通り補正
する。
特許請求の範囲
（１１絶縁層を挟んでその両面にそれぞれ導電層が積層
された部分を有する積層体を用いたスルーホール回路基
板において、前記絶縁層の両面に積層された導電層が、
固相線と液相線とが異なるはんだにより接続されている
ことを特徴とするスルーホール回路基板
（２）前記はんだの固相線温度における固体成分の割合
が体積比ではんだ全体の０．５％以上である特許請求の
範囲第１項に記載のスルーホール回路基板（３）絶縁層
を挟んでその両面にそれぞれ導電層が積層された部分を
有する積層体を用いたスルーホール回路基板の製造方法
において、少なくともｉ）前記積層体にスルーホール用
の穴をあける工程と、
ｉｉ ）前記穴に、固相線と液相線が異なるはんだ粒と
フラックスとから成るはんだペーストを充填する工程と
、
ｉｉｉ ）前記はんだペーストを前記はんだ粒の固相線
温度以上に加熱して、前記はんだ粒の少なくとも一部分
をリフローさせる工程、
とを含むことを特徴とするスルーホール回路基板の製造
方法
（４）前記はんだ粒の固相線温度における固体成分の割
合が体積比ではんだ粒全体の０．５％以上である特許請
求の範囲第３項に記載のスルーホール回路基板の製造方
法
（５）溶融はんだの割合が体積比ではんだ粒合計の１０
％以上となる温度でリフローさせゑ特許請求の範囲第３
項または第４項に記載のスルーホール回路基板の製造方
法FIG. 1 is a sectional view showing 11 examples of the through-hole circuit board of the present invention. FIGS. 2A to 2C are cross-sectional views illustrating an embodiment of the manufacturing process of the through-hole circuit board of the present invention. FIG. 3(4) to FIG. 4 are cross-sectional views illustrating other embodiments of the through-hole circuit board of the present invention. FIG. 5 is a cross-sectional view of a through-hole circuit board using a conventional solder paste (eutectic). l...i carcass, 2--insulating layer, 3,3C...conductive layer, 4.4'-...solder, 5...hole, 6...flux, 7-...solder, 8... Space formed by gas Patent applicant Asahi Kasei Industries, Ltd. Figure 1 Figure 3 Figure 4 Figure 5 Procedural amendment February 16, 1988 Director General of the Patent Office Kunio Ogawa 1, Display of the case 1986 Patent Application No. 296120 2 Name of the invention Through-hole circuit board and its manufacturing method 3 Person making the amendment Relationship to the case Patent applicant 1-2-6 Dojimahama, Kita-ku, Osaka-shi, Osaka Prefecture (003)71
! ! , ILSeiichigyo Co., Ltd. ,'iDe11. ；′、、
') Representative Director and President Makoto Seko 55, Contents of the amendment (The scope of claims in the 11th specification will be amended as shown in the attached sheet. (2) The detailed description of the invention column in the specification will be amended as follows. Claims (11) A through-hole circuit board using a laminate having conductive layers laminated on both sides of an insulating layer, the conductive layers laminated on both sides of the insulating layer comprising:
A through-hole circuit board characterized in that a solidus line and a liquidus line are connected by different solders. % or more of the through-hole circuit board according to claim 1 (3) Manufacture of a through-hole circuit board using a laminate having a portion in which conductive layers are laminated on both sides with an insulating layer sandwiched therebetween. The method includes at least the steps of: i) drilling holes for through holes in the laminate; ii) filling the holes with solder paste consisting of solder particles and flux having different solidus and liquidus lines; (4) A method for manufacturing a through-hole circuit board, characterized in that it includes the step of: (iii) heating the solder paste to a temperature higher than the solidus temperature of the solder particles to reflow at least a portion of the solder particles. (5) The method for manufacturing a through-hole circuit board according to claim 3, wherein the proportion of solid components at the solidus temperature of the solder grains is 0.5% or more of the total solder grains in terms of volume ratio. The ratio is 10 of the total solder grains by volume.
% or more.Claim 3
4. Method for manufacturing a through-hole circuit board according to item 4 or 4.
Claims (5)
された部分を有する積層体を用いたスルーホール回路基
板において、前記絶縁層の両面に積層された導電層が、
固相線と液相線とが異なるはんだにより接続されている
ことを特徴とするスルーホール回路基板(1) In a through-hole circuit board using a laminate having portions sandwiching an insulating layer and having conductive layers laminated on both sides thereof, the conductive layers laminated on both sides of the insulating layer,
A through-hole circuit board characterized in that a solidus line and a liquidus line are connected by different solders.
が体積比ではんだ全体の０．５％以上である特許請求の
範囲第１項に記載のスルーホール回路基板(2) The through-hole circuit board according to claim 1, wherein the proportion of the solid component at the solidus temperature of the solder is 0.5% or more of the entire solder in terms of volume ratio.
された部分を有する積層体を用いたスルーホール回路基
板の製造方法において、少なくとも ｉ）前記積層体にスルーホール用の穴をあける工程と、 ｉｉ）前記穴に、固相線と液相線が異なるはんだ粒とフ
ラックスとから成るはんだペーストを充填する工程と、 ｉｉｉ）前記はんだペーストを前記はんだ粒の固相線温
度以上に加熱して、前記はんだ粒の少なくとも一部分を
リフローさせる工程 とを含むことを特徴とするスルーホール回路基板の製造
方法(3) A method for manufacturing a through-hole circuit board using a laminate having conductive layers laminated on both sides of an insulating layer sandwiching the insulating layer, at least i) drilling holes for through holes in the laminate; ii) filling the hole with a solder paste consisting of solder grains and flux having different solidus and liquidus lines, and iii) heating the solder paste to a temperature higher than the solidus temperature of the solder grains. and reflowing at least a portion of the solder grains.
合が体積比ではんだ粒全体の０．５％以上である特許請
求の範囲第３項に記載のスルーホール回路基板の製造方
法(4) The method for manufacturing a through-hole circuit board according to claim 3, wherein the proportion of solid components at the solidus temperature of the solder grains is 0.5% or more of the entire solder grains in terms of volume ratio.
％以上となる温度でリフローさせ特許請求の範囲第３項
または第４項に記載のスルーホール回路基板の製造方法(5) The proportion of molten solder is 10% of the total solder grains by volume.
The method for manufacturing a through-hole circuit board according to claim 3 or 4 by reflowing at a temperature of % or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62296120A JPH01138788A (en) | 1987-11-26 | 1987-11-26 | Through-hole circuit substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62296120A JPH01138788A (en) | 1987-11-26 | 1987-11-26 | Through-hole circuit substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01138788A true JPH01138788A (en) | 1989-05-31 |
Family
ID=17829396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62296120A Expired - Lifetime JPH01138788A (en) | 1987-11-26 | 1987-11-26 | Through-hole circuit substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01138788A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0348486A (en) * | 1989-07-15 | 1991-03-01 | Sony Corp | Printed circuit board |
| WO2016175206A1 (en) * | 2015-04-27 | 2016-11-03 | 京セラ株式会社 | Circuit substrate and electronic device provided with same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419172A (en) * | 1977-07-14 | 1979-02-13 | Shindo Denshi Kougiyou Kk | Method of making flexible throughhhole print wire substrate |
| JPS5513436A (en) * | 1978-07-12 | 1980-01-30 | Nec Corp | Misreading detector circuit |
| JPS61263194A (en) * | 1985-05-16 | 1986-11-21 | 熊谷 彰治郎 | Surface-back conduction for double-side printed wiring board |
| JPS6214960A (en) * | 1985-07-15 | 1987-01-23 | Kubota Ltd | Fountain apparatus |
-
1987
- 1987-11-26 JP JP62296120A patent/JPH01138788A/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419172A (en) * | 1977-07-14 | 1979-02-13 | Shindo Denshi Kougiyou Kk | Method of making flexible throughhhole print wire substrate |
| JPS5513436A (en) * | 1978-07-12 | 1980-01-30 | Nec Corp | Misreading detector circuit |
| JPS61263194A (en) * | 1985-05-16 | 1986-11-21 | 熊谷 彰治郎 | Surface-back conduction for double-side printed wiring board |
| JPS6214960A (en) * | 1985-07-15 | 1987-01-23 | Kubota Ltd | Fountain apparatus |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0348486A (en) * | 1989-07-15 | 1991-03-01 | Sony Corp | Printed circuit board |
| WO2016175206A1 (en) * | 2015-04-27 | 2016-11-03 | 京セラ株式会社 | Circuit substrate and electronic device provided with same |
| JPWO2016175206A1 (en) * | 2015-04-27 | 2017-05-18 | 京セラ株式会社 | Circuit board and electronic device having the same |
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