JPH01115220A - Pll frequency adjusting circuit - Google Patents
Pll frequency adjusting circuitInfo
- Publication number
- JPH01115220A JPH01115220A JP62274043A JP27404387A JPH01115220A JP H01115220 A JPH01115220 A JP H01115220A JP 62274043 A JP62274043 A JP 62274043A JP 27404387 A JP27404387 A JP 27404387A JP H01115220 A JPH01115220 A JP H01115220A
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- frequency
- phase
- signal
- pll
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＰＬＬ回路のフリーラン周波数を調整するＰＬ
Ｌ周波数調整回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a PL that adjusts the free run frequency of a PLL circuit.
This invention relates to an L frequency adjustment circuit.
本発明はＰＬＬ回路のフリーラン周波数を調整するＰＬ
Ｌ周波数調整回路に関し、可変発振器の発振出力と入力
信号の位相とを比較する第１の位相比較器から成るＰＬ
Ｌ回路と、入力信号と同相のＰＬＬ回路からの出力信号
と基準となる入力信号とを比較する第２の位相比較器と
、第２の位ト目比較器の比較出力信号を検波する検波器
とを具備し、検波器の検出出力電圧が最小となる様に可
変発振器の周波数を調整する様にして簡単な測定器によ
って高精度にフリーラン周波数調整が出来る様にしたも
のである。The present invention provides a PL that adjusts the free run frequency of a PLL circuit.
Regarding the L frequency adjustment circuit, the PL consists of a first phase comparator that compares the oscillation output of the variable oscillator and the phase of the input signal.
L circuit, a second phase comparator that compares the output signal from the PLL circuit that is in phase with the input signal and a reference input signal, and a detector that detects the comparison output signal of the second digit comparator. The frequency of the variable oscillator is adjusted so that the detection output voltage of the wave detector is minimized, thereby making it possible to adjust the free-run frequency with high precision using a simple measuring device.
従来のＰ Ｌ Ｌ（Ｐｈａｓｅ １ｏｃｋｅｄ １ｏｏ
ｐ ：位相同期ループ）回路はＦＭ或いはＡＭ受信機の
復調器等に多く利用されている。例えば、特公昭６０−
４９３８７号公報にはＡＭステレオ受信機のＰＬＬ回路
が示されている。この様なＰＬＬ回路のフリーラン周波
数を調整するＰＬＬ周波数調整回路は第５図の如く構成
されていた。第５図で入力端子Ｔ１ に供給した基準入
力信号は位相比較器（１〕に供給され、位相比較器（１
）の出力はループフィルタの低域通過濾波器（ＬＰＦ）
（２）を介して可変発振器を構成する電圧制御発振器（
ＶＣＯ）（３）に供給される。更に、ＶＣＯ（３）の入
力端子Ｔ２ には、フリーラン調整用信号が供給される
。Ｖ ＣＯ（３）の出力は出力端子Ｔ３ に出力される
と共に分周器又は移送器（４）を介して位相比較器（１
）にフィードバックされ、位相比較器（１）では基準入
力信号に比例した信号を出力してＰＬＬ回路を構成して
いる。Conventional PLL (Phase 1ocked 1oo)
p: phase-locked loop) circuits are often used in demodulators of FM or AM receivers. For example, special public service in 1986-
No. 49387 discloses a PLL circuit for an AM stereo receiver. A PLL frequency adjustment circuit for adjusting the free run frequency of such a PLL circuit was constructed as shown in FIG. In FIG. 5, the reference input signal supplied to the input terminal T1 is supplied to the phase comparator (1).
) output is a loop filter low pass filter (LPF)
(2) A voltage controlled oscillator (
VCO) (3). Furthermore, a free run adjustment signal is supplied to the input terminal T2 of the VCO (3). The output of the V CO (3) is output to the output terminal T3 and is also sent to the phase comparator (1) via a frequency divider or shifter (4).
), and the phase comparator (1) outputs a signal proportional to the reference input signal to form a PLL circuit.
上述の構成で、ＰＬＬ回路のフリーラン周波数を調整す
るには従来２通りの方法が用いられていた。Conventionally, two methods have been used to adjust the free run frequency of the PLL circuit in the above configuration.
第１の調整方法は入力端子Ｔ１ に入力信号を供給しな
い無人力状態で、ＶＣＯ（３）の出力端子Ｔ３に周波数
カウンタ（５）を接続して、周波数を直読するものであ
り、第２の調整方法は入力端子Ｔ、に基準入力信号（正
規の周波数のパイロット信号）を入力し、位相比較器（
１）の比較出力をＬ Ｐ Ｆ （２）に通した後に直流
電圧計（６）又はコンパレータ等で電圧測定を行うもの
である。The first adjustment method is to directly read the frequency by connecting a frequency counter (5) to the output terminal T3 of the VCO (3) in an unmanned state without supplying an input signal to the input terminal T1. The adjustment method is to input the reference input signal (pilot signal of regular frequency) to the input terminal T, and use the phase comparator (
After passing the comparative output of 1) through LPF (2), the voltage is measured using a DC voltmeter (6) or a comparator.
上述の第１のＰＬＬ周波数調整回路の調整方法では周波
数カウンタを用いることでＰＬＬのフリーラン周波数を
精度よく調整する事が出来るが、ＰＬＬ回路を構成する
基板内に周波数測定可能な周波数カウンタを設は様とす
ると、回路が膨大になり、高価となる問題があった。又
、第２０ＰＬＬ周波数調整回路の調整方法によれば直流
電圧計又はコンパレークを配設すればよいので測定手段
は廉価に構成出来る。然し、位相比較器（１）やＬＰＦ
（２）に直流オフセット（ＤＣｏｆｆｓｅｔ）があると
、調整精度が高くとれない問題があった。In the first adjustment method for the PLL frequency adjustment circuit described above, the free run frequency of the PLL can be adjusted accurately by using a frequency counter. However, there was a problem in that the circuit would be huge and expensive. Further, according to the adjustment method of the 20th PLL frequency adjustment circuit, a DC voltmeter or a comparator may be provided, so that the measuring means can be constructed at low cost. However, the phase comparator (1) and LPF
If there is a DC offset (DCoffset) in (2), there is a problem that high adjustment accuracy cannot be obtained.
本発明は叙上の欠点に鑑み成されたもので、その目的と
するところは高価な周波数カウンタを用いずに精度よ＜
ＰＬＬ回路のフリーラン周波数を調整し得るＰＬＬ周波
数調整回路を提供せんとするものである。The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to improve accuracy without using expensive frequency counters.
It is an object of the present invention to provide a PLL frequency adjustment circuit that can adjust the free run frequency of a PLL circuit.
本発明のＰＬＬ周波数調整回路はその一例を第１図に示
す様に可変発振器（５）の発振出力と入力信号ＳＲの位
相とを比較する第１の位相比較器（１）から成るＰＬＬ
回路（ｌＯ）と、入力信号Ｓ８ と同相のＰＬＬ回路
（１０）からの出力信号Ｓ、と、基準となる入力信号Ｓ
、とを比較する第２の位相比較器（７）と、第２の位相
比較器（７）の比較出力信号を検波する検波器（９）と
を具備し、検波器（９）の検出出力電圧が最小となる様
に可変発振器（３）の周波数を調整して成るものである
。An example of the PLL frequency adjustment circuit of the present invention is a PLL circuit comprising a first phase comparator (1) that compares the oscillation output of a variable oscillator (5) with the phase of an input signal SR, as shown in FIG.
circuit (lO), an output signal S from the PLL circuit (10) that is in phase with the input signal S8, and a reference input signal S.
, and a detector (9) that detects the comparison output signal of the second phase comparator (7), the detection output of the detector (9) The frequency of the variable oscillator (3) is adjusted so that the voltage is minimized.
本発明のＰＬＬ周波数調整回路は第２の位相比較器（７
）で比較（乗算）された基準の入力信号Ｓ。The PLL frequency adjustment circuit of the present invention includes a second phase comparator (7
) is compared (multiplied) by the reference input signal S.
と入力信号と同位相のＰＬＬ出力信号Ｓ、をピーク検波
すると、この検波出力はＶＣＯ（５）のフＩＪ −ラン
周波数に対し、正弦波曲線で変化するのでピーク検波出
力が最も小さな値を求めれば精度よくフリーラン周波数
の調整を行うことが可能となる。When PLL output signal S, which is in phase with the input signal, is peak-detected, this detection output changes in a sinusoidal curve with respect to the VCO (5)'s IJ-run frequency, so find the smallest value for the peak detection output. This makes it possible to adjust the free-run frequency with high precision.
以下、本発明のＰＬＬ周波数調整回路の一実施例を第１
図乃至第３図について説明する。Hereinafter, one embodiment of the PLL frequency adjustment circuit of the present invention will be described as a first embodiment.
A description will be given of FIGS. 3 to 3.
第１図の系統図に於いて第５図と対応する部分には同一
符号を付して重複説明を省略する。In the system diagram of FIG. 1, parts corresponding to those in FIG. 5 are given the same reference numerals and redundant explanation will be omitted.
第１図で破線によりＰＬＬ回路（１０）として示されて
いる部分は第５図の構成と全く同じであるが分周器又は
移相器（４）の出力は基準入力信号Ｓ、と位相差が９０
°異なる出力信号Ｓ。と、基準入力信号ＳＲと位相が同
相の出力信号Ｓ、が取り出される様にしたもので入力端
子Ｔ１ に加わる基準入力信号ＳＲは第１及び第２の位
相比較器（１）、 （７）に供給され、分周器又は移
相器（４）からの基準入力信号Ｓ、と９０°位相の異な
る出力信号Ｓ、は第１の位相比較器（１）にフィードバ
ックされ、基準入力信号Ｓ、と同相の出力信号Ｓ、は第
２の位相比較器（７）に供給される。第２の位相比較器
（７）はマルチプライヤ等で構成され、例えば、第２図
Ａ図示の基準入力信号Ｓ８ と、第２図、Ｂ、Ｄ、Ｆ等
に示す基準入力信号と同相の出力信号Ｓ、が乗算される
。The part indicated by a broken line as the PLL circuit (10) in FIG. 1 has exactly the same configuration as the one in FIG. 5, but the output of the frequency divider or phase shifter (4) has a phase difference with the reference input signal S. is 90
° Different output signals S. The output signal S having the same phase as the reference input signal SR is extracted, and the reference input signal SR applied to the input terminal T1 is sent to the first and second phase comparators (1) and (7). The reference input signal S from the frequency divider or phase shifter (4) and the output signal S having a phase difference of 90° are fed back to the first phase comparator (1), and the reference input signal S, The in-phase output signal S, is fed to a second phase comparator (7). The second phase comparator (7) is composed of a multiplier, etc., and outputs, for example, the reference input signal S8 shown in FIG. 2A, and the reference input signals shown in FIG. 2, B, D, F, etc. The signal S, is multiplied.
第２図Ｂはフリーラン調整信号の周波数が低い場合を、
第２図りはフリーラン調整信号の周波数が基準入力信号
Ｓ８ と一致している場合、第２図Ｆはフリーラン調整
信号の周波数が高い場合の波形を夫々示している。第２
の位相比較器（７）で掛算された基準入力信号ＳＢ
と、分周器又は移相器（４）の出力信号ＳＳ は必要に
応じ設けた反転器（８）で反転され第２図Ｃ，Ｅ、Ｇに
示す如き波形の比較出力信号Ｓ。とじて出力される。第
２図Ｃ，Ｅ、Ｇの比較出力信号Ｓ。の波形はフリーラン
周波数が低い場合、基準信号とフリーラン周波数が一致
している場合、フリーラン周波数が高い場合を示してい
る。第２図りでは基準入力信号Ｓ＋ｌ と分周器又は移
相器（４）の出力信号Ｓ、の位相が一致しているために
反転器（８）の出力信号波形は基準入力信号波形を全波
整流した波形となる。又、第２図Ｂ、 Ｆの場合は基
準入力信号ＳＢ と分周器又は吟相器（４）の出力信号
Ｓ、の位相がずれているので反転器（８）の出力信号波
形は全波整流した波形がくずれて基準の閾値ＳＬより上
に出る。（第２図Ｃ，ＧでＰＬで示す部分）この様な反
転器（８）の出力をピーク検波器（９）に供給し、第２
図Ｃ，Ｇで示すピーク値ＰＬを検波することにより、ピ
ーク検波器（９）の出力には第３図で示す出力電圧が得
られる。Figure 2B shows the case where the frequency of the free run adjustment signal is low.
Figure 2 shows the waveforms when the frequency of the free run adjustment signal matches the reference input signal S8, and Figure 2F shows the waveforms when the frequency of the free run adjustment signal is high. Second
The reference input signal SB multiplied by the phase comparator (7) of
The output signal SS of the frequency divider or phase shifter (4) is inverted by an inverter (8) provided as necessary to obtain a comparison output signal S with waveforms as shown in FIG. 2C, E, and G. The output is closed. Comparison output signal S of FIG. 2 C, E, and G. The waveforms indicate cases where the free run frequency is low, cases where the reference signal and the free run frequency match, and cases where the free run frequency is high. In the second diagram, since the phases of the reference input signal S+l and the output signal S of the frequency divider or phase shifter (4) match, the output signal waveform of the inverter (8) is the full waveform of the reference input signal waveform. It becomes a rectified waveform. In addition, in the cases of B and F in Fig. 2, the phase of the reference input signal SB and the output signal S of the frequency divider or phaser (4) is shifted, so the output signal waveform of the inverter (8) is a full wave. The rectified waveform is distorted and appears above the reference threshold value SL. (The part indicated by PL in Figure 2 C and G) The output of such an inverter (8) is supplied to the peak detector (9), and the second
By detecting the peak value PL shown in FIGS. C and G, the output voltage shown in FIG. 3 is obtained at the output of the peak detector (9).
第３図で縦軸はピーク検波器（９）の出力電圧レベルを
、横軸はフリーラン周波数を示している。ピーク検波器
（９）の直流出力電圧はフリーラン周波数が基準入力信
号と位相が一致した一致点（１１）で最小となり、フリ
ーラン周波数がＡ、Ｂの矢印で示す方向にずれるにした
がって正弦波曲線り１２）のｌ ｓｉｎ θ］で変化
する。（ここで−９０°〈θ＜９０゜二〇はＰＬＬの定
常位相誤差〉依って、ピーク検波出力の直流電圧が最小
になる様にＶＣＯ（３）のフリーラン周波数を調整すれ
ば精度の高い調整が可能となる。In FIG. 3, the vertical axis represents the output voltage level of the peak detector (9), and the horizontal axis represents the free run frequency. The DC output voltage of the peak detector (9) becomes the minimum at the matching point (11) where the free run frequency matches the reference input signal in phase, and as the free run frequency shifts in the directions indicated by arrows A and B, it becomes a sine wave. 1 sin θ] of the curve 12). (Here, -90°〈θ〈90゜20 is the steady phase error of PLL〉) Therefore, if the free run frequency of VCO (3) is adjusted so that the DC voltage of the peak detection output is minimized, high accuracy can be achieved. Adjustment is possible.
第４図はフリーラン周波数を変化させてピーク検波器（
９）の出力が最小となる点（１１）を直流電圧計（６）
で検出し、このポイントをフリーラン周波数が基準入力
信号Ｓ、と一致しているポイントとして調整したもので
、この場合は測定手段としては単に直流電圧計（６）が
あればフリーラン周波数調整が可能となる。Figure 4 shows the peak detector (
Point (11) where the output of 9) is minimum is measured using a DC voltmeter (6).
, and this point is adjusted as the point where the free run frequency matches the reference input signal S. In this case, the free run frequency can be adjusted simply by using a DC voltmeter (6) as a measuring means. becomes.
更に測定手段としてコンパレータ（１５）を用意しピー
ク検波器（９）の検波出力をコンパレータ（１５）に接
続し、Ｖ ＣＯ（３）に供給するフリーラン調整信号を
変化させる。コンパレータ（１５）の闇値を第４図ＳＬ
、 の様に選択し、コンパレータ（７）の出力が反転
する２点（１３）のフリーラン周波数を求め、この周波
数の真中のポイント（１１）を基準入力信号と一致した
ポイントとすればよい、この場合はコンパレータク１５
）をＰＬＬ周波数調整回路内（或いは基板）に組込むこ
とが極めて容易で、２点間の真中を演算する場合等はラ
ジオ受信機等の機器に含まれているマイクロコンピュー
タを用いて簡単に自動調整化し得る。Further, a comparator (15) is prepared as a measuring means, the detection output of the peak detector (9) is connected to the comparator (15), and the free run adjustment signal supplied to the VCO (3) is changed. The darkness value of the comparator (15) is shown in Figure 4 SL
, and find the free run frequency of the two points (13) where the output of the comparator (7) is inverted, and set the point (11) in the middle of these frequencies as the point that matches the reference input signal. In this case, comparator tak15
) is extremely easy to incorporate into the PLL frequency adjustment circuit (or board), and when calculating the center between two points, automatic adjustment can be easily performed using a microcomputer included in equipment such as a radio receiver. can be converted into
尚、本発明は上述の実施例に限定されることなく、発明
の要旨を逸脱しない範囲で種々の変形が可能であること
は勿論である。It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made without departing from the gist of the invention.
本発明は叙上の如く構成させたのでＰＬＬ回路に第２の
位相比較器とピーク検波器並びに必要に応じて測定手段
としてのコンパレータを組込むだけでＰＬＬ回路のフリ
ーラン周波数が高精度に調整可能となり、コンビエータ
による自動調整化も容易に成る等の多くの特長を有する
。Since the present invention is configured as described above, the free run frequency of the PLL circuit can be adjusted with high precision simply by incorporating the second phase comparator, peak detector, and, if necessary, a comparator as a measuring means into the PLL circuit. It has many features such as easy automatic adjustment using a combiator.
第１図は本発明のＰＬＬ周波数調整回路の一実施例を示
す系統図、第２図は本発明のＰＬＬ周波数調整回路の動
作説明波形図、第３図は本発明のＰＬＬ周波数調整回路
に用いられるピーク検波器の出力電圧変化図、第４図は
本発明のＰＬＬ周波数調整回路の周波数調整方法の説明
図、第５図は従来のＰＬＬ回路のフリーラン周波数調整
回路の系統図である。
（１）は第１の位相比較器、（２）はＬ Ｐ Ｆ 、
（３）は可変発振器（ＶＣＯ）、（４）は分周器又は移
相器、（５）は周波数カウンタ、（６）は直流電圧計、
（７）は第２の位相比較器、（８）は反転器、（９）は
ピーク検波器、（１０）はＰＬＬ回路、（１５）はコン
パレータである。
不梵明っＰＬＬ川液用功整１回Ｂ柄−’ｊ２Ｔｈ＋デ汐
Ｗ・亨ｔｉ先圀第１図
！”月ｑＦＬＬ湯汲枚調整−回路（動作１文明流臀ｍ／
２正弧うＬａ穐
嘱
本割を四つビーフや１友Ｗ煽ｔ、力ｖ凰尖ｊ（口笛３図
／Ｉ’ ７リーラ＞Ｍ汲（欠精り月
／ｌＰＬＬ粛１１攻」司寒蓬−回１ｈ戸Ｕ友恢調ち［５
ヲレ畝９η囮第４図
／
第５図FIG. 1 is a system diagram showing an embodiment of the PLL frequency adjustment circuit of the present invention, FIG. 2 is a waveform diagram explaining the operation of the PLL frequency adjustment circuit of the present invention, and FIG. 3 is a diagram showing the operation of the PLL frequency adjustment circuit of the present invention. FIG. 4 is an explanatory diagram of the frequency adjustment method of the PLL frequency adjustment circuit of the present invention, and FIG. 5 is a system diagram of the conventional free-run frequency adjustment circuit of the PLL circuit. (1) is the first phase comparator, (2) is L P F ,
(3) is a variable oscillator (VCO), (4) is a frequency divider or phase shifter, (5) is a frequency counter, (6) is a DC voltmeter,
(7) is a second phase comparator, (8) is an inverter, (9) is a peak detector, (10) is a PLL circuit, and (15) is a comparator. Fubon Ming PLL River liquid use 1st time B pattern-'j2Th+Deshio W・Hingti forward area 1st figure! "Month qFLL hot water pump adjustment - circuit (movement 1 civilized style buttocks m/
2 positive arcs La Aoki Honwari 4 beefs, 1 friend W fan t, power v 凰 thorn j (whistle 3 figure / I' 7 Leela > M 汲 (missing moon / l PLL 11 attack) Shikan Yogi-time 1h door U friendship tune [5
Figure 4/Figure 5
Claims (1)
１の位相比較器から成るＰＬＬ回路と、上記入力信号と
同相のＰＬＬ回路からの出力信号と基準となる入力信号
とを比較する第２の位相比較器と、 上記第２の位相比較器の比較出力信号を検波する検波器
とを具備し、 上記検波器の検出出力電圧が最小となる様に上記可変発
振器の周波数を調整してなることを特徴とするＰＬＬ周
波数調整回路。[Claims] A PLL circuit comprising a first phase comparator that compares the oscillation output of a variable oscillator with the phase of an input signal, an output signal from the PLL circuit having the same phase as the input signal, and an input signal serving as a reference. and a detector that detects the comparison output signal of the second phase comparator, and a detector that detects the comparison output signal of the second phase comparator, A PLL frequency adjustment circuit characterized by adjusting the frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62274043A JPH01115220A (en) | 1987-10-29 | 1987-10-29 | Pll frequency adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62274043A JPH01115220A (en) | 1987-10-29 | 1987-10-29 | Pll frequency adjusting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01115220A true JPH01115220A (en) | 1989-05-08 |
Family
ID=17536168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62274043A Pending JPH01115220A (en) | 1987-10-29 | 1987-10-29 | Pll frequency adjusting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115220A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6700629B1 (en) | 2000-07-06 | 2004-03-02 | Mitsubishi Denki Kabushiki Kaisha | Video intermediate frequency processing apparatus |
-
1987
- 1987-10-29 JP JP62274043A patent/JPH01115220A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6700629B1 (en) | 2000-07-06 | 2004-03-02 | Mitsubishi Denki Kabushiki Kaisha | Video intermediate frequency processing apparatus |
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