JPH01106455A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH01106455A
JPH01106455A JP62263433A JP26343387A JPH01106455A JP H01106455 A JPH01106455 A JP H01106455A JP 62263433 A JP62263433 A JP 62263433A JP 26343387 A JP26343387 A JP 26343387A JP H01106455 A JPH01106455 A JP H01106455A
Authority
JP
Japan
Prior art keywords
lead frame
integrated circuit
circuit element
circuit device
metal wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62263433A
Other languages
English (en)
Inventor
Mitsuaki Uenishi
上西　光明
Tatsuo Kikuchi
菊池　立郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62263433A priority Critical patent/JPH01106455A/ja
Publication of JPH01106455A publication Critical patent/JPH01106455A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明はＩＣカード等に使用する半導体集積回路装置に
関するものである。
従来の技術 近年、記憶容量の大きさ、機密保持の点から。
マイクロコンピュータ、メモリなどの集積回路素子を内
蔵したＩＣカードが実用化されつつある。
このＩＣカードは、塩化ビニル等のプラスチックカード
に、リーダー・ライター等の外部機器との接続のための
端子を有する半導体集積回路装置が埋設される構成であ
シ、この半導体集積回路装置は、プラスチックカードの
厚み以下の極めて薄型に構成することが必要とされる。
このため、従来の半導体集積回路装置は、第３図に示す
ように、フィルム状の絶縁基板１１に、外部接続用の端
子ハタ−フッ０１回路パターン９及びスルーホール８等
の配線導体を形成した薄型配線基板に、集積回路素子１
４を接着剤１３によりダイスボンディングし、集積回路
素子１４の入出力電極と回路パターン９とをワイヤポン
ディング方式等によシ金属線１５で接続する。また、樹
脂封止の際に、樹脂流れを防止するために封止枠１２を
絶縁基板１１に接着して設け、エポキシ樹脂等の封止材
１６によシ各部材を封止して得られる（参照：特開昭５
５−５６６４７号公報、特開昭５８−９２５９７号公報
）。
発明が解決しようとする問題点 Ｉ（ｉカードに搭載される半導体集積回路装置において
は、薄型化と同時に、高寸法精度でかつ低コストである
ことが求められている。しかしながら、前述したような
集積回路装置においては、用いられる配線基板が、絶縁
基板１１０両面に配線導体を形成し、スルーホール８に
よって接続したスルーホール付両面配線基板であるので
次のような問題点を有している。（１）配線基板が高価
である。
（巧スルーホール形成はめっきにより行うので、この時
のめっき厚のバラツキが配線基板の総厚のバラツキとな
り、良好な厚み寸法精度が得にくい。
（３）集積回路素子１４の樹脂封止の時、樹脂がスルー
ホールより流出するので、流出防止のためにスルーホー
ルを封口する手段が必要である。
本発明は、上記問題点に鑑みてなされたもので、高寸法
精度でかつ高能率に製造でき、しかも安価な半導体集積
回路装置を提供するものである。
問題点を解決するための手段 この目的を達成するために、本発明は所定のパターンに
加工した、リードフレームの一方の面を外部機器との接
続のための端子面、他方の面を集積回路素子の固定面と
し、リードフレームの固定面側に、集積回路素子の近傍
、あるいは、集積回路素子と端子面とをワイヤポンディ
ング方式等によシ結線する金属線の接合部の近傍に、微
小溝を形成、上記リードフレームと集積回路素子とを接
着、固定して、端子面を除いて、上記の各部材をエポキ
シ樹脂等で封止した構成の半導体集積回路装置としてい
る。
−作用 このような構成にすれば、集積回路素子とリードフレー
ムを接着、固定する時に、一定の厚みの接着層が形成さ
れた後、不要な接着剤は微小溝に吸収され、この溝の外
側には流出することがない。
従って、接着剤がリードフレームの端子面側に流出する
ことがなく、外部機器との良好な接続が可能となる。ま
た、リードフレームの金属線の接合部にも接着剤が流出
せず、この接合部と集積回路素子とが良好に結線される
。このようにリードフレームに微小溝を形成することに
よって、初めて本発明の半導体集積回路装置を具現化す
ることができる。
実施例 第１図に本発明の半導体集積回路装置の一実施例として
、その断面図を示す。第１図において、１は金属材料か
らなるリードフレーム、２はリードフレーム１に形成し
た微小溝、３はリードフレーム１と集積回路素子とを接
着、固定する接着剤、４は集積回路素子、５は金属線、
６は封止樹脂である。外部機器との接続のため所定の端
子パターンに加工したリードフレーム１の一方の面に、
金属線６の接合部の近傍で、微小溝２を形成、集積回路
素子４を接着剤３を介して接着、固定し、金属線６によ
シリードフレーム１と結線して、上記の各部材を、リー
ドフレーム１の他方の面を露出して、封止樹脂６で封止
した構成としている。
また、第２図に別の実施例として、本発明の半導体集積
回路装置の断面図を示す。第２図の各番号は第１図に示
すものと同じである。この場合。
集積回路素子４の近傍で、リードフレーム１に微小溝２
を形成した構成であシ、この微小溝２は、集積回路素子
４の裏面に形成しても良い。
さらに、このような微小溝２は、リードフレーム１の金
属線５の接合部の近傍（第１図）と同時に、集積回路素
子４の近傍（第２図）に形成する構造であっても良い。
このような構成にすれば、いずれの場合も、接着剤３の
不要に量は微小溝２に吸収されて、リードフレーム１の
端子面に露出したり、金属線５の接合部に流出したシす
ることがない。
発明の効果 以上のように、本発明の構成は、集積回路素子とリード
フレームを接着、固定する接着剤を不要な部分、即ち、
外部機器との接続のための端子面やワイヤポンド方式等
による金属線の接合部等に流出させることがなく、良好
な電気的接続を可能にするものである。このことによシ
初めて、安価なリードフレームを使用し、しかも、一般
に知られている樹脂成形法を本発明の半導体集積回路装
置に適用することができる。従って、本発明はその材料
費が低減し、また、その製造能率及び寸法精度が向上す
るという工業価値の高い効果をもたらすものである。む
ろん、ＩＣカード等に本発明の半導体集積回路装置を使
用すれば、ＩＣカード自身の価格を低減し、その寸法精
度を向上できることは言うまでもない。
【図面の簡単な説明】
第１図は本発明の一実施例を示す半導体集積回路装置の
断面図、第２図は本発明の別の実施例を示す半導体集積
回路装置の断面図、第３図は従来例の半導体集積回路装
置の断面図である。 １・・・・・・リードフレーム、２・・・・・・微小溝
、３・・・・・・接着剤、４・・・・・・集積回路素子
、５・・・・・・金属線、６・・・・・・封止樹脂。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名１−
−−　ソード７しｉム Ｃ−−＃　　　　庸 第２図 第　３　図 １σ　　　ＩＩ　　１０　　　ゾ　θ

Claims (1)

    【特許請求の範囲】
  1. 　リードフレームの一方の面を外部機器との接続のため
    の端子面、他方の面を集積回路素子の固定面とし、上記
    リードフレームの固定面側に、集積回路素子の近傍、あ
    るいは、集積回路素子と端子面とを結線する金属線の接
    合部の近傍に、微小溝を形成し、上記リードフレームと
    集積回路素子とを接着、固定して、端子面を除いて、上
    記各部材を封止樹脂で封止した半導体集積回路装置。
JP62263433A 1987-10-19 1987-10-19 半導体集積回路装置 Pending JPH01106455A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62263433A JPH01106455A (ja) 1987-10-19 1987-10-19 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62263433A JPH01106455A (ja) 1987-10-19 1987-10-19 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH01106455A true JPH01106455A (ja) 1989-04-24

Family

ID=17389436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62263433A Pending JPH01106455A (ja) 1987-10-19 1987-10-19 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH01106455A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
JPH1154551A (ja) * 1997-08-04 1999-02-26 Matsushita Electron Corp 樹脂封止型半導体装置およびその製造方法
WO1999000826A3 (en) * 1997-06-27 1999-05-27 Matsushita Electronics Corp Resin molded type semiconductor device and a method of manufacturing the same
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
US6831372B2 (en) * 2001-09-28 2004-12-14 Infineon Technologies Ag Electronic devices with semiconductor chips and a leadframe with device positions and methods for producing the same
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
WO1999000826A3 (en) * 1997-06-27 1999-05-27 Matsushita Electronics Corp Resin molded type semiconductor device and a method of manufacturing the same
KR100397539B1 (ko) * 1997-06-27 2003-09-13 마츠시타 덴끼 산교 가부시키가이샤 수지밀봉형 반도체 장치 및 그 제조방법
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
CN100423253C (zh) * 1997-06-27 2008-10-01 松下电器产业株式会社 树脂密封型半导体装置及其制造方法
US7538416B2 (en) 1997-06-27 2009-05-26 Panasonic Corporation Resin molded type semiconductor device and a method of manufacturing the same
JPH1154551A (ja) * 1997-08-04 1999-02-26 Matsushita Electron Corp 樹脂封止型半導体装置およびその製造方法
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
EP1335427A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device
EP1335428A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device and method for manufacturing the same
US6831372B2 (en) * 2001-09-28 2004-12-14 Infineon Technologies Ag Electronic devices with semiconductor chips and a leadframe with device positions and methods for producing the same

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