JPH01105569A - Semiconductor integrated device and removing method for malfunction thereof - Google Patents
Semiconductor integrated device and removing method for malfunction thereofInfo
- Publication number
- JPH01105569A JPH01105569A JP26325587A JP26325587A JPH01105569A JP H01105569 A JPH01105569 A JP H01105569A JP 26325587 A JP26325587 A JP 26325587A JP 26325587 A JP26325587 A JP 26325587A JP H01105569 A JPH01105569 A JP H01105569A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- lower electrode
- semiconductor integrated
- insulating film
- integrated device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims description 12
- 230000007257 malfunction Effects 0.000 title description 2
- 239000003990 capacitor Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000002344 surface layer Substances 0.000 claims abstract description 6
- 230000007547 defect Effects 0.000 claims description 24
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000002950 deficient Effects 0.000 abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 238000000605 extraction Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体基板に形成されたコンデンサを備えた
半導体集積装置及びその不良除去方法、特にそのコンデ
ンサの溝道とそのコンデンサの不良除去方法に関するも
のである。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated device having a capacitor formed on a semiconductor substrate and a method for removing defects thereof, particularly a groove in the capacitor and a method for removing defects in the capacitor. It is related to.
（従来の技術）
従来、このような分野の技術としては、例えば第２図及
び第３図のようなものがあった。以下、その構成を説明
する。(Prior Art) Conventionally, there have been technologies in this field, such as those shown in FIGS. 2 and 3, for example. The configuration will be explained below.
第２図は従来の半導体集積装置におけるコンデンサの平
面図、及び第３図はそのＡ−Ａ線断面拡大図である。FIG. 2 is a plan view of a capacitor in a conventional semiconductor integrated device, and FIG. 3 is an enlarged cross-sectional view taken along line A--A.
このコンデンサは、例えばバイポーラ型半導体集積装置
に設けられるもので、バイポーラ型トランジスタ等の能
動素子が形成されるＮ型シリコン基板１の表層には、高
濃度Ｎ型不純物層からなる下部電極２が形成され、さら
にその上にはシリコン酸化１１３を介して、導電層から
なる上部電極４が形成されている。ざらにシリコン酸化
膜３上には、上部電極４に接続された取出し配線５と、
コンタクト孔を介して下部電極２に接続された取出し配
線６とが形成されている。This capacitor is provided, for example, in a bipolar semiconductor integrated device, and a lower electrode 2 made of a highly concentrated N-type impurity layer is formed on the surface layer of an N-type silicon substrate 1 on which active elements such as bipolar transistors are formed. Further, an upper electrode 4 made of a conductive layer is formed thereon via silicon oxide 113. Roughly on the silicon oxide film 3, there is a lead-out wiring 5 connected to the upper electrode 4;
A lead wiring 6 connected to the lower electrode 2 through the contact hole is formed.
以上の構成において、取出し配線５，６を通して、上部
電極４、酸化シリコン膜３、及び下部電極２からなるコ
ンデンサに対する電荷の充電または放電が行われる。こ
のコンデンサの容ＩＣは、次式で表わされる。In the above configuration, the capacitor composed of the upper electrode 4, the silicon oxide film 3, and the lower electrode 2 is charged or discharged through the lead-out wirings 5 and 6. The capacitance IC of this capacitor is expressed by the following equation.
但し、Ａ；電極の対向面積
ε０；真空の誘電率
εｏｘ’シリコン酸化膜
の比誘電率
ｔｏｘ”シリコン酸化膜
の膜厚
第４図は第２図のコンデンサの耐圧特性図であり、横軸
に印加電界、縦軸に破壊頻度がとられている。However, A: opposing area of electrodes ε0; dielectric constant in vacuum εox' relative dielectric constant of silicon oxide film tox'' film thickness of silicon oxide film Figure 4 is a breakdown voltage characteristic diagram of the capacitor in Figure 2; The applied electric field and the breakdown frequency are plotted on the vertical axis.
第４図に示すように、前記のようなコンデンサにあって
は、高電界領域での破壊分布と共に、比較的低電界で絶
縁破壊するものがある。これは、コンデンサの対向部分
内におけるシリコン酸化膜３に局所的な欠陥が存在する
場合に生ずる。このような低電界で絶縁破壊するコンデ
ンサは、破壊によって上・下部電極４，２間が短絡して
大きな電流が流れ、半導体集積装置の動作上問題となる
。As shown in FIG. 4, among the capacitors described above, there are some that exhibit dielectric breakdown in a relatively low electric field as well as breakdown distribution in a high electric field region. This occurs when a local defect exists in the silicon oxide film 3 within the opposing portion of the capacitor. In a capacitor that undergoes dielectric breakdown under such a low electric field, the breakdown causes a short circuit between the upper and lower electrodes 4 and 2, causing a large current to flow, which poses a problem in the operation of the semiconductor integrated device.
そこで、半導体集積装置の試験時に、コンデンサ電圧印
加試験を行い、コンデンサに動作上必要な電圧を印加し
、その電圧で破壊するものは取り除くようにしていた。Therefore, when testing a semiconductor integrated device, a capacitor voltage application test is performed to apply a voltage necessary for operation to the capacitor, and to remove those that would be destroyed by that voltage.
（発明が解決しようとする問題点）
しかしながら、上記構成のコンデンサ及びその不良除去
方法では、次のような問題があった。(Problems to be Solved by the Invention) However, the capacitor having the above configuration and the method for removing defects thereof have the following problems.
前記コンデンサにおいて、大きな容量を得ようとすれば
シリコン酸化膜３の膜厚ｔ。Ｘを小さくすればよいが、
その膜厚ｔ。Ｘには必要な絶縁破壊電圧の関係から下限
があるため、電極対向面積Ａを大きくする必要がある。In the capacitor, if a large capacity is to be obtained, the thickness t of the silicon oxide film 3 must be increased. You can make X smaller, but
Its film thickness t. Since X has a lower limit due to the required dielectric breakdown voltage, it is necessary to increase the electrode facing area A.
ところが、電極対向面積Ａを大きくすると、その増加に
比例してその対向面積内に酸化膜欠陥が存在する確率が
増えるために、第４図に示した低電界での破壊頻度が増
加してコンデンサの不良率が増し、それによって半導体
集積装置の歩留りを低下させるという問題があった。However, when the electrode facing area A is increased, the probability that oxide film defects exist within the facing area increases in proportion to the increase, so the frequency of breakdown in low electric fields as shown in Figure 4 increases, and the capacitor There is a problem in that the defective rate of semiconductor integrated devices increases, thereby reducing the yield of semiconductor integrated devices.
また、前記のコンデンサ不良除去方法では、コンデンサ
電圧印加試験によって短絡したものは不良品として取り
除くようにしているが、局所的な酸化膜欠陥によってコ
ンデンサ全体が使用できなくなり、それによって半導体
集積装置の歩留りが低下するという問題があった。In addition, in the above-mentioned capacitor defect removal method, capacitors that are short-circuited during a capacitor voltage application test are removed as defective products, but local oxide film defects may make the entire capacitor unusable, thereby reducing the yield of semiconductor integrated devices. There was a problem that the
本発明は前記従来技術が持っていた問題点として、大容
量コンデンサを得るための電極対向面積の増加によるコ
ンデンサ不良率の、増加という点と、局所的な酸化膜欠
陥によりコンデンサ全体が使用不可能になる点について
解決した半導体集積装置及びその不良除去方法を提供す
るものである。The present invention solves the problems that the conventional technology had, such as an increase in the capacitor defect rate due to an increase in the electrode facing area to obtain a large capacity capacitor, and an unusable capacitor as a whole due to local oxide film defects. The object of the present invention is to provide a semiconductor integrated device and a method for removing defects thereof, which solve the problem.
（問題点を解決するための手段）
第１の発明は前記問題点を解決するために、半導体基板
に形成された能動素子とその半導体基板の一部に集積し
て形成されたコンデンサとを備えた半導体集積装置にお
いて、前記コンデンサは、前記半導体基板の表層に形成
された高濃度不純物層からなる下部電極と、前記下部電
極の表面に形成された絶縁膜と、前記絶縁膜上に形成さ
れた導電層からなる複数の上部電極と、一部に配線幅の
狭い領域を有し前記複数の上部電極を並列接続するため
の取出し配線とを備えたもので坐る。(Means for Solving the Problems) In order to solve the above problems, the first invention includes an active element formed on a semiconductor substrate and a capacitor formed integrally on a part of the semiconductor substrate. In the semiconductor integrated device, the capacitor includes a lower electrode made of a highly concentrated impurity layer formed on a surface layer of the semiconductor substrate, an insulating film formed on the surface of the lower electrode, and a lower electrode formed on the insulating film. The device is equipped with a plurality of upper electrodes made of a conductive layer, and an extraction wiring having a narrow wiring width region in a part and connecting the plurality of upper electrodes in parallel.
また、第２の発明は半導体集積装置におけるコンデンサ
の不良なものを除去する不良除去方法において、第１の
発明の半導体集積装置を用いて、予め前記下部電極及び
取出し配線に高電圧を印加し、短絡している上部電極及
び下部電極に対応する前記取出し配線の配線幅の狭い領
域を溶断するようにしたものである。Further, a second invention is a defect removal method for removing defective capacitors in a semiconductor integrated device, using the semiconductor integrated device of the first invention, applying a high voltage to the lower electrode and the lead-out wiring in advance, The narrow wiring width region of the lead-out wiring corresponding to the short-circuited upper electrode and lower electrode is blown out.
（作 用）
第１の発明によれば、以上のように半導体集積装置を構
成したので、複数個に分割され、かつ並列接続された複
数個の単位上部電極は、その下の共通絶縁膜を機能的に
複数個に分割し、絶縁膜欠陥の発生確率を減少させるよ
うに働き、それによって低電界での破壊頻度が少なくな
る。また、第２の発明の不良除去方法では、コンデンサ
電圧印加試験時において共通の下部電極と上部電極用の
取出し配線とに高電圧を印加し、絶縁膜欠陥により短絡
した単位コンデンサに対してはその短絡電流によって配
線幅の狭い領域を溶断させ、その不良な単位コンデンサ
のみ切り離す。これにより、他の良品の単位コンデンサ
が使用可能になり、それによって半導体集積装置の歩留
りが向上する。(Function) According to the first invention, since the semiconductor integrated device is configured as described above, the plurality of unit upper electrodes that are divided into a plurality of pieces and connected in parallel can be connected to the common insulating film thereunder. It is functionally divided into a plurality of parts and works to reduce the probability of occurrence of insulating film defects, thereby reducing the frequency of breakdown in low electric fields. In addition, in the defect removal method of the second invention, a high voltage is applied to the common lower electrode and the lead wire for the upper electrode during the capacitor voltage application test, and a high voltage is applied to the unit capacitor that is short-circuited due to an insulating film defect. The short-circuit current causes the narrow area of the wiring to melt, disconnecting only the defective unit capacitor. This makes it possible to use other good unit capacitors, thereby improving the yield of semiconductor integrated devices.
従って前記問題点を除去できるのである。′（実施例）
第１図は本発明の実施例を示す半導体集積装置における
コンデンサの平面図、第５図は第１図のＢ−Ｂ線断面拡
大図である。Therefore, the above-mentioned problem can be eliminated. (Embodiment) FIG. 1 is a plan view of a capacitor in a semiconductor integrated device showing an embodiment of the present invention, and FIG. 5 is an enlarged cross-sectional view taken along the line B--B in FIG. 1.
このコンデンサは、例えばバイポーラ型半導体集積装置
に設けられるもので、バイポーラ型トランジスタ等の能
動素子が形成されるＮ型シリコン基板等の半導体基板１
１の表層には、Ｎ型等の高濃度不純物層からなる下部電
極１２が形成されている。この下部電極１２は、例えば
バイポーラ型トランジスタのエミッタ拡散層と同時に不
純物拡散によって形成されるもので、低い抵抗率を有し
ている。下部電極１２の表面には、酸化処理によって形
成されたシリコン酸化膜等の絶縁膜１３が形成され、さ
らにその絶縁膜１３上に、Ａ、ｌｌ等の導電層からなる
複数個の分割された上部電極１４が形成されている。絶
縁膜１３は、その膜厚により、完成されたコンデンサの
容量及び絶縁破壊電圧が変化する。この絶縁膜１３上に
はざらに、複数個の上部電極１４を並列接続するための
引出し配線１５と、絶縁膜１３に形成されたコンタクト
孔１３ａを通して下部電極１２と接続された引出し配線
１６とが形成されている。各上部電極１４に接続された
引出し配線１５には、部分的に配線幅の狭い領域１５ａ
が形成されて０る。通常これらの上部電極１４及び取出
し配線１５．１６は、絶縁膜１３にコンタクト孔１３ａ
を形成した後に、全面にＡ、ｌｌ等の導電層を被着し、
その導電層をホトリソ技術を用いて選択的にエツチング
することにより、同時に形成される。This capacitor is provided, for example, in a bipolar semiconductor integrated device, and includes a semiconductor substrate 1 such as an N-type silicon substrate on which active elements such as bipolar transistors are formed.
A lower electrode 12 made of a high concentration impurity layer such as N-type is formed on the surface layer of the electrode 1 . This lower electrode 12 is formed, for example, by impurity diffusion simultaneously with the emitter diffusion layer of a bipolar transistor, and has a low resistivity. An insulating film 13 such as a silicon oxide film formed by oxidation treatment is formed on the surface of the lower electrode 12, and a plurality of divided upper parts made of conductive layers such as A and 11 are formed on the insulating film 13. An electrode 14 is formed. The capacitance and dielectric breakdown voltage of the completed capacitor vary depending on the thickness of the insulating film 13. Roughly on this insulating film 13, there are a lead wire 15 for connecting a plurality of upper electrodes 14 in parallel, and a lead wire 16 connected to the lower electrode 12 through a contact hole 13a formed in the insulating film 13. It is formed. The lead wiring 15 connected to each upper electrode 14 has a partially narrow wiring area 15a.
is formed and becomes 0. Normally, these upper electrodes 14 and lead-out wirings 15 and 16 are connected to contact holes 13a in the insulating film 13.
After forming, conductive layers such as A and ll are deposited on the entire surface,
They are simultaneously formed by selectively etching the conductive layer using photolithography.
以上のように構成されるコンデンサにおいて、複数個の
上部電極１４は取出し配線１５に並列接続され、その下
の絶縁膜１３及び下部電極１２は総ての上部電極１４に
対して共通になっている。In the capacitor configured as described above, the plurality of upper electrodes 14 are connected in parallel to the extraction wiring 15, and the underlying insulating film 13 and lower electrode 12 are common to all the upper electrodes 14. .
そのため、取出し配線１５．１６を通して、各単位コン
デンサに対して同時に電荷の充電または放電が行われる
ことになる。そしてコンデンサの全容量は各単位コンデ
ンサの容量の和となる。また、一部の単位コンデンサが
破壊されている場合には、並列接続のためにその一部の
単位コンデンサのみが動作不良となり、その他の単位コ
ンデンサは正常動作を行ってその単位コンデンサの容量
の和が全体の容量となる。Therefore, each unit capacitor is simultaneously charged or discharged through the lead-out wiring 15, 16. The total capacitance of the capacitor is then the sum of the capacitances of each unit capacitor. In addition, if some unit capacitors are destroyed, only some of them will malfunction due to parallel connection, and the other unit capacitors will operate normally and the sum of the capacitances of the unit capacitors will be is the total capacity.
次に、前記コンデンサの不良除去方法について説明する
。Next, a method for removing defects from the capacitor will be explained.
コンデンサの動作状態を検査するために、コンデンサ電
圧印加試験時に取出し配線１５．１６に高電圧を印加す
る。並列コンデンサの全電極対向部分内の絶縁膜１３の
一部に欠陥が存在している場合、印加された電圧によっ
てこの欠陥を含む単位コンデンサが破壊し、上部電極１
４と下部電極１２間が短絡してその取出し配線１５．１
６に大きな短絡電流が流れる。この時、取出し配線１５
内の配線幅が狭くなった領域１５ａでの電流密度は大き
くなり、その領域１５ａが溶断される。例えば、幅４μ
ｍ、厚さ１μｍのＡＮ配線を考えた場合、そのＡ、ｌ！
配線は４００ｍＡ程度の電流で溶断することが知られて
いる。このように不良の単位コンデンサ箇所の領域１５
ａが溶断されると、その不良の単位コンデンサは取出し
配線１５から切り離され、初期の並列コンデンサからこ
の単位コンデンサのみが簡単に取り除かれることになる
。In order to inspect the operating state of the capacitor, a high voltage is applied to the lead wires 15 and 16 during a capacitor voltage application test. If a defect exists in a part of the insulating film 13 in the portion of the parallel capacitor that faces all the electrodes, the unit capacitor containing this defect is destroyed by the applied voltage, and the upper electrode 1
4 and the lower electrode 12 are short-circuited and the lead-out wiring 15.1
A large short-circuit current flows through 6. At this time, take out wiring 15
The current density in the region 15a where the wiring width is narrowed increases, and the region 15a is blown out. For example, width 4μ
m, when considering an AN wiring with a thickness of 1 μm, its A, l!
It is known that wiring can be fused with a current of about 400 mA. In this way, area 15 of the defective unit capacitor location
When a is fused, the defective unit capacitor is separated from the lead-out wiring 15, and only this unit capacitor can be easily removed from the initial parallel capacitors.
この時、並列コンデンサの全容伍は初期の容量より１つ
の単位コンデンサの容量分だけ減少する。At this time, the total capacity of the parallel capacitors decreases from the initial capacity by the capacity of one unit capacitor.
しかし、１個あるいは複数個の単位コンデンサが開放さ
れても、必要な容量が確保されるように単位コンデンサ
の分割数を増やしておけば、並列コンデンサの機能は保
持される。However, even if one or more unit capacitors are opened, the function of the parallel capacitor can be maintained if the number of divisions of the unit capacitors is increased to ensure the required capacity.
本実施例のコンデンサ構造及びその不良除去方法では、
次のような利点を有している。In the capacitor structure and defect removal method of this example,
It has the following advantages:
従来の上部電極を複数個に分割し、その分割された各上
部電極１４に接続された取出し配線１５の一部に配線幅
の狭い領域１５ａを設けるようにしたので、単位コンデ
ンサの絶縁膜１３に欠陥が存在し、コンデンサ電圧印加
試験時に絶縁破壊を起こし、−時的にコンデンサの上部
電極１４と下部電極１２が短絡状態となっても、試験中
に前記絶縁膜欠陥が存在した単位コンデンサの上部電極
用取出し配線１５のみが自動的に開放され、全並列コン
デンサの機能は保持されるので、コンデンサの不良率は
低減し、半導体集積装置の歩留りが著しく向上する。そ
の上、不良な単位コンデンサの取出し配線１５のみが自
動的に開放されるため、゛コンデンサ電圧印加試験を兼
ねて不良な単位コンデンサの除去も行え、それによって
不良品除去作業の簡略化が図れる。本実施例の効果は、
特に大容量を得るために大きな対向面積を有するコンデ
ンサを備える半導体集積装置において大きい。The conventional upper electrode is divided into a plurality of parts, and a region 15a with a narrow wiring width is provided in a part of the extraction wiring 15 connected to each divided upper electrode 14, so that the insulating film 13 of the unit capacitor Even if a defect exists and dielectric breakdown occurs during the capacitor voltage application test, and the upper electrode 14 and lower electrode 12 of the capacitor are temporarily short-circuited, the upper part of the unit capacitor in which the insulating film defect existed during the test Since only the electrode lead wiring 15 is automatically opened and the functions of all parallel capacitors are maintained, the defect rate of capacitors is reduced and the yield of semiconductor integrated devices is significantly improved. Furthermore, since only the lead-out wiring 15 of the defective unit capacitor is automatically opened, the defective unit capacitor can also be removed while performing the capacitor voltage application test, thereby simplifying the work of removing defective products. The effects of this example are as follows:
This is particularly large in semiconductor integrated devices that include capacitors that have a large facing area in order to obtain large capacitance.
なお、本発明は図示の実施例に限定されず、種々の変形
が可能である。その変形例としては、例えば次のような
ものがおる。Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.
（ｉ） 上記実施例において、半導体基板１１はＰ型シ
リコン基板等の他の基板でもよく、それに応じて下部電
極１２もＰ型等の他の極性にすればよい。絶縁膜１３を
窒化シリコン膜等の他の材料にしたり、ざらに上部電極
１４及び取出し配線１５．１６をポリシリコン等の伯の
導電材料で形成してもよい。また、分割された上部電極
１４の平面形状や配列状態を他の形態にしたり、それに
応じて取出し配線１５を伯の配置状態にすることも可能
である。(i) In the above embodiments, the semiconductor substrate 11 may be another substrate such as a P-type silicon substrate, and the lower electrode 12 may also be of other polarity such as P-type accordingly. The insulating film 13 may be made of another material such as a silicon nitride film, or the upper electrode 14 and the lead-out wirings 15 and 16 may be made of a conductive material such as polysilicon. Further, it is also possible to change the planar shape and arrangement state of the divided upper electrodes 14 to other shapes, and to arrange the lead-out wiring 15 in a square arrangement state accordingly.
（１１〉 上記実施例では、バイポーラ型の半導体集
積装置について説明したが、ユニポーラ型等の他の半導
体集積装置にも適用可能である。(11> In the above embodiment, a bipolar type semiconductor integrated device has been described, but it is also applicable to other semiconductor integrated devices such as a unipolar type.
（発明の効果）
以上詳細に説明したように、第１の発明のコンデンサで
は、従来の上部電極を複数に分割してそれらを取出し配
線で並列に接続したので、それらの下に設けられる絶縁
膜の欠陥発生確率を減少させ、それによって低電界での
破壊頻度の減少と、それによる歩留りの向上が図れる。(Effects of the Invention) As explained in detail above, in the capacitor of the first invention, the conventional upper electrode is divided into a plurality of parts and these are connected in parallel with wiring, so that the insulating film provided below them is The probability of defect occurrence is reduced, thereby reducing the frequency of breakdown in low electric fields and improving yield.
また第２の発明の不良除去方法では、取出し配線の一部
に配線幅の狭い領域を設けておき、取出し配線と下部電
極との間に高電圧を印加して不良な単位コンデンサに生
じる短絡電流によって配線幅の狭い領域を溶断するよう
にしたので、簡単に不良な単位コンデンサを切り離すこ
とができ、それによって不良箇所の除去を簡易、的確に
行える。In addition, in the defect removal method of the second invention, a region with a narrow wiring width is provided in a part of the extraction wiring, and a high voltage is applied between the extraction wiring and the lower electrode to eliminate the short-circuit current generated in the defective unit capacitor. Since the area where the wiring width is narrow is fused, the defective unit capacitor can be easily separated, thereby allowing the defective portion to be removed easily and accurately.
第１図は本発明の実施例を示す半導体集積装置における
コンデンサの平面図、第２図は従来の半導体集積装置に
おけるコンデンサの平面図、第３図は第２図のＡ−Ａ線
断面拡大図、第４図は第２図の耐圧特性図、第５図は第
１図のＢ−Ｂ線断面拡大図である。
１１・・・・・・半導体基板、１２・・・・・・下部電
極、１３・・・・・・絶縁膜、１４・・・・・・上部電
極、１５．１６・・・・・・取出し配線、１５ａ・・・
・・・配線幅の狭い領域。
出願人代理人 柿 本 恭 成１２°下郁電極
本発明の半導体集積装置のコレデンサ
第２図のＡ−Ａ線断面拡大図FIG. 1 is a plan view of a capacitor in a semiconductor integrated device showing an embodiment of the present invention, FIG. 2 is a plan view of a capacitor in a conventional semiconductor integrated device, and FIG. 3 is an enlarged cross-sectional view taken along line A-A in FIG. , FIG. 4 is a breakdown voltage characteristic diagram of FIG. 2, and FIG. 5 is an enlarged cross-sectional view taken along the line B--B of FIG. 1. 11... Semiconductor substrate, 12... Lower electrode, 13... Insulating film, 14... Upper electrode, 15.16... Extraction Wiring, 15a...
...A region with narrow wiring width. Applicant's agent Kyo Kakimoto 12° lower electrode Enlarged cross-sectional view taken along line A-A of FIG. 2 of the correductor of the semiconductor integrated device of the present invention
Claims (1)
の一部に集積して形成されたコンデンサとを備えた半導
体集積装置において、 前記コンデンサは、 前記半導体基板の表層に形成された高濃度不純物層から
なる下部電極と、 前記下部電極の表面に形成された絶縁膜と、前記絶縁膜
上に形成された導電層からなる複数の上部電極と、 一部に配線幅の狭い領域を有し前記複数の上部電極を並
列接続するための取出し配線とを備えたことを特徴とす
る半導体集積装置。 ２、能動素子が形成された半導体基板の一部の表層に形
成された高濃度不純物層からなる下部電極と、前記下部
電極の表面に形成された絶縁膜と、前記絶縁膜上に形成
された導電層からなる複数の上部電極と、一部に配線幅
の狭い領域を有し前記複数の上部電極を並列接続するた
めの取出し配線とを備えたコンデンサを有する半導体集
積装置を用いて、 予め前記下部電極及び取出し配線に高電圧を印加し、 短絡している上部電極及び下部電極に対応する前記取出
し配線の配線幅の狭い領域を溶断することを特徴とする
半導体集積装置の不良除去方法。[Claims] 1. In a semiconductor integrated device comprising an active element formed on a semiconductor substrate and a capacitor integrated and formed on a part of the semiconductor substrate, the capacitor is formed on a surface layer of the semiconductor substrate. a lower electrode made of a high concentration impurity layer formed; an insulating film formed on the surface of the lower electrode; a plurality of upper electrodes made of a conductive layer formed on the insulating film; What is claimed is: 1. A semiconductor integrated device comprising a lead wire having a narrow area and connecting the plurality of upper electrodes in parallel. 2. A lower electrode made of a highly concentrated impurity layer formed on the surface layer of a part of the semiconductor substrate on which the active element is formed, an insulating film formed on the surface of the lower electrode, and a lower electrode formed on the insulating film. Using a semiconductor integrated device having a capacitor including a plurality of upper electrodes made of a conductive layer and a lead wire that partially has a narrow wiring width region and connects the plurality of upper electrodes in parallel, A method for removing defects in a semiconductor integrated device, characterized in that a high voltage is applied to a lower electrode and a lead-out wiring, and a narrow area of the lead-out wiring corresponding to the short-circuited upper electrode and lower electrode is fused.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26325587A JPH01105569A (en) | 1987-10-19 | 1987-10-19 | Semiconductor integrated device and removing method for malfunction thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26325587A JPH01105569A (en) | 1987-10-19 | 1987-10-19 | Semiconductor integrated device and removing method for malfunction thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01105569A true JPH01105569A (en) | 1989-04-24 |
Family
ID=17386930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26325587A Pending JPH01105569A (en) | 1987-10-19 | 1987-10-19 | Semiconductor integrated device and removing method for malfunction thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01105569A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0603101A1 (en) * | 1992-12-17 | 1994-06-22 | International Business Machines Corporation | A self protective decoupling capacitor structure |
| EP1416536A2 (en) * | 2002-11-04 | 2004-05-06 | Texas Instruments Incorporated | Eliminating defective decoupling capacitors |
| JP2009094093A (en) * | 2007-10-03 | 2009-04-30 | Nec Electronics Corp | Semiconductor device |
| JP2019110279A (en) * | 2017-12-20 | 2019-07-04 | スタンレー電気株式会社 | Piezoelectric type actuator |
-
1987
- 1987-10-19 JP JP26325587A patent/JPH01105569A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0603101A1 (en) * | 1992-12-17 | 1994-06-22 | International Business Machines Corporation | A self protective decoupling capacitor structure |
| JPH06283665A (en) * | 1992-12-17 | 1994-10-07 | Internatl Business Mach Corp <Ibm> | Self-protecting type decoupling capacitor |
| EP1416536A2 (en) * | 2002-11-04 | 2004-05-06 | Texas Instruments Incorporated | Eliminating defective decoupling capacitors |
| EP1416536A3 (en) * | 2002-11-04 | 2009-06-24 | Texas Instruments Incorporated | Eliminating defective decoupling capacitors |
| JP2009094093A (en) * | 2007-10-03 | 2009-04-30 | Nec Electronics Corp | Semiconductor device |
| JP2019110279A (en) * | 2017-12-20 | 2019-07-04 | スタンレー電気株式会社 | Piezoelectric type actuator |
| US11665966B2 (en) | 2017-12-20 | 2023-05-30 | Stanley Electric Co., Ltd. | Piezoelectric actuator |
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