JPH01100800A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPH01100800A
JPH01100800A JP62259028A JP25902887A JPH01100800A JP H01100800 A JPH01100800 A JP H01100800A JP 62259028 A JP62259028 A JP 62259028A JP 25902887 A JP25902887 A JP 25902887A JP H01100800 A JPH01100800 A JP H01100800A
Authority
JP
Japan
Prior art keywords
output
code data
register
program counter
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62259028A
Other languages
Japanese (ja)
Inventor
Yukishige Maeda
前田　幸茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62259028A priority Critical patent/JPH01100800A/en
Publication of JPH01100800A publication Critical patent/JPH01100800A/en
Pending legal-status Critical Current

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  • Stored Programmes (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To decrease an expense and to shorten a time without needing the retrial due to a code data error by providing a means to store the correcting part of code data and make access as necessary. CONSTITUTION:When a noncomformity is found at the code data of the AB address of a ROM 119 to store a user program, next, the correct code data is set to a first register 116 and an action is started. At this time, the output of a program counter 118 is successively changed, the code data making address by it is outputted from the ROM 119 and inputted to a gate group 120 by a switching circuit 114. When the output of the program counter 118 becomes the AB address, the output of the second register 115 and the output of the program counter 118 are coincident. Thus, an output terminal 101 of a comparator 117 is changed, and by the switching circuit 114, the output of the register 116, namely, the correct code data can be inputted to a gate group 120.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は読出し専用メモリ（以下ＲＯＭという）のメモ
リ制御方式、特にＲＯＭに格納したユーザプログラムに
ミスが発生し場合のメモリ制御方式〔従来の技術〕 従来、半導体気構回路などに内蔵されている記憶装置（
ＲＯＭ）に格納されたユーザプログラムは、第２図に示
すようにプログラムカウンタ２１４によってアドレス信
号２０１を発生させＲＯＭ２１５をアクセスし、指定さ
れたアドレスからユーザプログラムのコードデータを出
力し、その命令によって内部ゲート群２１６を制御し目
的の機能動作を行っていた。したがって上記のコードデ
ータにミスが発生した場合にはＲＯＭを作り直す必要が
あり、多大な時閉と費用がかかるという欠点がある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory control method for a read-only memory (hereinafter referred to as ROM), and particularly to a memory control method in the case where a mistake occurs in a user program stored in a ROM. Technology] Traditionally, memory devices (
As shown in FIG. 2, the user program stored in the ROM (ROM) generates an address signal 201 by the program counter 214, accesses the ROM 215, outputs the code data of the user program from the specified address, and executes internal operations according to the command. The gate group 216 was controlled to perform the desired functional operation. Therefore, if a mistake occurs in the above code data, it is necessary to recreate the ROM, which is disadvantageous in that it costs a lot of time and money.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明が解決しようとする問題点、換言すれば本発明の
目的は、コードデータの訂正部分を格納し必要に応じて
アクセスする手段を設けるようにして上記の欠点を改善
したメモリ制御方式を提供することにある。The problem to be solved by the present invention, in other words, the purpose of the present invention is to provide a memory control method that improves the above-mentioned drawbacks by providing means for storing the corrected portion of code data and accessing it as necessary. It's about doing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のメモリ制御方式は、読出し専用メモリと書換え
可能な第一のレジスタとを同時にアドレッシングするプ
ログラムカウンタと、前記プログラムカウンタの出力と
書き換え可能な第二のレジスタの出力とを比較する比較
回路と、前記比較回路の出力信号に従って前記読出し専
用メモリの出力を前記第一のレジスタの出力に切り換え
る切換回路とを有して構成される。The memory control method of the present invention includes a program counter that simultaneously addresses a read-only memory and a rewritable first register, and a comparison circuit that compares the output of the program counter with the output of a rewritable second register. , and a switching circuit that switches the output of the read-only memory to the output of the first register according to the output signal of the comparison circuit.

〔実施例〕〔Example〕

以下、本発明によるメモリ制御方式について図面を参照
して説明する。Hereinafter, a memory control method according to the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

同図においてメモリ制御方式は汎用端子１１１からアド
レスを格納する第二のレジスタ１１５にアドレスを書き
込んだり、データを格納する第一のレジスタ１１６にデ
ータを書き込む、１１８はプログラムカウンタ、１１７
は第二のレジスタ１１５の出力とプログラムカウンタ１
１８の出力を比較する比較器、１１９はユーザプログラ
ムを格納するＲＯＭ、１１４はＲＯＭ１１９の出力と第
一のレジスタ１１６の出力とを比較器１１７の出力によ
って切り換える切換回路、１０１は比較器１１７の出力
でありプログラムカウンタ１１８の出力と第二のレジス
タの出力とが一致したときに変化する信号線、１２０は
ゲート群である。In the figure, the memory control method writes an address from a general-purpose terminal 111 to a second register 115 that stores an address, writes data to a first register 116 that stores data, 118 is a program counter, and 117
is the output of the second register 115 and the program counter 1
119 is a ROM that stores a user program; 114 is a switching circuit that switches between the output of ROM 119 and the output of first register 116 according to the output of comparator 117; 101 is the output of comparator 117; A signal line 120, which changes when the output of the program counter 118 and the output of the second register match, is a gate group.

今、ユーザプログラムを格納したＲＯＭ１１９のＡＢ番
地のコードデータに不具合が発見された場合、まず汎用
端子１１１から第二のレジスタ１１５にＡＢをセットし
、次に正しいコードデータを第一のレジスタ１１６にセ
ットし動作を開始する。このとき、プログラムカウンタ
１１８の出力つまりＲＯＭアドレスは順次変化し、プロ
グラムカウンタ１１８の出力でアドレッシングされたコ
ードデータをＲＯＭ１１９から出力し切り換え回路１１
４によってゲート群１２０に入力する。If a defect is found in the code data at address AB in the ROM 119 that stores the user program, first set AB in the second register 115 from the general-purpose terminal 111, and then set the correct code data in the first register 116. Set and start operation. At this time, the output of the program counter 118, that is, the ROM address, changes sequentially, and the code data addressed by the output of the program counter 118 is output from the ROM 119, and the switching circuit 11
4 to the gate group 120.

プログラムカウンタ１１８の出力がＡＢ番地になると第
二のレジスタ１１５の出力とプログラムカウンタ１１８
の出力とが一致するので、比較器１１７の出力端子１０
１が変化して切り換え回路１１４によって第一のレジス
タ１１６の出力つまり正しいコードデータをゲート群１
２０に入力することができる。When the output of the program counter 118 reaches address AB, the output of the second register 115 and the program counter 118
Since the output of the comparator 117 matches the output of the
1 changes and the switching circuit 114 transfers the output of the first register 116, that is, the correct code data, to the gate group 1.
20 can be entered.

上記の実施例では単一アドレスについて説明したが、第
一のレジスタおよび第二のレジスタを複数個準備するこ
とによって複数アドレスについてもコードデータを変更
できる。またレジスタのかわりにランダムアクセスメモ
リ（ＲＡＭ）を用いることも可能である。In the above embodiment, a single address has been described, but by preparing a plurality of first registers and second registers, code data can be changed for a plurality of addresses as well. It is also possible to use random access memory (RAM) instead of registers.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明のメモリ制御方式によれば、
コードデータミスによる再試作をする必要がなく、費用
を軽減し時間を短縮する効果がある。As explained above, according to the memory control method of the present invention,
There is no need for re-prototyping due to code data errors, which has the effect of reducing costs and time.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のメモリ制御方式のブロック
図、第２図は従来のメモリ制御方式の例を示すブロック
図である。 １１４・・・切換え回路、１１５，１１６・・・レジス
タ、１１７・・・比較器、１１８・・・プログラムカウ
ンタ、１１９・・・ＲＯＭ。FIG. 1 is a block diagram of a memory control method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional memory control method. 114...Switching circuit, 115, 116...Register, 117...Comparator, 118...Program counter, 119...ROM.

Claims (1)

【特許請求の範囲】[Claims] 　読出し専用メモリと書換え可能な第一のレジスタとを
同時にアドレッシングするプログラムカウンタと、前記
プログラムカウンタの出力と書き換え可能な第二のレジ
スタの出力とを比較する比較回路と、前記比較回路の出
力信号に従って前記読出し専用メモリの出力を前記第一
のレジスタの出力に切り換える切換回路とを有すること
を特徴とするメモリ制御方式。a program counter for simultaneously addressing a read-only memory and a first rewritable register; a comparator circuit for comparing an output of said program counter with an output of a second rewritable register; and in accordance with an output signal of said comparator circuit. A memory control system comprising: a switching circuit that switches the output of the read-only memory to the output of the first register.
JP62259028A 1987-10-13 1987-10-13 Memory control system Pending JPH01100800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62259028A JPH01100800A (en) 1987-10-13 1987-10-13 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62259028A JPH01100800A (en) 1987-10-13 1987-10-13 Memory control system

Publications (1)

Publication Number Publication Date
JPH01100800A true JPH01100800A (en) 1989-04-19

Family

ID=17328336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62259028A Pending JPH01100800A (en) 1987-10-13 1987-10-13 Memory control system

Country Status (1)

Country Link
JP (1) JPH01100800A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621174U (en) * 1992-03-27 1994-03-18 中島通信機工業株式会社 Coaxial cable connector

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613595A (en) * 1979-07-13 1981-02-09 Fuji Electric Co Ltd Data selector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613595A (en) * 1979-07-13 1981-02-09 Fuji Electric Co Ltd Data selector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621174U (en) * 1992-03-27 1994-03-18 中島通信機工業株式会社 Coaxial cable connector

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