JP7494071B2 - メモリシステム - Google Patents
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- JP7494071B2 JP7494071B2 JP2020158140A JP2020158140A JP7494071B2 JP 7494071 B2 JP7494071 B2 JP 7494071B2 JP 2020158140 A JP2020158140 A JP 2020158140A JP 2020158140 A JP2020158140 A JP 2020158140A JP 7494071 B2 JP7494071 B2 JP 7494071B2
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- 239000000758 substrate Substances 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 2
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 1
- 238000013403 standard screening design Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Human Computer Interaction (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Logic Circuits (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
ウェイクアップ信号PEWAKE#は、ホスト装置100がメモリシステム1を起動させたいときにホスト装置100からメモリシステム1へ送信される信号である。リセット信号PERST#は、ホスト装置100がメモリシステム1を初期化したいときにホスト装置100からメモリシステム1へ送信される信号である。
また、バイポーラトランジスタQ4のエミッタは3.3Vの電源電圧に接続される。
その結果、バイポーラトランジスタQ2,Q3,Q4,Q6はオン状態となり、出力電圧は3.3Vとなる。
クロック要求信号CLKREQ#及びCLKREQBは双方向の信号であり、ポートUP1内のクロック要求信号CLKREQB用のピンからのロー信号は寄生ダイオードD1を通して、NMOSトランジスタNM1のソースSの電位を降下させ、ゲートGとソースS間に電位差が生じる。その結果、NMOSトランジスタNM1がオン状態となり、ポートDP1内のクロック要求信号CLKREQ#用のピンにロー信号が伝わる。
ウェイクアップ信号PEWAKE#及びPEWAKEBは双方向の信号であり、ポートUP2内のPEWAKEB用のピンからのロー信号は寄生ダイオードD2を通して、NMOSトランジスタNM2のソースSの電位を降下させ、ゲートGとソースS間に電位差が生じること。その結果、NM2がオン状態となり、ポートDP内のウェイクアップ信号PEWAKE#用のピンにロー信号が伝わる。
2…プリント基板
4…PCIeインターフェース
10…不揮発性メモリ
20…コントローラ
31…電圧自動切替え回路(第1の回路)
32…レベルシフト回路(第2の回路)
40…インターフェース
100…ホスト装置
Claims (9)
- ホスト装置に接続可能なメモリシステムであって、
不揮発性メモリと、
前記不揮発性メモリを制御し、第1の電圧が供給されるコントローラと、
前記メモリシステムと前記ホスト装置とが接続された状態で、前記ホスト装置から第1の信号及び第2の信号が入力され、前記第1の信号及び前記第2の信号が共に前記第1の電圧よりも低い第2の電圧を有する第1の場合において、前記第2の電圧を有する前記第2の信号を、前記第1の電圧に変換して第3の信号として前記コントローラに出力し、前記メモリシステムと前記ホスト装置とが接続された状態で、前記ホスト装置から前記第1の信号が入力されず前記第2の信号が入力され、前記第2の信号が前記第1の電圧を有する第2の場合において、前記第1の電圧を有する前記第2の信号を、電圧を変換させずに第4の信号として前記コントローラに出力する回路と
を具備するメモリシステム。 - 前記回路は前記第1の信号が入力される第1の回路を含み、前記第1の場合において、前記第1の回路の出力は第1の状態となり、前記第2の場合において、前記第1の回路の前記出力は前記第1の状態とは異なる第2の状態となる請求項1に記載のメモリシステム。
- 前記回路は前記第2の信号が入力される第2の回路を含み、前記第1の回路の前記出力が前記第1の状態となる場合には、前記第2の回路は前記第2の電圧を有する前記第2の信号を前記第3の信号に変換して出力し、前記第1の回路の前記出力が前記第2の状態となる場合には、前記第2の回路は前記第1の電圧を有する前記第2の信号を電圧変換せず前記第4の信号として出力する請求項2に記載のメモリシステム。
- 前記ホスト装置に接続可能なコネクタを更に具備し、
前記コネクタは第1のピン及び第2のピンを含み、
前記第1のピン及び前記第2のピンは前記回路に接続され、
前記第1のピンには前記第1の信号が入力され、前記第2のピンには前記第2の信号が入力される請求項1に記載のメモリシステム。 - 前記コネクタは、M.2規格に準拠した形状を有する請求項4に記載のメモリシステム。
- 前記メモリシステムと前記ホスト装置との間の信号の送受信はPCIe規格に準拠して行われ、
前記第1の信号は、前記PCIe規格で規定されるVIO 1.8V信号であり、
前記第2の信号は、前記PCIe規格で規定されるクロック要求信号CLKREQ#、ウェイクアップ信号PEWAKE#、又は、リセット信号PERST#であり、
前記第2の場合、前記回路は、前記PCIe規格で規定されるVIO CFG信号を出力する請求項1に記載のメモリシステム。 - 前記回路は、トランジスタを含み、前記トランジスタを通過させた前記第2の信号を、前記第3の信号又は前記第4の信号として出力する請求項1に記載のメモリシステム。
- 基板を更に具備し、
前記不揮発性メモリ、前記コントローラ、及び前記回路は、前記基板に実装される請求項1に記載のメモリシステム。 - 前記第1の電圧は3.3Vであり、前記第2の電圧は1,8Vである請求項1に記載のメモリシステム。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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JP2020158140A JP7494071B2 (ja) | 2020-09-23 | 2020-09-23 | メモリシステム |
US17/205,239 US11430501B2 (en) | 2020-09-23 | 2021-03-18 | Memory system |
TW110123525A TWI794855B (zh) | 2020-09-23 | 2021-06-28 | 記憶體系統 |
TW112102513A TWI834483B (zh) | 2020-09-23 | 2021-06-28 | 記憶體系統 |
CN202111002793.7A CN114253469B (zh) | 2020-09-23 | 2021-08-30 | 存储*** |
CN202310817472.5A CN116820345A (zh) | 2020-09-23 | 2021-08-30 | 存储*** |
US17/870,880 US11804256B2 (en) | 2020-09-23 | 2022-07-22 | Memory system |
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JP2020158140A JP7494071B2 (ja) | 2020-09-23 | 2020-09-23 | メモリシステム |
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JP7494071B2 (ja) * | 2020-09-23 | 2024-06-03 | キオクシア株式会社 | メモリシステム |
TWI768881B (zh) * | 2021-05-07 | 2022-06-21 | 慧榮科技股份有限公司 | 邊帶信號調整系統及其方法和儲存裝置 |
JP2023141299A (ja) * | 2022-03-23 | 2023-10-05 | キオクシア株式会社 | メモリシステム |
US20240094792A1 (en) * | 2022-09-21 | 2024-03-21 | Qualcomm Incorporated | Input-output voltage control for data communication interface |
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- 2021-03-18 US US17/205,239 patent/US11430501B2/en active Active
- 2021-06-28 TW TW112102513A patent/TWI834483B/zh active
- 2021-06-28 TW TW110123525A patent/TWI794855B/zh active
- 2021-08-30 CN CN202310817472.5A patent/CN116820345A/zh active Pending
- 2021-08-30 CN CN202111002793.7A patent/CN114253469B/zh active Active
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CN114253469A (zh) | 2022-03-29 |
CN114253469B (zh) | 2023-07-07 |
US11430501B2 (en) | 2022-08-30 |
TWI794855B (zh) | 2023-03-01 |
CN116820345A (zh) | 2023-09-29 |
TWI834483B (zh) | 2024-03-01 |
US20220358990A1 (en) | 2022-11-10 |
US11804256B2 (en) | 2023-10-31 |
TW202215258A (zh) | 2022-04-16 |
TW202321934A (zh) | 2023-06-01 |
JP2022052010A (ja) | 2022-04-04 |
US20220093156A1 (en) | 2022-03-24 |
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