JP7480789B2 - Connection structure and method for manufacturing the same - Google Patents

Connection structure and method for manufacturing the same Download PDF

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Publication number
JP7480789B2
JP7480789B2 JP2021567160A JP2021567160A JP7480789B2 JP 7480789 B2 JP7480789 B2 JP 7480789B2 JP 2021567160 A JP2021567160 A JP 2021567160A JP 2021567160 A JP2021567160 A JP 2021567160A JP 7480789 B2 JP7480789 B2 JP 7480789B2
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Japan
Prior art keywords
solder particles
electrode
solder
anisotropic conductive
conductive film
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JP2021567160A
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Japanese (ja)
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JPWO2021131620A1 (en
Inventor
邦彦 赤井
勝将 宮地
純一 欠畑
芳則 江尻
敏光 森谷
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Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
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Publication of JPWO2021131620A1 publication Critical patent/JPWO2021131620A1/ja
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Publication of JP7480789B2 publication Critical patent/JP7480789B2/en
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    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
    • H01R4/02—Soldered or welded connections
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    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0026—Apparatus for manufacturing conducting or semi-conducting layers, e.g. deposition of metal
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    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/20—Conductive material dispersed in non-conductive organic material
    • H01B1/22—Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
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Description

本発明は、接続構造体及び接続構造体の製造方法に関する。 The present invention relates to a connection structure and a method for manufacturing a connection structure.

電子デバイスに搭載される半導体チップは、回路基板上にワイヤーボンディングやはんだボールを用いたボールグリッドアレイ（ＢＧＡ）接続などで実装された後、絶縁性樹脂材料で封止され、半導体パッケージと呼ばれる機能集積体として利用される。特に、ＢＧＡ接続は、電極間ピッチを狭く出来ることから、半導体パッケージの小型化に寄与してきた（特許文献１）。Semiconductor chips mounted on electronic devices are mounted on circuit boards using wire bonding or ball grid array (BGA) connections using solder balls, and then sealed with insulating resin materials to be used as functional integrated units called semiconductor packages. In particular, BGA connections have contributed to the miniaturization of semiconductor packages because they allow for a narrower inter-electrode pitch (Patent Document 1).

近年は、スマートフォンやタブレットといった小型で高機能な製品向けに、半導体パケージの低背、薄型、高機能化が進行し、接続する電極数の増大と、電極間ピッチの狭小化が進んでいる。半導体パッケージの１次接続側では、１００μｍ以下の狭ピッチ接続を実現するために、銅ピラーの先端にはんだを積層したはんだ付Ｃｕピラー構造が用いられている（特許文献２）。In recent years, semiconductor packages have become lower, thinner, and more functional for small, high-performance products such as smartphones and tablets, and the number of electrodes to be connected is increasing and the pitch between electrodes is narrowing. On the primary connection side of the semiconductor package, a soldered Cu pillar structure in which solder is laminated on the tip of a copper pillar is used to achieve a narrow pitch connection of 100 μm or less (Patent Document 2).

また、環境性能の観点から２０００年代からは、スズに銀や銅を添加した鉛フリーはんだが用いられており、２６０℃前後のリフロー温度により実装がなされている。しかしながら、金属やガラスや樹脂などの複合体である半導体パッケージでは、２６０℃リフローによる熱履歴により、各材料の熱膨張率の違いから、実装部（はんだ部分）へ応力が掛かり、破壊が起こる課題があった。また、２６０℃リフローでは、はんだと電極の金属材料との合金化が進行し、破壊を促進する合金層が生成してしまう課題もあった。また、スズ－銀系統のはんだは、２６０℃リフローを必要とするため、より安価な樹脂材料を適用出来ない課題があった。特許文献３では、スズとビスマスを用いた２００℃以下の融点を有する低温はんだを用いた実装方法が開示されている。しかしながら、スズ－ビスマスはんだは、ビスマスが脆いことから外部からの衝撃によりはんだ接合部が破壊しやすい課題があった。特許文献４では、スズ－ビスマスはんだに、微量金属を添加することで、接合部の脆さを改善する試みがなされている。 In addition, from the viewpoint of environmental performance, lead-free solders in which silver or copper is added to tin have been used since the 2000s, and mounting is performed at a reflow temperature of around 260°C. However, in semiconductor packages, which are composites of metal, glass, resin, etc., the thermal history of 260°C reflow causes stress on the mounting part (solder part) due to the difference in the thermal expansion coefficient of each material, which causes a problem of destruction. In addition, in 260°C reflow, alloying of the solder and the metal material of the electrode progresses, and an alloy layer that promotes destruction is generated. In addition, since tin-silver type solder requires 260°C reflow, there is a problem that cheaper resin materials cannot be applied. Patent Document 3 discloses a mounting method using low-temperature solder that uses tin and bismuth and has a melting point of 200°C or less. However, tin-bismuth solder has a problem that the solder joint is easily broken by external impact because bismuth is brittle. In Patent Document 4, an attempt is made to improve the brittleness of the joint by adding a trace metal to tin-bismuth solder.

一方で、多数の電極を一括で電気的な接続を取る方法として、従来から異方性導電フィルム、異方性導電ペースト等の異方性導電材料が用いられてきた。異方性導電材料は、ディスプレイのコントロールＩＣの実装やタブ線の接続・実装など多数の配線を一括で実装する用途に用いられ、近年では３０μｍを下回る狭ピッチ接続を可能としてきた。これら異方性導電材料に配合される導電性粒子として、従来からはんだ粒子の使用が検討されている。例えば、特許文献５には、熱硬化性成分と、特定の表面処理を施された複数のはんだ粒子と、を含む導電ペーストが記載されている。On the other hand, anisotropic conductive materials such as anisotropic conductive films and anisotropic conductive pastes have been used as a method for electrically connecting a large number of electrodes at once. Anisotropic conductive materials are used for the purpose of mounting a large number of wirings at once, such as mounting control ICs for displays and connecting/mounting tab wires, and in recent years have made it possible to achieve narrow-pitch connections of less than 30 μm. The use of solder particles as conductive particles to be mixed into these anisotropic conductive materials has been considered for some time. For example, Patent Document 5 describes a conductive paste containing a thermosetting component and multiple solder particles that have been subjected to a specific surface treatment.

特開２００３－７８９４公報JP 2003-7894 A 特開２０１５－１０６６５４公報JP 2015-106654 A 特開２０１４－８４３９５公報JP 2014-84395 A ＷＯ２０１４０６１０８５公報WO2014061085 Publication 特開２０１６－７６４９４号公報JP 2016-76494 A

このように、近年、回路部材の多様化に対応した接続温度の低温化、回路部材の高精細化に伴って接続箇所の微小化、薄型化が進行しており、接続構造体の導通信頼性の確保が難しくなっている。As such, in recent years, connection temperatures have been lowered to accommodate the diversification of circuit components, and connection points have become smaller and thinner as circuit components become more precise, making it difficult to ensure the conductivity reliability of connection structures.

本発明は上記事情に鑑みてなされたものであり、導通信頼性及び絶縁信頼性に優れた接続構造体及びその製造方法を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and aims to provide a connection structure and a manufacturing method thereof that have excellent conductivity reliability and insulation reliability.

本発明の一側面は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、第一の電極と第二の電極とを電気的に接続する接合部を複数有する中間層と、を備え、接合部で接続される前記第一の電極及び前記第二の電極の少なくとも一方が金電極であり、複数の接合部のうち９０％以上が、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む、接続構造体に関する。One aspect of the present invention relates to a connection structure comprising a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and an intermediate layer having a plurality of junctions electrically connecting the first and second electrodes, wherein at least one of the first and second electrodes connected at the junctions is a gold electrode, and 90% or more of the plurality of junctions include a first region containing a tin-gold alloy connecting the first and second electrodes, and a second region containing bismuth that is in contact with the first region.

一態様において、中間層は、第一の回路部材と第二の回路部材との間を封止する絶縁性樹脂層を更に有していてよい。In one embodiment, the intermediate layer may further have an insulating resin layer that seals between the first circuit member and the second circuit member.

本発明の他の一側面は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、異方性導電フィルムと、を準備する準備工程と、第一の回路部材、第二の回路部材及び異方性導電フィルムを、第一の回路部材の第一の電極を有する面と第二の回路部材の第二の電極を有する面とが異方性導電フィルムを介して対向するように配置して、第一の回路部材、異方性導電フィルム及び第二の回路部材がこの順で積層した積層体を得る配置工程と、積層体を厚み方向に押圧した状態で加熱することにより、第一の電極と前記第二の電極とを接合部を介して電気的に接続する接続工程と、を含む、接続構造体の製造方法に関する。この製造方法において、第一の電極及び第二の電極のうち少なくとも一方は金電極であり、異方性導電フィルムは、絶縁性樹脂組成物から構成される絶縁性フィルムと、前記絶縁性フィルム中に配置されている複数のはんだ粒子とを含む。また、はんだ粒子は、スズ－ビスマス合金を含有し、はんだ粒子の平均粒子径は１μｍ～３０μｍであり、はんだ粒子のＣ．Ｖ．値は２０％以下である。また、異方性導電フィルムの縦断面において、はんだ粒子は、隣接するはんだ粒子と離隔した状態で横方向に並ぶように配置されている。また、接続工程で形成される複数の接合部のうち９０％以上は、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む。Another aspect of the present invention relates to a method for producing a connection structure, the method including: a preparation step of preparing a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and an anisotropic conductive film; an arrangement step of arranging the first circuit member, the second circuit member, and the anisotropic conductive film so that the surface of the first circuit member having the first electrode and the surface of the second circuit member having the second electrode face each other via the anisotropic conductive film to obtain a laminate in which the first circuit member, the anisotropic conductive film, and the second circuit member are laminated in this order; and a connection step of heating the laminate while pressing it in the thickness direction to electrically connect the first electrode and the second electrode through a joint. In this production method, at least one of the first electrode and the second electrode is a gold electrode, and the anisotropic conductive film includes an insulating film composed of an insulating resin composition and a plurality of solder particles arranged in the insulating film. The solder particles contain a tin-bismuth alloy, the average particle size of the solder particles is 1 μm to 30 μm, and the C.V. value of the solder particles is 20% or less. In the longitudinal section of the anisotropic conductive film, the solder particles are arranged so as to be aligned in the horizontal direction while being spaced apart from adjacent solder particles. Moreover, 90% or more of the multiple joints formed in the connection step include a first region containing a tin-gold alloy that connects the first electrode and the second electrode, and a second region containing bismuth that is in contact with the first region.

一態様において、はんだ粒子は、複数の凹部を有する基体と、スズ－ビスマス合金を含有するはんだ微粒子と、を準備するはんだ微粒子準備工程と、はんだ微粒子の少なくとも一部を凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部の内部にはんだ粒子を形成する融合工程と、を含む方法により製造されたはんだ粒子であってよい。In one embodiment, the solder particles may be solder particles manufactured by a method including a solder particle preparation step of preparing a substrate having a plurality of recesses and solder particles containing a tin-bismuth alloy, a placement step of placing at least a portion of the solder particles in the recesses, and a fusion step of fusing the solder particles placed in the recesses to form solder particles inside the recesses.

一態様において、はんだ微粒子準備工程で準備されるはんだ微粒子のＣ．Ｖ．値は２０を超えていてよい。In one embodiment, the C.V. value of the solder particles prepared in the solder particle preparation process may be greater than 20.

一態様において、異方性導電フィルムは、はんだ粒子が収容された凹部を複数有する基体の、凹部の開口側に絶縁性樹脂組成物を接触させて、はんだ粒子が転写された第一の樹脂層を得る転写工程と、はんだ粒子が転写された側の第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、を含む方法により製造された異方性導電フィルムであってよい。In one embodiment, the anisotropic conductive film may be an anisotropic conductive film manufactured by a method including a transfer step of contacting an insulating resin composition with the opening side of a recess of a substrate having a plurality of recesses in which solder particles are accommodated, to obtain a first resin layer to which the solder particles are transferred, and a lamination step of forming a second resin layer composed of the insulating resin composition on the surface of the first resin layer on the side to which the solder particles are transferred, to obtain an anisotropic conductive film.

本発明によれば、導通信頼性及び絶縁信頼性に優れた接続構造体及びその製造方法が提供される。 The present invention provides a connection structure having excellent conductivity reliability and insulation reliability, and a method for manufacturing the same.

図１は異方性導電フィルムの第一実施形態を模式的に示す断面図である。FIG. 1 is a cross-sectional view illustrating a first embodiment of an anisotropic conductive film. 図２（ａ）は図１に示すＩＩａ－ＩＩａ線における模式的な横断面図であり、図２（ｂ）は第一実施形態の変形例を模式的に示す横断面図である。FIG. 2(a) is a schematic cross-sectional view taken along line IIa-IIa shown in FIG. 1, and FIG. 2(b) is a schematic cross-sectional view showing a modified example of the first embodiment. 図３（ａ）は基体の一例を模式的に示す平面図であり、図３（ｂ）は図３（ａ）のＩｂ－Ｉｂ線における断面図である。FIG. 3(a) is a plan view showing a schematic diagram of an example of the base body, and FIG. 3(b) is a cross-sectional view taken along line Ib-Ib in FIG. 3(a). 図４（ａ）～（ｈ）は基体の凹部の断面形状の例を模式的に示す断面図である。4(a) to (h) are cross-sectional views that diagrammatically show examples of the cross-sectional shape of a recess in a base body. 図５は基体の凹部にはんだ微粒子が収容された状態を模式的に示す断面図である。FIG. 5 is a cross-sectional view showing a schematic state in which solder particles are contained in the recesses of the base. 図６は基体の凹部にはんだ粒子が形成された状態を模式的に示す断面図である。FIG. 6 is a cross-sectional view showing a schematic state in which solder particles are formed in recesses of a base. 図７（ａ）は図６における凹部の開口部と反対側からはんだ粒子を見た図であり、図７（ｂ）ははんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ≦Ｘ）を示す図である。7(a) is a diagram showing a solder particle viewed from the opposite side to the opening of the recess in FIG. 6, and FIG. 7(b) is a diagram showing the distances X and Y (where Y≦X) between opposing sides of a rectangle circumscribing a projected image of the solder particle when the rectangle is created by two pairs of parallel lines. 図８（ａ）～（ｃ）は第一実施形態に係る異方性導電フィルムの製造過程の一例を模式的に示す断面図である。8A to 8C are cross-sectional views that diagrammatically show an example of a manufacturing process for the anisotropic conductive film according to the first embodiment. 図９（ａ）～（ｃ）は第二実施形態に係る異方性導電フィルムの製造過程の一例を模式的に示す断面図である。9A to 9C are cross-sectional views that diagrammatically show an example of a manufacturing process for the anisotropic conductive film according to the second embodiment. 図１０（ａ）及び図１０（ｂ）は異方性導電フィルムの製造過程の他の一例を模式的に示す断面図である。10A and 10B are cross-sectional views that diagrammatically show another example of the process for producing an anisotropic conductive film. 図１１は接続構造体の一部を拡大して示す図であって、第一の電極と第二の電極とが接合部によって電気的に接続された状態を模式的に示す断面図である。FIG. 11 is an enlarged view of a portion of the connection structure, and is a cross-sectional view that typically illustrates a state in which a first electrode and a second electrode are electrically connected by a joint. 図１２（ａ）及び図１２（ｂ）は、本発明に係る接続構造体の製造過程の第一の例を模式的に示す断面図である。12(a) and 12(b) are cross-sectional views that diagrammatically show a first example of a process for producing a connection structure according to the present invention. 図１３（ａ）及び図１３（ｂ）は、本発明に係る接続構造体の製造過程の第二の例を模式的に示す断面図である。13(a) and 13(b) are cross-sectional views that typically show a second example of the process for producing a connection structure according to the present invention. 図１４（ａ）及び図１４（ｂ）は、本発明に係る接続構造体の製造過程の第三の例を模式的に示す断面図である。14(a) and 14(b) are cross-sectional views that typically show a third example of the process for producing a connection structure according to the present invention. 図１５（ａ）、図１５（ｂ）、図１５（ｃ）及び図１５（ｄ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す断面図である。15(a), 15(b), 15(c) and 15(d) are cross-sectional views each showing a schematic example of a bonding portion including a first region and a second region. 図１６（ａ）、図１６（ｂ）、図１６（ｃ）及び図１６（ｄ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す断面図である。16(a), 16(b), 16(c) and 16(d) are cross-sectional views each showing a schematic example of a bonding portion including a first region and a second region. 図１７（ａ）、図１７（ｂ）、図１７（ｃ）、図１７（ｄ）、図１７（ｅ）及び図１７（ｆ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す平面図である。Figures 17(a), 17(b), 17(c), 17(d), 17(e) and 17(f) are plan views each showing a schematic example of a bonding portion including a first region and a second region. 図１８（ａ）、図１８（ｂ）及び図１８（ｃ）は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す断面図である。18(a), 18(b), and 18(c) are cross-sectional views each showing a schematic example of a joint portion not including a first region and a second region. 図１９（ａ）、図１９（ｂ）、図１９（ｃ）及び図１９（ｄ）は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す断面図である。19(a), 19(b), 19(c) and 19(d) are cross-sectional views each showing a schematic example of a bonding portion not including a first region and a second region. 図２０は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第一の例を模式的に示す平面図である。FIG. 20 is a plan view showing a first example of the relationship between the positions of the solder particles on the anisotropic conductive film and the positions of the bumps (electrodes) before pressing and heating. 図２１は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第二の例を模式的に示す平面図である。FIG. 21 is a plan view showing a second example of the relationship between the positions of the solder particles on the anisotropic conductive film and the positions of the bumps (electrodes) before pressing and heating. 図２２は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第三の例を模式的に示す平面図である。FIG. 22 is a plan view showing a third example of the relationship between the positions of the solder particles on the anisotropic conductive film and the positions of the bumps (electrodes) before pressing and heating. 図２３は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）との関係の第四の例を模式的に示す平面図である。FIG. 23 is a plan view showing a fourth example of the relationship between the positions of the solder particles on the anisotropic conductive film and the bumps (electrodes) before pressing and heating. 図２４は基体の凹部の断面形状の他の例を模式的に示す断面図である。FIG. 24 is a cross-sectional view showing a schematic example of another example of the cross-sectional shape of the recess of the base body. 図２５（ａ）は、押圧及び加熱がなされた後の接続構造体の断面像であり、図２５（ｂ）は、当該断面像のＥＤＸ分析結果を示す図である。FIG. 25(a) is a cross-sectional image of the connection structure after pressing and heating, and FIG. 25(b) is a diagram showing the results of EDX analysis of the cross-sectional image.

以下、本発明の実施形態について説明する。本発明は以下の実施形態に限定されるものではない。なお、以下で例示する材料は、特に断らない限り、一種単独で用いてもよく、二種以上を組み合わせて用いてもよい。組成物中の各成分の含有量は、組成物中に各成分に該当する物質が複数存在する場合、特に断らない限り、組成物中に存在する当該複数の物質の合計量を意味する。「～」を用いて示された数値範囲は、「～」の前後に記載される数値をそれぞれ最小値及び最大値として含む範囲を示す。本明細書中に段階的に記載されている数値範囲において、ある段階の数値範囲の上限値又は下限値は、他の段階の数値範囲の上限値又は下限値に置き換えてもよい。本明細書中に記載されている数値範囲において、その数値範囲の上限値又は下限値は、実施例に示されている値に置き換えてもよい。 The following describes an embodiment of the present invention. The present invention is not limited to the following embodiment. The materials exemplified below may be used alone or in combination of two or more types, unless otherwise specified. When a plurality of substances corresponding to each component are present in the composition, the content of each component in the composition means the total amount of the plurality of substances present in the composition, unless otherwise specified. A numerical range indicated using "~" indicates a range including the numerical values described before and after "~" as the minimum and maximum values, respectively. In the numerical ranges described in stages in this specification, the upper or lower limit of a numerical range of a certain stage may be replaced by the upper or lower limit of a numerical range of another stage. In the numerical ranges described in this specification, the upper or lower limit of the numerical range may be replaced by the values shown in the examples.

本実施形態に係る接続構造体は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、第一の電極と前記第二の電極とを電気的に接続する接合部を複数有する中間層と、を備える。また、接合部で接続される第一の電極及び第二の電極の少なくとも一方が金電極であり、複数の接合部のうち９０％以上は、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含むものとなっている。The connection structure according to this embodiment includes a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and an intermediate layer having a plurality of junctions that electrically connect the first electrodes and the second electrodes. At least one of the first and second electrodes connected at the junctions is a gold electrode, and 90% or more of the plurality of junctions include a first region containing a tin-gold alloy that connects the first electrode and the second electrode, and a second region containing bismuth that contacts the first region.

本実施形態に係る接続構造体は、第一の電極と第二の電極との間を連結する第一の領域と、前記第一の領域に接する第二の領域とを含む接合部を備えている。当該接合部は、第一の領域がスズ－金合金を含んで一体化され、更に第二の領域が補強部として機能するため、クラックが生じにくい。また、当該接合部は、第一の領域が融点の高いスズ－金合金を含むため、接合部の再溶融が十分に抑制されている。本実施形態に係る接続構造体は、接合部の９０％以上が、このような第一の領域及び第二の領域を含むものであることから、接合部へのクラックの発生及び接合部の溶融が十分に抑制され、導通信頼性に優れる。また、本実施形態に係る接続構造体は、接合部の溶融が十分に抑制されていることから、二次実装等への適用が容易であり、また、高温環境下での使用にも適する。The connection structure according to the present embodiment includes a joint including a first region connecting the first electrode and the second electrode, and a second region in contact with the first region. The first region of the joint is integrated with a tin-gold alloy, and the second region functions as a reinforcing portion, so that cracks are unlikely to occur. In addition, the first region of the joint contains a tin-gold alloy with a high melting point, so that remelting of the joint is sufficiently suppressed. Since 90% or more of the joints of the connection structure according to the present embodiment include such a first region and a second region, the occurrence of cracks in the joint and melting of the joint are sufficiently suppressed, and the connection structure according to the present embodiment has excellent electrical reliability. In addition, since melting of the joint is sufficiently suppressed, the connection structure according to the present embodiment is easily applicable to secondary mounting, etc., and is also suitable for use in high-temperature environments.

中間層は、第一の回路部材と第二の回路部材との間を封止する絶縁性樹脂層を更に有していてもよい。絶縁性樹脂層は、後述の異方性導電フィルムの絶縁性フィルムにより形成されたものであってよい。The intermediate layer may further include an insulating resin layer that seals between the first circuit member and the second circuit member. The insulating resin layer may be formed from an insulating film of an anisotropic conductive film described below.

本実施形態において、接続構造体中の接合部のうち、第一の領域及び第二の領域を含む上記接合部の割合は、８０％以上であり、好ましくは８５％以上であり、より好ましくは９０％以上であり、１００％であってもよい。In this embodiment, the proportion of the joints in the connection structure that include the first region and the second region is 80% or more, preferably 85% or more, more preferably 90% or more, and may be 100%.

接続構造体の接合部の大半を第一の領域及び第二の領域を含むものとするためには、各接合部の形成に供されるはんだ粒子が均一であることが望ましい。また、接続構造体の接合部の大半を第一の領域及び第二の領域を含むものとするためには、はんだ粒子の周囲に絶縁性樹脂組成物が配置されており、はんだ粒子の溶融時に、溶融したはんだが第一の電極及び第二の電極の間に十分な時間保持されることが望ましい。これらの観点から、本実施形態に係る接続構造体は、以下に示す異方性導電フィルムを用いて第一の回路部材と第二の回路部材とを接合したものであることが好ましい。In order for the majority of the joints of the connection structure to include the first and second regions, it is desirable that the solder particles used to form each joint be uniform. Also, in order for the majority of the joints of the connection structure to include the first and second regions, it is desirable that an insulating resin composition is disposed around the solder particles, and that when the solder particles melt, the molten solder is held between the first and second electrodes for a sufficient period of time. From these viewpoints, the connection structure according to this embodiment is preferably one in which a first circuit member and a second circuit member are joined using an anisotropic conductive film as shown below.

以下、図面を参照しつつ、接続構造体の製造に有用な異方性導電フィルム及びその製造方法、並びに、接続構造体及びその製造方法の好適な形態について説明する。 Below, with reference to the drawings, we will explain preferred forms of an anisotropic conductive film and its manufacturing method that are useful for manufacturing a connection structure, as well as a connection structure and its manufacturing method.

＜異方性導電フィルム＞
図１に示す第一実施形態に係る異方性導電フィルム１０は、絶縁性樹脂組成物からなる絶縁性フィルム２と、絶縁性フィルム２中に配置されている複数のはんだ粒子１とによって構成されている。異方性導電フィルム１０の所定の縦断面において、一個のはんだ粒子１は隣接する一個のはんだ粒子１と離隔した状態で横方向（図１における左右方向）に並ぶように配置されている。換言すると、異方性導電フィルム１０は、その縦断面において、複数のはんだ粒子１が横方向に列をなしている中央領域１０ａと、はんだ粒子１が実質的に存在しない表面側領域１０ｂ，１０ｃとによって構成されている。 <Anisotropic Conductive Film>
The anisotropic conductive film 10 according to the first embodiment shown in Fig. 1 is composed of an insulating film 2 made of an insulating resin composition, and a plurality of solder particles 1 disposed in the insulating film 2. In a given longitudinal section of the anisotropic conductive film 10, each solder particle 1 is disposed so as to be aligned in the lateral direction (the left-right direction in Fig. 1) while being spaced apart from an adjacent solder particle 1. In other words, in its longitudinal section, the anisotropic conductive film 10 is composed of a central region 10a in which a plurality of solder particles 1 are aligned in the lateral direction, and surface side regions 10b and 10c in which the solder particles 1 are substantially absent.

図２（ａ）は図１に示すＩＩａ－ＩＩａ線における模式的な横断面図である。図２に示されるとおり、異方性導電フィルム１０の横断面において、はんだ粒子１が規則的に配置されている。図２（ａ）に示されたとおり、はんだ粒子１は異方性導電フィルム１０の全体の領域に対して規則的且つほぼ均等の間隔で配置されていてもよく、図２（ｂ）に示された変形例のように、異方性導電フィルム１０の横断面において、複数のはんだ粒子１が規則的に配置されている領域１０ｄと、はんだ粒子１が実質的に存在しない領域１０ｅとが規則的に形成されるように、はんだ粒子１を配置してもよい。例えば、接続すべき電極の形状、サイズ及びパターン等に応じ、はんだ粒子１の位置及び個数等を設定すればよい。2(a) is a schematic cross-sectional view taken along line IIa-IIa in FIG. 1. As shown in FIG. 2, the solder particles 1 are regularly arranged in the cross-section of the anisotropic conductive film 10. As shown in FIG. 2(a), the solder particles 1 may be regularly and substantially evenly spaced across the entire area of the anisotropic conductive film 10, or, as in the modified example shown in FIG. 2(b), the solder particles 1 may be arranged so that a region 10d in which a plurality of solder particles 1 are regularly arranged and a region 10e in which the solder particles 1 are substantially absent are regularly formed in the cross-section of the anisotropic conductive film 10. For example, the position and number of the solder particles 1 may be set according to the shape, size, pattern, etc. of the electrodes to be connected.

（はんだ粒子）
はんだ粒子１の平均粒子径は、例えば３０μｍ以下であり、好ましくは２５μｍ以下、より好ましくは２０μｍ以下、さらに好ましくは１５μｍ以下である。また、はんだ粒子１の平均粒子径は、例えば１μｍ以上であり、好ましくは２μｍ以上、より好ましくは３μｍ以上、さらに好ましくは５μｍ以上である。 (solder particles)
The average particle diameter of the solder particles 1 is, for example, 30 μm or less, preferably 25 μm or less, more preferably 20 μm or less, and even more preferably 15 μm or less. The average particle diameter of the solder particles 1 is, for example, 1 μm or more, preferably 2 μm or more, more preferably 3 μm or more, and even more preferably 5 μm or more.

はんだ粒子１の平均粒子径は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザ回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。The average particle diameter of the solder particles 1 can be measured using various methods suited to the size. For example, methods such as dynamic light scattering, laser diffraction, centrifugal sedimentation, electrical sensing zone method, and resonance mass measurement method can be used. Furthermore, a method can be used to measure the particle size from images obtained by an optical microscope, electron microscope, etc. Specific devices include a flow type particle image analyzer, a microtrack, a Coulter counter, etc.

はんだ粒子１のＣ．Ｖ．値は、より優れた導電信頼性及び絶縁信頼性を実現できる観点から、好ましくは２０％以下、より好ましくは１０％以下、更に好ましくは７％以下である。また、はんだ粒子１のＣ．Ｖ．値の下限は特に限定されない。例えば、はんだ粒子１のＣ．Ｖ．値は１％以上であってよく、２％以上であってもよい。The C.V. value of the solder particle 1 is preferably 20% or less, more preferably 10% or less, and even more preferably 7% or less, from the viewpoint of achieving better conductive reliability and insulating reliability. The lower limit of the C.V. value of the solder particle 1 is not particularly limited. For example, the C.V. value of the solder particle 1 may be 1% or more, or may be 2% or more.

はんだ粒子１のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径で割った値に１００を掛けることで算出される。The C.V. value of solder particle 1 is calculated by dividing the standard deviation of the particle diameter measured by the above-mentioned method by the average particle diameter and multiplying the result by 100.

図７（ａ）に示すように、はんだ粒子１は、表面の一部に平面部１１が形成されていてよく、このとき当該平面部１１以外の表面は、球冠状であることが好ましい。すなわち、はんだ粒子１は、平面部１１と、球冠状の曲面部と、を有するものであってよい。はんだ粒子１の直径Ｂに対する平面部１１の直径Ａの比（Ａ／Ｂ）は、例えば０．０１超１．０未満（０．０１＜Ａ／Ｂ＜１．０）であってよく、０．１～０．９であってもよい。はんだ粒子１が平面部１１を有することで、接続時の加圧による位置ずれが生じ難くなり、より優れた導電信頼性及び絶縁信頼性を実現できる。 As shown in FIG. 7(a), the solder particle 1 may have a flat portion 11 formed on a portion of its surface, and in this case, the surface other than the flat portion 11 is preferably spherical crown-shaped. That is, the solder particle 1 may have a flat portion 11 and a spherical crown-shaped curved portion. The ratio (A/B) of the diameter A of the flat portion 11 to the diameter B of the solder particle 1 may be, for example, greater than 0.01 and less than 1.0 (0.01<A/B<1.0), or may be 0.1 to 0.9. When the solder particle 1 has the flat portion 11, misalignment due to pressure applied during connection is less likely to occur, and better conductive and insulating reliability can be achieved.

はんだ粒子１の投影像に外接する四角形を二対の平行線により作成した場合において、対向する辺間の距離をＸ及びＹ（但しＹ＜Ｘ）としたときに、Ｘに対するＹの比（Ｙ／Ｘ）は、０．８超１．０未満（０．８＜Ｙ／Ｘ＜１．０）であってよく、０．９以上１．０未満であってもよい。このようなはんだ粒子１はより真球に近い粒子ということができる。後述の製造方法によれば、このようなはんだ粒子１を容易に得ることができる。はんだ粒子１が真球に近いことで、例えば、対向する複数の電極間をはんだ粒子１を介して電気的に接続させるときに、はんだ粒子１と電極間接触にムラが生じ難く、安定した接続が得られる傾向がある。また、はんだ粒子１を樹脂組成物中に分散した導電性フィルムや樹脂を作製したとき、高い分散性が得られ、製造時の分散安定性が得られる傾向がある。さらに、はんだ粒子１を樹脂組成物に分散したフィルムやペーストを、電極間の接続に用いる場合、樹脂中ではんだ粒子１が回転しても、はんだ粒子１が球体形状であれば、投影像で見たとき、はんだ粒子１同士の投影面積が近い。そのため、電極同士を接続する際にばらつきの少ない、安定した電気接続を得易い傾向がある。When a rectangle circumscribing a projected image of the solder particle 1 is created by two pairs of parallel lines, and the distance between the opposing sides is X and Y (where Y<X), the ratio of Y to X (Y/X) may be greater than 0.8 and less than 1.0 (0.8<Y/X<1.0), or may be 0.9 or more and less than 1.0. Such solder particles 1 can be said to be particles closer to a true sphere. According to the manufacturing method described below, such solder particles 1 can be easily obtained. Since the solder particles 1 are closer to a true sphere, for example, when a plurality of opposing electrodes are electrically connected via the solder particles 1, there is a tendency for unevenness to occur in the contact between the solder particles 1 and the electrodes, and a stable connection is obtained. In addition, when a conductive film or resin in which the solder particles 1 are dispersed in a resin composition is produced, high dispersibility is obtained, and dispersion stability during production tends to be obtained. Furthermore, when a film or paste in which the solder particles 1 are dispersed in a resin composition is used to connect electrodes, even if the solder particles 1 rotate in the resin, if the solder particles 1 are spherical, the projected areas of the solder particles 1 are close to each other when viewed in a projected image. Therefore, there is a tendency to easily obtain a stable electrical connection with little variation when connecting electrodes.

図７（ｂ）は、はんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ＜Ｘ）を示す図である。例えば、任意の粒子を走査型電子顕微鏡により観察して投影像を得る。得られた投影像に対し二対の平行線を描画し、一対の平行線は平行線の距離が最小となる位置に、もう一対の平行線は平行線の距離が最大となる位置に配し、その粒子のＹ／Ｘを求める。この作業を３００個のはんだ粒子に対して行って平均値を算出し、はんだ粒子のＹ／Ｘとする。 Figure 7 (b) is a diagram showing the distances X and Y (where Y<X) between opposing sides when a rectangle circumscribing the projected image of a solder particle is created with two pairs of parallel lines. For example, an arbitrary particle is observed with a scanning electron microscope to obtain a projected image. Two pairs of parallel lines are drawn on the obtained projected image, one pair of parallel lines is placed at a position where the distance between the parallel lines is smallest and the other pair of parallel lines is placed at a position where the distance between the parallel lines is largest, and the Y/X of the particle is determined. This process is performed for 300 solder particles and the average value is calculated to obtain the Y/X of the solder particle.

はんだ粒子１は、スズ－ビスマス合金（Ｓｎ－Ｂｉ合金）を含む。スズ－ビスマス合金の具体例としては、下記の例が挙げられる。
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ（Ｓｎ７２質量％、Ｂｉ２８質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％ 融点１３９℃） The solder particles 1 contain a tin-bismuth alloy (Sn--Bi alloy). Specific examples of the tin-bismuth alloy include the following.
・Sn-Bi (Sn 43% by mass, Bi 57% by mass, melting point 138°C)
・Sn-Bi (Sn 72% by mass, Bi 28% by mass, melting point 138°C)
・Sn-Bi-Ag (Sn 42% by mass, Bi 57% by mass, Ag 1% by mass, melting point 139°C)

はんだ粒子１は、Ｓｎ及びＢｉ以外の他の金属を更に含んでいてもよい。他の金属としては、例えばＡｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ、Ｂ、Ｇａ、Ａｓ、Ｓｂ、Ｔｅ、Ｇｅ、Ｓｉ、Ａｌ等が挙げられる。はんだ粒子１の他の金属の含有率は、例えば１０質量％以下であり、好ましくは５質量％以下、より好ましくは３質量％以下である。The solder particles 1 may further contain other metals besides Sn and Bi. Examples of the other metals include Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P, B, Ga, As, Sb, Te, Ge, Si, and Al. The content of the other metals in the solder particles 1 is, for example, 10% by mass or less, preferably 5% by mass or less, and more preferably 3% by mass or less.

（絶縁性フィルム）
絶縁性フィルム２を構成する絶縁性樹脂組成物は、熱硬化性化合物を含んでもよい。熱硬化性化合物としては、オキセタン化合物、エポキシ化合物、エピスルフィド化合物、（メタ）アクリル化合物、フェノール化合物、アミノ化合物、不飽和ポリエステル化合物、ポリウレタン化合物、シリコーン化合物及びポリイミド化合物等が挙げられる。なかでも、絶縁樹脂の硬化性及び粘度をより一層良好にし、接続信頼性をより一層高める観点から、エポキシ化合物が好ましい。 (Insulating film)
The insulating resin composition constituting the insulating film 2 may contain a thermosetting compound. Examples of the thermosetting compound include oxetane compounds, epoxy compounds, episulfide compounds, (meth)acrylic compounds, phenol compounds, amino compounds, unsaturated polyester compounds, polyurethane compounds, silicone compounds, and polyimide compounds. Among them, epoxy compounds are preferred from the viewpoint of further improving the curability and viscosity of the insulating resin and further increasing the connection reliability.

絶縁性樹脂組成物は熱硬化剤をさらに含んでもよい。熱硬化剤としては、イミダゾール硬化剤、アミン硬化剤、フェノール硬化剤、ポリチオール硬化剤、酸無水物、熱カチオン開始剤及び熱ラジカル発生剤等が挙げられる。これらは一種を単独で用いてもよく、二種以上を併用してもよい。これらのうち、低温で速やかに硬化可能である点で、イミダゾール硬化剤、ポリチオール硬化剤又はアミン硬化剤が好ましい。また、熱硬化性化合物と熱硬化剤とを混合したときに保存安定性が高くなるので、潜在性の硬化剤が好ましい。潜在性の硬化剤は、潜在性イミダゾール硬化剤、潜在性ポリチオール硬化剤又は潜在性アミン硬化剤であることが好ましい。なお、上記熱硬化剤は、ポリウレタン樹脂又はポリエステル樹脂等の高分子物質で被覆されていてもよい。The insulating resin composition may further contain a heat curing agent. Examples of heat curing agents include imidazole curing agents, amine curing agents, phenol curing agents, polythiol curing agents, acid anhydrides, thermal cationic initiators, and thermal radical generators. These may be used alone or in combination of two or more. Among these, imidazole curing agents, polythiol curing agents, and amine curing agents are preferred because they can be cured quickly at low temperatures. In addition, latent curing agents are preferred because they have high storage stability when mixed with a thermosetting compound and a heat curing agent. The latent curing agent is preferably a latent imidazole curing agent, a latent polythiol curing agent, or a latent amine curing agent. The heat curing agent may be coated with a polymeric substance such as a polyurethane resin or a polyester resin.

上記イミダゾール硬化剤としては、特に限定されず、２－メチルイミダゾール、２－エチル－４－メチルイミダゾール、１－シアノエチル－２－フェニルイミダゾール、１－シアノエチル－２－フェニルイミダゾリウムトリメリテート、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン及び２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジンイソシアヌル酸付加物等が挙げられる。The imidazole curing agent is not particularly limited, and examples thereof include 2-methylimidazole, 2-ethyl-4-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, and 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct.

上記ポリチオール硬化剤としては、特に限定されず、トリメチロールプロパントリス－３－メルカプトプロピオネート、ペンタエリスリトールテトラキス－３－メルカプトプロピオネート及びジペンタエリスリトールヘキサ－３－メルカプトプロピオネート等が挙げられる。ポリチオール硬化剤の溶解度パラメーターは、好ましくは９．５以上、好ましくは１２以下である。上記溶解度パラメーターは、Ｆｅｄｏｒｓ法にて計算される。例えば、トリメチロールプロパントリス－３－メルカプトプロピオネートの溶解度パラメーターは９．６、ジペンタエリスリトールヘキサ－３－メルカプトプロピオネートの溶解度パラメーターは１１．４である。The polythiol curing agent is not particularly limited, and examples thereof include trimethylolpropane tris-3-mercaptopropionate, pentaerythritol tetrakis-3-mercaptopropionate, and dipentaerythritol hexa-3-mercaptopropionate. The solubility parameter of the polythiol curing agent is preferably 9.5 or more, and preferably 12 or less. The solubility parameter is calculated by the Fedors method. For example, the solubility parameter of trimethylolpropane tris-3-mercaptopropionate is 9.6, and the solubility parameter of dipentaerythritol hexa-3-mercaptopropionate is 11.4.

上記アミン硬化剤としては、特に限定されず、ヘキサメチレンジアミン、オクタメチレンジアミン、デカメチレンジアミン、３，９－ビス（３－アミノプロピル）－２，４，８，１０－テトラスピロ［５．５］ウンデカン、ビス（４－アミノシクロヘキシル）メタン、メタフェニレンジアミン及びジアミノジフェニルスルホン等が挙げられる。 The above amine curing agents are not particularly limited, and examples thereof include hexamethylenediamine, octamethylenediamine, decamethylenediamine, 3,9-bis(3-aminopropyl)-2,4,8,10-tetraspiro[5.5]undecane, bis(4-aminocyclohexyl)methane, metaphenylenediamine, and diaminodiphenylsulfone.

上記熱カチオン硬化剤としては、ヨードニウム系カチオン硬化剤、オキソニウム系カチオン硬化剤及びスルホニウム系カチオン硬化剤等が挙げられる。上記ヨードニウム系カチオン硬化剤としては、ビス（４－ｔｅｒｔ－ブチルフェニル）ヨードニウムヘキサフルオロホスファート等が挙げられる。上記オキソニウム系カチオン硬化剤としては、トリメチルオキソニウムテトラフルオロボラート等が挙げられる。上記スルホニウム系カチオン硬化剤としては、トリ－ｐ－トリルスルホニウムヘキサフルオロホスファート等が挙げられる。 The above-mentioned thermal cationic curing agents include iodonium cationic curing agents, oxonium cationic curing agents, and sulfonium cationic curing agents. The above-mentioned iodonium cationic curing agents include bis(4-tert-butylphenyl)iodonium hexafluorophosphate. The above-mentioned oxonium cationic curing agents include trimethyloxonium tetrafluoroborate. The above-mentioned sulfonium cationic curing agents include tri-p-tolylsulfonium hexafluorophosphate.

上記熱ラジカル発生剤としては、特に限定されず、アゾ化合物及び有機過酸化物等が挙げられる。上記アゾ化合物としては、アゾビスイゾブチロニトリル（ＡＩＢＮ）等が挙げられる。上記有機過酸化物としては、ジ－ｔｅｒｔ－ブチルペルオキシド及びメチルエチルケトンペルオキシド等が挙げられる。The thermal radical generator is not particularly limited, and examples thereof include azo compounds and organic peroxides. Examples of the azo compounds include azobisisobutyronitrile (AIBN). Examples of the organic peroxides include di-tert-butyl peroxide and methyl ethyl ketone peroxide.

（フラックス）
異方性導電フィルム１０は、フラックスを含むことが好ましい。具体的には、異方性導電フィルム１０を構成する絶縁性樹脂組成物がフラックスを含有するとともに、はんだ粒子１の表面をフラックスが覆っていることが好ましい。フラックスは、はんだ表面の酸化物を溶融して、はんだ粒子同士の融着性及び電極へのはんだの濡れ性を向上させる。 (flux)
The anisotropic conductive film 10 preferably contains a flux. Specifically, it is preferable that the insulating resin composition constituting the anisotropic conductive film 10 contains a flux, and that the flux covers the surfaces of the solder particles 1. The flux melts oxides on the solder surface, improving the fusion between the solder particles and the wettability of the solder to the electrodes.

フラックスとしては、はんだ接合等に一般的に用いられているものを使用できる。具体例としては、塩化亜鉛、塩化亜鉛と無機ハロゲン化物との混合物、塩化亜鉛と無機酸との混合物、溶融塩、リン酸、リン酸の誘導体、有機ハロゲン化物、ヒドラジン、有機酸及び松脂等が挙げられる。これらは一種を単独で用いてもよく、二種以上を併用してもよい。 Fluxes that are generally used for solder joints and the like can be used. Specific examples include zinc chloride, a mixture of zinc chloride and an inorganic halide, a mixture of zinc chloride and an inorganic acid, molten salts, phosphoric acid, derivatives of phosphoric acid, organic halides, hydrazine, organic acids, and rosin. These may be used alone or in combination of two or more.

溶融塩としては、塩化アンモニウム等が挙げられる。有機酸としては、乳酸、クエン酸、ステアリン酸、グルタミン酸及びグルタル酸等が挙げられる。松脂としては、活性化松脂及び非活性化松脂等が挙げられる。松脂はアビエチン酸を主成分とするロジン類である。フラックスとして、カルボキシル基を二個以上有する有機酸又は松脂を使用することにより、電極間の導通信頼性がより一層高くなるという効果が奏される。 Examples of molten salts include ammonium chloride. Examples of organic acids include lactic acid, citric acid, stearic acid, glutamic acid, and glutaric acid. Examples of rosin include activated rosin and non-activated rosin. Rosin is a rosin whose main component is abietic acid. By using an organic acid or rosin having two or more carboxyl groups as the flux, the effect of further increasing the reliability of conduction between electrodes is achieved.

フラックスの融点は、好ましくは５０℃以上であり、より好ましくは７０℃以上であり、さらに好ましくは８０℃以上である。フラックスの融点は、好ましくは２００℃以下であり、より好ましくは１６０℃以下であり、さらに好ましくは１５０℃以下であり、特に好ましくは１４０℃以下である。上記フラックスの融点が上記下限以上及び上記上限以下であると、フラックス効果がより一層効果的に発揮され、はんだ粒子が電極上により一層効率的に配置される。フラックスの融点の範囲は、８０～１９０℃であることが好ましく、８０～１４０℃以下であることがより好ましい。The melting point of the flux is preferably 50°C or higher, more preferably 70°C or higher, and even more preferably 80°C or higher. The melting point of the flux is preferably 200°C or lower, more preferably 160°C or lower, even more preferably 150°C or lower, and particularly preferably 140°C or lower. When the melting point of the flux is above the lower limit and below the upper limit, the flux effect is more effectively exerted, and the solder particles are more efficiently arranged on the electrodes. The melting point of the flux is preferably in the range of 80 to 190°C, and more preferably 80 to 140°C or lower.

融点が８０～１９０℃の範囲にあるフラックスとしては、コハク酸（融点１８６℃）、グルタル酸（融点９６℃）、アジピン酸（融点１５２℃）、ピメリン酸（融点１０４℃）、スベリン酸（融点１４２℃）等のジカルボン酸、安息香酸（融点１２２℃）、リンゴ酸（融点１３０℃）等が挙げられる。Fluxes with melting points in the range of 80 to 190°C include dicarboxylic acids such as succinic acid (melting point 186°C), glutaric acid (melting point 96°C), adipic acid (melting point 152°C), pimelic acid (melting point 104°C), and suberic acid (melting point 142°C), as well as benzoic acid (melting point 122°C) and malic acid (melting point 130°C).

＜異方性導電フィルムの製造方法＞
異方性導電フィルム１０の製造方法は、複数の凹部を有する基体とはんだ微粒子とを準備するはんだ微粒子準備工程と、はんだ微粒子の少なくとも一部を凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部の内部にはんだ粒子を形成する融合工程と、はんだ粒子が凹部に収容されている基体の、凹部の開口側に絶縁性樹脂組成物を接触させて、はんだ粒子が転写された第一の樹脂層を得る転写工程と、はんだ粒子が転写された側の第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、を含む。 <Method of manufacturing anisotropic conductive film>
The manufacturing method of the anisotropic conductive film 10 includes a solder particle preparation step of preparing a substrate having a plurality of recesses and solder particles, a storage step of accommodating at least some of the solder particles in the recesses, a fusion step of fusing the solder particles contained in the recesses to form solder particles inside the recesses, a transfer step of contacting an insulating resin composition with the opening side of the recesses of the substrate in which the solder particles are accommodated in the recesses to obtain a first resin layer to which the solder particles are transferred, and a lamination step of forming a second resin layer composed of an insulating resin composition on the surface of the first resin layer on the side to which the solder particles are transferred, thereby obtaining an anisotropic conductive film.

図３～８を参照しながら、第一実施形態に係る異方性導電フィルム１０の製造方法について説明する。 With reference to Figures 3 to 8, a manufacturing method for the anisotropic conductive film 10 according to the first embodiment will be described.

まず、はんだ微粒子と、はんだ微粒子を収容するための基体６０を準備する。図３（ａ）は基体６０の一例を模式的に示す平面図であり、図３（ｂ）は図３（ａ）に示すＩｂ－Ｉｂ線における断面図である。図３（ａ）に示す基体６０は、複数の凹部６２を有している。複数の凹部６２は所定のパターンで規則的に配置されていてよい。この場合、後述の転写工程に基体６０をそのまま用いることができる。First, solder particles and a base 60 for housing the solder particles are prepared. FIG. 3(a) is a plan view showing a schematic example of the base 60, and FIG. 3(b) is a cross-sectional view taken along line Ib-Ib shown in FIG. 3(a). The base 60 shown in FIG. 3(a) has a plurality of recesses 62. The recesses 62 may be regularly arranged in a predetermined pattern. In this case, the base 60 can be used as is in the transfer process described below.

基体６０の凹部６２は、凹部６２の底部６２ａ側から基体６０の表面６０ａ側に向けて開口面積が拡大するテーパ状に形成されていることが好ましい。すなわち、図３（ａ）及び図３（ｂ）に示すように、凹部６２の底部６２ａの幅（図３（ａ）及び図３（ｂ）における幅ａ）は、凹部６２の表面６０ａにおける開口の幅（図３（ａ）及び図３（ｂ）における幅ｂ）よりも狭いことが好ましい。そして、凹部６２のサイズ（幅ａ、幅ｂ、容積、テーパ角度及び深さ等）は、目的とするはんだ粒子のサイズに応じて設定すればよい。The recess 62 of the base 60 is preferably formed in a tapered shape with an opening area expanding from the bottom 62a of the recess 62 toward the surface 60a of the base 60. That is, as shown in Figures 3(a) and 3(b), the width of the bottom 62a of the recess 62 (width a in Figures 3(a) and 3(b)) is preferably narrower than the width of the opening on the surface 60a of the recess 62 (width b in Figures 3(a) and 3(b)). The size of the recess 62 (width a, width b, volume, taper angle, depth, etc.) may be set according to the size of the desired solder particles.

なお、凹部６２の形状は図３（ａ）及び図３（ｂ）に示す形状以外の形状であってもよい。例えば、凹部６２の表面６０ａにおける開口の形状は、図３（ａ）に示すような円形以外に、楕円形、三角形、四角形、多角形等であってよい。The shape of the recess 62 may be a shape other than that shown in Figures 3(a) and 3(b). For example, the shape of the opening in the surface 60a of the recess 62 may be an ellipse, a triangle, a rectangle, a polygon, etc., other than the circle shown in Figure 3(a).

また、表面６０ａに対して垂直な断面における凹部６２の形状は、例えば、図４に示すような形状であってよい。図４（ａ）～（ｈ）は、基体が有する凹部の断面形状の例を模式的に示す断面図である。図４（ａ）～（ｈ）に示すいずれの断面形状も、凹部６２の表面６０ａにおける開口の幅（幅ｂ）が、断面形状における最大幅となっている。これにより、凹部６２内に形成されたはんだ粒子が取り出しやすくなり、作業性が向上する。また、表面６０ａに対して垂直な断面における凹部６２の形状は、例えば、図２４に示すように、図４（ａ）～（ｈ）に示す断面形状における壁面を傾斜させた形状であってもよい。図２４は、図４（ｂ）に示す断面形状の壁面を傾斜させた形状ということができる。 The shape of the recess 62 in a cross section perpendicular to the surface 60a may be, for example, a shape as shown in FIG. 4. FIGS. 4(a) to (h) are cross-sectional views showing examples of cross-sectional shapes of the recesses of the base. In all of the cross-sectional shapes shown in FIGS. 4(a) to (h), the width (width b) of the opening in the surface 60a of the recess 62 is the maximum width in the cross-sectional shape. This makes it easier to remove the solder particles formed in the recess 62, improving workability. The shape of the recess 62 in a cross section perpendicular to the surface 60a may be, for example, a shape in which the wall surfaces in the cross-sectional shapes shown in FIGS. 4(a) to (h) are inclined, as shown in FIG. 24. FIG. 24 can be said to be a shape in which the wall surfaces in the cross-sectional shape shown in FIG. 4(b) are inclined.

基体６０を構成する材料としては、例えば、シリコン、各種セラミックス、ガラス、ステンレススチール等の金属等の無機材料、並びに、各種樹脂等の有機材料を使用することができる。これらのうち、基体６０は、はんだ微粒子の溶融温度で変質しない耐熱性を有する材質からなることが好ましい。また、基体６０の凹部６２は、フォトリソグラフ法、インプリント法、エッチング法等の公知の方法によって形成することができる。 Materials that can be used to form the base 60 include inorganic materials such as silicon, various ceramics, glass, and metals such as stainless steel, as well as organic materials such as various resins. Of these, the base 60 is preferably made of a heat-resistant material that does not change at the melting temperature of the solder particles. The recesses 62 in the base 60 can be formed by known methods such as photolithography, imprinting, and etching.

はんだ微粒子準備工程で準備されるはんだ微粒子は、凹部６２の表面６０ａにおける開口の幅（幅ｂ）より小さい粒子径の微粒子を含むものであればよく、幅ｂより小さい粒子径の微粒子をより多く含むことが好ましい。例えば、はんだ微粒子は、粒度分布のＤ１０粒子径が幅ｂより小さいことが好ましく、粒度分布のＤ３０粒子径が幅ｂより小さいことがより好ましく、粒度分布のＤ５０粒子径が幅ｂより小さいことが更に好ましい。The solder particles prepared in the solder particle preparation process may include particles having a particle diameter smaller than the width (width b) of the opening on the surface 60a of the recess 62, and preferably include more particles having a particle diameter smaller than width b. For example, the solder particles preferably have a D10 particle diameter in the particle size distribution smaller than width b, more preferably a D30 particle diameter in the particle size distribution smaller than width b, and even more preferably a D50 particle diameter in the particle size distribution smaller than width b.

はんだ微粒子の粒度分布は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザ回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。The particle size distribution of solder particles can be measured using various methods suited to the size. For example, dynamic light scattering, laser diffraction, centrifugal sedimentation, electrical sensing zone method, resonance mass measurement method, etc. can be used. In addition, a method can be used to measure particle size from images obtained by an optical microscope, electron microscope, etc. Specific devices include a flow type particle image analyzer, Microtrac, Coulter counter, etc.

準備工程で準備されるはんだ微粒子のＣ．Ｖ．値は特に限定されないが、大小の微粒子の組み合わせによる凹部６２への充填性が向上する観点から、Ｃ．Ｖ．値は高いことが好ましい。例えば、はんだ微粒子のＣ．Ｖ．値は、２０％を超えていてよく、好ましくは２５％以上、より好ましくは３０％以上である。Although the C.V. value of the solder particles prepared in the preparation process is not particularly limited, it is preferable that the C.V. value is high from the viewpoint of improving the filling property into the recess 62 by the combination of large and small particles. For example, the C.V. value of the solder particles may be more than 20%, preferably 25% or more, and more preferably 30% or more.

はんだ微粒子のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径（Ｄ５０粒子径）で割った値に１００を掛けることで算出される。The C.V. value of the solder particles is calculated by dividing the standard deviation of the particle diameter measured by the above-mentioned method by the average particle diameter (D50 particle diameter) and multiplying the result by 100.

はんだ微粒子は、スズ－ビスマス合金（Ｓｎ－Ｂｉ合金）を含む。スズ－ビスマス合金の具体例としては、下記の例が挙げられる。
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ（Ｓｎ７２質量％、Ｂｉ２８質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％ 融点１３９℃） The solder particles include a tin-bismuth alloy (Sn--Bi alloy). Specific examples of the tin-bismuth alloy include the following:
・Sn-Bi (Sn 43% by mass, Bi 57% by mass, melting point 138°C)
・Sn-Bi (Sn 72% by mass, Bi 28% by mass, melting point 138°C)
・Sn-Bi-Ag (Sn 42% by mass, Bi 57% by mass, Ag 1% by mass, melting point 139°C)

はんだ微粒子は、Ｓｎ及びＢｉ以外の他の金属を更に含んでいてもよい。他の金属としては、例えばＡｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ、Ｂ、Ｇａ、Ａｓ、Ｓｂ、Ｔｅ、Ｇｅ、Ｓｉ、Ａｌ等が挙げられる。はんだ微粒子の他の金属の含有率は、例えば１０質量％以下であり、好ましくは５質量％以下、より好ましくは３質量％以下である。The solder particles may further contain other metals besides Sn and Bi. Examples of other metals include Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P, B, Ga, As, Sb, Te, Ge, Si, and Al. The content of other metals in the solder particles is, for example, 10% by mass or less, preferably 5% by mass or less, and more preferably 3% by mass or less.

収容工程では、基体６０の凹部６２のそれぞれに、はんだ微粒子準備工程で準備したはんだ微粒子を収容する。収容工程では、はんだ微粒子準備工程で準備したはんだ微粒子の全部を凹部６２に収容する工程であってよく、はんだ微粒子準備工程で準備したはんだ微粒子の一部（例えば、はんだ微粒子のうち、凹部６２の開口の幅ｂより小さいもの）を凹部６２に収容する工程であってよい。In the accommodation process, the solder particles prepared in the solder particle preparation process are accommodated in each of the recesses 62 of the base 60. The accommodation process may be a process in which all of the solder particles prepared in the solder particle preparation process are accommodated in the recesses 62, or a process in which only a portion of the solder particles prepared in the solder particle preparation process (for example, solder particles smaller than the width b of the opening of the recesses 62) are accommodated in the recesses 62.

図５は、基体６０の凹部６２にはんだ微粒子１１１が収容された状態を模式的に示す断面図である。図５に示すように、複数の凹部６２のそれぞれに、複数のはんだ微粒子１１１が収容される。 Figure 5 is a cross-sectional view showing a schematic state in which solder particles 111 are accommodated in the recesses 62 of the base 60. As shown in Figure 5, a plurality of solder particles 111 are accommodated in each of the plurality of recesses 62.

凹部６２に収容されたはんだ微粒子１１１の量は、例えば、凹部６２の容積に対して２０％以上であることが好ましく、３０％以上であることがより好ましく、５０％以上であることが更に好ましく、６０％以上であることがもっとも好ましい。これにより、収容量のばらつきが抑えられ、粒度分布のより小さいはんだ粒子が得られやすくなる。The amount of solder particles 111 contained in the recess 62 is, for example, preferably 20% or more of the volume of the recess 62, more preferably 30% or more, even more preferably 50% or more, and most preferably 60% or more. This reduces the variation in the amount contained, making it easier to obtain solder particles with a smaller particle size distribution.

はんだ微粒子を凹部６２に収容する方法は特に限定されない。収容方法は、乾式、湿式のいずれであってもよい。例えば、準備工程で準備したはんだ微粒子を基体６０上に配置し、スキージを用いて基体６０の表面６０ａを擦ることで、余分なはんだ微粒子を除去しつつ、凹部６２内に十分なはんだ微粒子を収容することができる。凹部６２の開口の幅ｂが凹部６２の深さより大きい場合、凹部６２の開口からはんだ微粒子が飛び出す場合がある。スキージを用いると、凹部６２の開口から飛び出ているはんだ微粒子は除去される。余分なはんだ微粒子を除去する方法として、圧縮空気を吹き付ける、不織布又は繊維の束で基体６０の表面６０ａを擦る、等の方法も挙げられる。これらの方法は、スキージと比べて物理的な力が弱いため、変形しやすいはんだ微粒子を扱う上で好ましい。また、これらの方法では、凹部６２の開口から飛び出ているはんだ微粒子を凹部内に残すこともできる。The method of storing the solder particles in the recess 62 is not particularly limited. The method of storing may be either a dry method or a wet method. For example, the solder particles prepared in the preparation process are placed on the base 60, and the surface 60a of the base 60 is rubbed with a squeegee, so that sufficient solder particles can be stored in the recess 62 while removing excess solder particles. If the width b of the opening of the recess 62 is greater than the depth of the recess 62, the solder particles may fly out of the opening of the recess 62. If a squeegee is used, the solder particles protruding from the opening of the recess 62 are removed. Methods of removing excess solder particles include blowing compressed air, rubbing the surface 60a of the base 60 with a nonwoven fabric or a bundle of fibers, and the like. These methods are preferable for handling solder particles that are easily deformed because the physical force is weaker than that of a squeegee. In addition, these methods can also leave the solder particles protruding from the opening of the recess 62 in the recess.

融合工程は、凹部６２に収容されたはんだ微粒子１１１を融合させて、凹部６２の内部にはんだ粒子１を形成する工程である。図６は、基体６０の凹部６２にはんだ粒子１が形成された状態を模式的に示す断面図である。凹部６２に収容されたはんだ微粒子１１１は、溶融することで合一化し、表面張力によって球状化する。このとき、凹部６２の底部６２ａとの接触部では、溶融したはんだが底部６２ａに追従して平面部１１を形成する。これにより、形成されるはんだ粒子１は、表面の一部に平面部１１を有する形状となる。The fusion process is a process in which the solder particles 111 contained in the recesses 62 are fused to form solder particles 1 inside the recesses 62. Figure 6 is a cross-sectional view that shows a schematic state in which the solder particles 1 have been formed in the recesses 62 of the base 60. The solder particles 111 contained in the recesses 62 are unified by melting, and become spherical due to surface tension. At this time, at the contact portion with the bottom 62a of the recesses 62, the molten solder follows the bottom 62a to form a flat portion 11. As a result, the formed solder particle 1 has a shape that has a flat portion 11 on part of its surface.

図７（ａ）は、図６における凹部６２の開口部と反対側からはんだ粒子１を見た図である。はんだ粒子１は、直径Ｂを有する球の表面の一部に直径Ａの平面部１１が形成された形状を有している。なお、図６及び図７（ａ）に示すはんだ粒子１は、凹部６２の底部６２ａが平面であるため平面部１１を有するが、凹部６２の底部６２ａが平面以外の形状である場合は、底部６２ａの形状に対応した異なる形状の面を有するものとなる。 Figure 7(a) is a view of solder particle 1 viewed from the side opposite the opening of recess 62 in Figure 6. Solder particle 1 has a shape in which a flat portion 11 of diameter A is formed on part of the surface of a sphere having diameter B. Note that the solder particle 1 shown in Figures 6 and 7(a) has flat portion 11 because bottom 62a of recess 62 is flat, but if bottom 62a of recess 62 has a shape other than flat, it will have a surface of a different shape corresponding to the shape of bottom 62a.

凹部６２に収容されたはんだ微粒子１１１を溶融させる方法としては、はんだ微粒子１１１をはんだの融点以上に加熱する方法が挙げられる。はんだ微粒子１１１は、酸化被膜の影響で融点以上の温度で加熱しても溶融しない場合や、濡れ拡がらない場合や、合一化しない場合がある。このため、はんだ微粒子１１１を還元雰囲気下に晒し、はんだ微粒子１１１の表面酸化皮膜を除去した後に、はんだ微粒子１１１の融点以上の温度に加熱することで、はんだ微粒子１１１を溶融させ、濡れ拡がり、合一化させることができる。また、はんだ微粒子１１１の溶融は、還元雰囲気下で行うことが好ましい。はんだ微粒子１１１をはんだ微粒子１１１の融点以上に加熱し、かつ還元雰囲気とすることで、はんだ微粒子１１１の表面の酸化被膜が還元され、はんだ微粒子１１１の溶融、濡れ拡がり、合一化が効率的に進行しやすくなる。 As a method for melting the solder particles 111 accommodated in the recess 62, there is a method of heating the solder particles 111 to a temperature equal to or higher than the melting point of the solder. The solder particles 111 may not melt, wet, or coalesce even when heated to a temperature equal to or higher than the melting point due to the influence of an oxide film. For this reason, the solder particles 111 can be melted, wet, spread, and coalesce by exposing the solder particles 111 to a reducing atmosphere, removing the surface oxide film of the solder particles 111, and then heating the solder particles 111 to a temperature equal to or higher than the melting point of the solder particles 111. In addition, it is preferable to melt the solder particles 111 in a reducing atmosphere. By heating the solder particles 111 to a temperature equal to or higher than the melting point of the solder particles 111 and creating a reducing atmosphere, the oxide film on the surface of the solder particles 111 is reduced, and the melting, wet, spread, and coalescence of the solder particles 111 can proceed efficiently.

還元雰囲気にする方法は、上述の効果が得られる方法であれば特に限定されず、例えば水素ガス、水素ラジカル、ギ酸ガス等を用いる方法がある。例えば、水素還元炉、水素ラジカル還元炉、ギ酸還元炉、又はこれらのコンベアー炉若しくは連続炉を用いることで、還元雰囲気下にはんだ微粒子１１１を溶融させることができる。これらの装置は、炉内に、加熱装置、不活性ガス（窒素、アルゴン等）を充填するチャンバー、チャンバー内を真空にする機構等を備えていてよく、これにより還元ガスの制御がより容易となる。また、チャンバー内を真空にできると、はんだ微粒子１１１の溶融及び合一化の後に、減圧によってボイドの除去を行うことができ、接続安定性に一層優れるはんだ粒子１を得ることができる。The method of creating a reducing atmosphere is not particularly limited as long as the above-mentioned effects can be obtained, and examples of the method include a method using hydrogen gas, hydrogen radicals, formic acid gas, etc. For example, the solder particles 111 can be melted in a reducing atmosphere by using a hydrogen reduction furnace, a hydrogen radical reduction furnace, a formic acid reduction furnace, or a conveyor furnace or continuous furnace thereof. These devices may be equipped with a heating device, a chamber for filling an inert gas (nitrogen, argon, etc.), a mechanism for evacuating the chamber, etc., in the furnace, which makes it easier to control the reducing gas. In addition, if the chamber can be evacuated, voids can be removed by reducing the pressure after the solder particles 111 are melted and unified, and solder particles 1 with even better connection stability can be obtained.

はんだ微粒子１１１の還元、溶解条件、温度、炉内雰囲気調整などのプロファイルは、はんだ微粒子１１１の融点、粒度、凹部サイズ、基体６０の材質などを勘案して適宜設定されてよい。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。また、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターによりはんだ微粒子１１１を加熱して、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。還元雰囲気下で、はんだ微粒子を加熱することで、還元力が増し、はんだ微粒子の表面酸化皮膜の除去が容易になる利点がある。The reduction of the solder particles 111, the melting conditions, the temperature, the furnace atmosphere adjustment, and other profiles may be appropriately set in consideration of the melting point, particle size, recess size, and material of the base 60 of the solder particles 111. For example, the base 60 in which the recesses are filled with the solder particles 111 is inserted into a furnace, and after evacuation, a reducing gas is introduced to fill the furnace with the reducing gas, the surface oxide film of the solder particles 111 is removed, and the reducing gas is removed by evacuation. Thereafter, the solder particles 1 are heated to a temperature above the melting point of the solder particles 111 to melt and coalesce, forming solder particles in the recesses 62, and then nitrogen gas is filled and the temperature in the furnace is returned to room temperature to obtain the solder particles 1. Also, for example, the base 60 with the solder particles 111 filled in the recesses is inserted into a furnace, and after drawing a vacuum, a reducing gas is introduced to fill the furnace with the reducing gas, the solder particles 111 are heated by a furnace heater to remove the surface oxide film of the solder particles 111, and then the reducing gas is removed by drawing a vacuum, and then the solder particles 111 are heated to a temperature equal to or higher than the melting point thereof to melt and coalesce the solder particles to form solder particles in the recesses 62, and then nitrogen gas is filled and the temperature inside the furnace is returned to room temperature to obtain the solder particles 1. Heating the solder particles in a reducing atmosphere has the advantage of increasing the reducing power and making it easier to remove the surface oxide film of the solder particles.

さらに、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターにより基体６０をはんだ微粒子１１１の融点以上に加熱して、はんだ微粒子１１１の表面酸化被膜を還元により除去すると同時にはんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成し、真空引きにて還元ガスを除去し、さらにはんだ粒子内のボイドを減らした後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。この場合は、炉内温度の上昇、下降の調節がそれぞれ一回で良いため、短時間で処理出来る利点がある。 Furthermore, for example, the base 60 with the solder particles 111 filled in the recesses is inserted into a furnace, and after evacuation, reducing gas is introduced to fill the furnace with the reducing gas, and the base 60 is heated by the furnace heater to above the melting point of the solder particles 111, the surface oxide film of the solder particles 111 is removed by reduction and at the same time the solder particles are melted and unified to form solder particles in the recesses 62, the reducing gas is removed by evacuation, and the voids in the solder particles are further reduced. After that, nitrogen gas is filled in the furnace and the temperature in the furnace is returned to room temperature, and the solder particles 1 can be obtained. In this case, the temperature in the furnace only needs to be increased and decreased once each, which has the advantage of allowing processing in a short time.

上述の凹部６２内にはんだ粒子を形成した後に、もう一度炉内を還元雰囲気にして、除去し切れなかった表面酸化皮膜を除去する工程を加えてもよい。これにより、融合されずに残っていたはんだ微粒子や、融合されずに残っていた酸化皮膜の一部などの残渣を減らすことができる。After forming the solder particles in the recesses 62, a process may be added in which the furnace is once again placed in a reducing atmosphere to remove any remaining surface oxide film. This can reduce the amount of solder particles that remain unfused and the amount of oxide film that remains unfused.

大気圧のコンベアー炉を用いる場合は、はんだ微粒子１１１が凹部に充填された基体６０を搬送用コンベアーに載せ、複数のゾーンを連続して通過させてはんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点より低い温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点より低い温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化皮膜を除去し、続いてはんだ微粒子１１１の融点以上の温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させてはんだ微粒子１１１を溶融、合一化させ、続いて窒素やアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点以上の温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点以上の温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化皮膜を除去し、溶融、合一化させ、続いて窒素やアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。前記のコンベアー炉は、大気圧での処理が可能であることから、フィルム状の材料をロールトゥロールで連続的に処理することもできる。例えば、はんだ微粒子１１１が凹部に充填された基体６０の連続ロール品を作製し、コンベアー炉の入り口側にロール巻きだし機、コンベアー炉の出口側にロール巻き取り機を設置して、一定の速度で基体６０を搬送し、コンベアー炉内の各ゾーンを通過させることで、凹部に充填されたはんだ微粒子１１１を融合させることができる。When an atmospheric pressure conveyor furnace is used, the substrate 60 with the recesses filled with the solder particles 111 can be placed on a conveyor and passed through multiple zones in succession to obtain the solder particles 1. For example, the substrate 60 with the recesses filled with the solder particles 111 can be placed on a conveyor set to a constant speed, passed through a zone filled with an inert gas such as nitrogen or argon at a temperature lower than the melting point of the solder particles 111, then passed through a zone containing a reducing gas such as formic acid gas at a temperature lower than the melting point of the solder particles 111 to remove the surface oxide film of the solder particles 111, then passed through a zone filled with an inert gas such as nitrogen or argon at a temperature higher than the melting point of the solder particles 111 to melt and coalesce the solder particles 111, and then passed through a cooling zone filled with an inert gas such as nitrogen or argon to obtain the solder particles 1. For example, the base 60 with the solder particles 111 filled in the recesses is placed on a conveyor set at a constant speed, passed through a zone filled with an inert gas such as nitrogen or argon at a temperature equal to or higher than the melting point of the solder particles 111, and then passed through a zone where a reducing gas such as formic acid gas at a temperature equal to or higher than the melting point of the solder particles 111 is present, to remove the surface oxide film of the solder particles 111, melt and unify them, and then passed through a cooling zone filled with an inert gas such as nitrogen or argon to obtain solder particles 1. Since the conveyor furnace can perform processing at atmospheric pressure, it is also possible to continuously process a film-like material by roll-to-roll. For example, a continuous roll product of the base 60 with the solder particles 111 filled in the recesses is produced, and a roll unwinder is installed at the entrance side of the conveyor furnace and a roll winder is installed at the exit side of the conveyor furnace, and the base 60 is transported at a constant speed and passed through each zone in the conveyor furnace, thereby fusing the solder particles 111 filled in the recesses.

はんだ微粒子準備工程～融合工程によれば、はんだ微粒子１１１の材質及び形状によらず、均一なサイズのはんだ粒子１を形成することができる。また、形成されたはんだ粒子１は、基体６０の凹部６２に収容された状態で取り扱うことができるため、はんだ粒子１を変形させることなく運搬・保管等することができる。さらに、形成されたはんだ粒子１は、単に基体６０の凹部６２に収容された状態であるため、取り出しが容易であり、はんだ粒子を変形させることなく回収・表面処理等を行うことができる。 By carrying out the solder particle preparation process through the fusion process, solder particles 1 of uniform size can be formed regardless of the material and shape of the solder particles 111. Furthermore, since the formed solder particles 1 can be handled while contained in the recesses 62 of the base 60, they can be transported, stored, etc., without deforming the solder particles 1. Furthermore, since the formed solder particles 1 are simply contained in the recesses 62 of the base 60, they can be easily removed, and recovery, surface treatment, etc. can be performed without deforming the solder particles.

また、はんだ微粒子１１１は、粒度分布にばらつきが大きくても、形状がいびつであってもよく、凹部６２内に収容することができれば原料として好適に用いることができる。Furthermore, the solder particles 111 may have a large variation in particle size distribution or may have an irregular shape, and can be suitably used as a raw material as long as they can be contained within the recess 62.

また、上記方法において、基体６０は、リソグラフィー、機械加工、インプリント、エッチング等によって凹部６２の形状を自在に設計できる。はんだ粒子１のサイズは凹部６２に収容されるはんだ微粒子１１１の量に依存するため、凹部６２の設計によりはんだ粒子１のサイズを自在に設計できる。In the above method, the shape of the recesses 62 of the base 60 can be freely designed by lithography, machining, imprinting, etching, etc. Since the size of the solder particles 1 depends on the amount of solder particles 111 accommodated in the recesses 62, the size of the solder particles 1 can be freely designed by designing the recesses 62.

融合工程で形成されたはんだ粒子１は、そのまま転写工程に使用してよく、基体６０の凹部６２に収容された状態で表面をフラックス成分で被覆してから転写工程に使用してもよく、凹部６２から取り出し、表面をフラックス成分で被覆し、凹部６２に再度収容してから転写工程に使用してもよい。なお、ここでは、はんだ粒子１の形成に用いた基体６０をそのまま転写工程に利用しているが、凹部６２からはんだ粒子１と取り出すステップを含む場合は、取り出したはんだ粒子１を、基体６０とは異なる基体に収容して、転写工程に用いてもよい。The solder particles 1 formed in the fusion process may be used as is in the transfer process, or may be housed in the recess 62 of the base 60 with the surface coated with a flux component and then used in the transfer process, or may be removed from the recess 62, have the surface coated with a flux component, and housed again in the recess 62 before being used in the transfer process. Note that here, the base 60 used to form the solder particles 1 is used as is in the transfer process, but if a step of removing the solder particles 1 from the recess 62 is included, the removed solder particles 1 may be housed in a base different from the base 60 and used in the transfer process.

転写工程は、はんだ粒子１が凹部６２に収容されている状態の基体６０に対して、凹部６２の開口側から絶縁性樹脂材料２ａを接触させることにより、はんだ粒子１が転写された第一の樹脂層２ｂを得る工程である。The transfer process is a process in which an insulating resin material 2a is brought into contact with a base 60 in which solder particles 1 are contained in the recesses 62 from the opening side of the recesses 62, thereby obtaining a first resin layer 2b to which the solder particles 1 are transferred.

図８（ａ）に示す基体６０は、凹部６２のそれぞれに一個のはんだ粒子１が収容された状態である。この基体６０の凹部６２の開口側の面に、層状の絶縁性樹脂組成物２ａを対向させて、基体６０と層状の絶縁性樹脂組成物２ａとを近づける（図８（ａ）における矢印Ａ，Ｂ）。なお、層状の絶縁性樹脂組成物２ａは、支持体６５の表面上に形成されている。支持体６５は、プラスチックフィルムであってもよいし、金属箔であってもよい。 The substrate 60 shown in Figure 8(a) has one solder particle 1 accommodated in each recess 62. The layered insulating resin composition 2a is placed opposite the opening side of the recess 62 of the substrate 60, and the substrate 60 and the layered insulating resin composition 2a are brought close to each other (arrows A and B in Figure 8(a)). The layered insulating resin composition 2a is formed on the surface of the support 65. The support 65 may be a plastic film or a metal foil.

図８（ｂ）は、転写工程後の状態であって、基体６０の凹部６２の開口側の面を層状の絶縁性樹脂組成物２ａに接触させたことにより、基体６０の凹部６２に収容されていたはんだ粒子１が層状の絶縁性樹脂組成物２ａに転写された状態を示している。転写工程を経ることで、層状の絶縁性樹脂組成物２ａの所定の位置に複数のはんだ粒子１が転写された第一の樹脂層２ｂが得られる。第一の樹脂層２ｂは、その表面に複数のはんだ粒子１が露出している。なお、上記製造方法において、複数のはんだ粒子１は、いずれも平面部１１が第二の樹脂層２ｄ側を向いた状態で、異方性導電フィルム１０中に配置されている。 Figure 8 (b) shows the state after the transfer process, in which the surface on the opening side of the recess 62 of the substrate 60 is brought into contact with the layered insulating resin composition 2a, and the solder particles 1 contained in the recess 62 of the substrate 60 are transferred to the layered insulating resin composition 2a. Through the transfer process, a first resin layer 2b is obtained in which a plurality of solder particles 1 are transferred to predetermined positions of the layered insulating resin composition 2a. The first resin layer 2b has a plurality of solder particles 1 exposed on its surface. In the above manufacturing method, the plurality of solder particles 1 are all arranged in the anisotropic conductive film 10 with the planar portion 11 facing the second resin layer 2d.

積層工程は、第一の樹脂層２ｂの、はんだ粒子１が転写された側の表面２ｃ上に、絶縁性樹脂組成物で構成される第二の樹脂層２ｄを形成することにより、異方性導電フィルム１０を得る工程である。The lamination process is a process for obtaining an anisotropic conductive film 10 by forming a second resin layer 2d composed of an insulating resin composition on the surface 2c of the first resin layer 2b on which the solder particles 1 are transferred.

図８（ｃ）は、積層工程後の状態であって、第一の樹脂層２ｂの表面２ｃ上に、はんだ粒子１を覆うように第二の樹脂層２ｄを形成した後、支持体６５を取り除いた状態を示している。第二の樹脂層２ｄは、絶縁性樹脂組成物からなる絶縁性フィルムを第一の樹脂層２ｂにラミネートすることによって形成してもよく、絶縁性樹脂材料を含むワニスで第一の樹脂層２ｂを被覆した後、硬化処理を施すことによって形成してもよい。8(c) shows the state after the lamination process, in which the second resin layer 2d is formed on the surface 2c of the first resin layer 2b so as to cover the solder particles 1, and then the support 65 is removed. The second resin layer 2d may be formed by laminating an insulating film made of an insulating resin composition onto the first resin layer 2b, or may be formed by coating the first resin layer 2b with a varnish containing an insulating resin material and then performing a curing process.

次に、図９を参照しながら、第二実施形態に係る異方性導電フィルム１０の製造方法について説明する。Next, referring to Figure 9, a manufacturing method for the anisotropic conductive film 10 according to the second embodiment will be described.

第二実施形態では、準備工程、収容工程及び融合工程を第一実施形態と同様にして実施した後、転写工程において、凹部６２の内部にまで絶縁性樹脂組成物を侵入させることにより、はんだ粒子１を第一の樹脂層２ｂに埋設する。In the second embodiment, the preparation process, accommodation process and fusion process are carried out in the same manner as in the first embodiment, and then in the transfer process, the insulating resin composition is allowed to penetrate into the interior of the recess 62, thereby embedding the solder particles 1 in the first resin layer 2b.

図９（ａ）に示す基体６０は、凹部６２のそれぞれに一個のはんだ粒子１が収容された状態である。この基体６０の凹部６２の開口側の面に、層状の絶縁性樹脂組成物２ａを対向させて、基体６０と層状の絶縁性樹脂組成物２ａとを近づける（図９（ａ）における矢印Ａ，Ｂ）。 The substrate 60 shown in Figure 9(a) has one solder particle 1 housed in each recess 62. The layered insulating resin composition 2a is placed opposite the opening side of the recess 62 of the substrate 60, and the substrate 60 and the layered insulating resin composition 2a are brought close to each other (arrows A and B in Figure 9(a)).

図９（ｂ）は、転写工程後の状態であって、基体６０の凹部６２の開口側の面を層状の絶縁性樹脂組成物２ａに接触させたことにより、基体６０の凹部６２に収容されていたはんだ粒子１が層状の絶縁性樹脂組成物２ａに転写された状態を示している。転写工程を経ることで、所定の位置に複数のはんだ粒子１が配置された第一の樹脂層２ｂが得られる。第一の樹脂層２ｂの表面２ｃ側には、凹部６２に応じた複数の凸部２ｅが形成されており、これら凸部２ｅにはんだ粒子１が埋設されている。このような第一の樹脂層２ｂを得るため、転写工程では、凹部６２の内部にまで絶縁性樹脂材料２ａを侵入させる。具体的には、基体６０と層状の絶縁性樹脂組成物２ａとを、積層方向（図９（ａ）における矢印Ａ，Ｂの方向）に加圧することで、層状の絶縁性樹脂組成物２ａを凹部６２の内部に侵入させてよい。また、転写工程を減圧雰囲気下で行うと、層状の絶縁性樹脂組成物２ａが凹部６２の内部に入りやすくなる。また、図９では層状の絶縁性樹脂材料２ａによって転写工程を実施しているが、絶縁性樹脂組成物をワニスの状態で凹部６２の内部及び基体６０の表面に塗布し、硬化処理を施すことによって、第一の樹脂層２ｂを得ることもできる。9(b) shows the state after the transfer process, in which the surface of the opening side of the recess 62 of the substrate 60 is brought into contact with the layered insulating resin composition 2a, and the solder particles 1 accommodated in the recess 62 of the substrate 60 are transferred to the layered insulating resin composition 2a. Through the transfer process, a first resin layer 2b in which a plurality of solder particles 1 are arranged at predetermined positions is obtained. A plurality of convex portions 2e corresponding to the recess 62 are formed on the surface 2c side of the first resin layer 2b, and the solder particles 1 are embedded in these convex portions 2e. In order to obtain such a first resin layer 2b, in the transfer process, the insulating resin material 2a is allowed to penetrate into the inside of the recess 62. Specifically, the substrate 60 and the layered insulating resin composition 2a may be pressurized in the stacking direction (the direction of the arrows A and B in FIG. 9(a)) to allow the layered insulating resin composition 2a to penetrate into the inside of the recess 62. In addition, if the transfer process is performed under a reduced pressure atmosphere, the layered insulating resin composition 2a is more likely to enter the inside of the recess 62. In addition, in Figure 9, the transfer process is carried out using a layer of insulating resin material 2a, but the first resin layer 2b can also be obtained by applying an insulating resin composition in the form of a varnish to the inside of the recess 62 and the surface of the base 60 and carrying out a curing treatment.

図９（ｃ）は、積層工程後の状態であって、第一の樹脂層２ｂの表面２ｃ上に、第二の樹脂層２ｄを形成した後、支持体６５を取り除いた状態を示している。第二の樹脂層２ｄは、絶縁性樹脂組成物からなる絶縁性フィルムを第一の樹脂層２ｂにラミネートすることによって形成してもよく、絶縁性樹脂組成物を含むワニスで第一の樹脂層２ｂを被覆した後、硬化処理を施すことによって形成してもよい。9(c) shows the state after the lamination process, in which the second resin layer 2d is formed on the surface 2c of the first resin layer 2b and the support 65 is removed. The second resin layer 2d may be formed by laminating an insulating film made of an insulating resin composition onto the first resin layer 2b, or by coating the first resin layer 2b with a varnish containing the insulating resin composition and then performing a curing process.

なお、上記製造方法において、複数のはんだ粒子１は、いずれも平面部１１が第二の樹脂層２ｄ側を向いた状態で、異方性導電フィルム１０中に配置されている。融合工程で形成されたはんだ粒子１を一度取り出し、フラックス成分での被覆等の処理を施した後、再度、凹部６２に再配置する方法を採用した場合、複数のはんだ粒子１は、平面部１１の向きが互いに異なっていてもよい。図１０（ａ）は、一度取り出したはんだ粒子１を凹部６２に再配置した状態を示している。このような状態で転写工程及び積層工程を行うことで、複数のはんだ粒子１は、平面部１１の向きが一致しない状態で異方性導電フィルム１０中に配置される。図１０（ｂ）は、複数のはんだ粒子１が、平面部１１の向きが一致しない状態で異方性導電フィルム１０に配置された状態を示す図である。In the above manufacturing method, the multiple solder particles 1 are arranged in the anisotropic conductive film 10 with the flat portion 11 facing the second resin layer 2d. When the method of taking out the solder particles 1 formed in the fusion process, coating with a flux component, etc., and then re-arranging them in the recess 62 is adopted, the multiple solder particles 1 may have different orientations of the flat portion 11. FIG. 10(a) shows the state in which the solder particles 1 once taken out are rearranged in the recess 62. By performing the transfer process and lamination process in this state, the multiple solder particles 1 are arranged in the anisotropic conductive film 10 with the flat portions 11 not aligned. FIG. 10(b) is a diagram showing the state in which the multiple solder particles 1 are arranged in the anisotropic conductive film 10 with the flat portions 11 not aligned.

＜接続構造体＞
図１１は、接続構造体の一部を拡大して示す図であって、第一の電極と第二の電極とが接合部によって電気的に接続された状態を模式的に示す断面図である。すなわち、図１１は、第一の回路部材３０の電極３２と第二の回路部材４０の電極４２が、はんだ粒子１の融着により形成された接合部７０を介して電気的に接続された状態を模式的に示したものである。本明細書において「融着」とは上記のとおり、電極の少なくとも一部が熱によって融解されたはんだ粒子１によって接合され、その後、これが固化する工程を経ることによって電極の表面にはんだが接合された状態を意味する。第一の回路部材３０は、第一の回路基板３１と、その表面３１ａ上に配置された第一の電極３２とを備える。第二の回路部材４０は、第二の回路基板４１と、その表面４１ａ上に配置された第二の電極４２とを備える。回路部材３０，４０の間に充填された絶縁樹脂層５５は、第一の回路部材３０と第二の回路部材４０が接着された状態を維持するとともに、第一の電極３２と第二の電極４２が電気的に接続された状態を維持する。 <Connection structure>
11 is a diagram showing an enlarged portion of the connection structure, and is a cross-sectional view showing a state in which the first electrode and the second electrode are electrically connected by a joint. That is, FIG. 11 shows a schematic diagram of a state in which the electrode 32 of the first circuit member 30 and the electrode 42 of the second circuit member 40 are electrically connected via a joint 70 formed by fusion of the solder particles 1. In this specification, "fusion" means a state in which at least a part of the electrode is joined by the solder particles 1 melted by heat, and then the solder is joined to the surface of the electrode through a process of solidification, as described above. The first circuit member 30 includes a first circuit board 31 and a first electrode 32 arranged on the surface 31a of the first circuit board 31. The second circuit member 40 includes a second circuit board 41 and a second electrode 42 arranged on the surface 41a of the second circuit board 41. The insulating resin layer 55 filled between the circuit members 30, 40 maintains the first circuit member 30 and the second circuit member 40 in an adhered state, and also maintains the first electrode 32 and the second electrode 42 in an electrically connected state.

回路部材３０，４０のうちの一方の具体例として、ＩＣチップ（半導体チップ）、抵抗体チップ、コンデンサチップ、ドライバーＩＣ等のチップ部品；リジット型のパッケージ基板が挙げられる。これらの回路部材は、回路電極を備えており、多数の回路電極を備えているものが一般的である。回路部材３０，４０のうちの他方の具体例としては、金属配線を有するフレキシブルテープ基板、フレキシブルプリント配線板、インジウムスズ酸化物（ＩＴＯ）が蒸着されたガラス基板等の配線基板が挙げられる。 Specific examples of one of the circuit members 30, 40 include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, and driver ICs; and rigid package substrates. These circuit members have circuit electrodes, and generally have a large number of circuit electrodes. Specific examples of the other of the circuit members 30, 40 include wiring substrates such as flexible tape substrates with metal wiring, flexible printed wiring boards, and glass substrates on which indium tin oxide (ITO) is vapor-deposited.

第一の電極３２又は第二の電極４２の具体例としては、銅、銅／ニッケル、銅／ニッケル／金、銅／ニッケル／パラジウム、銅／ニッケル／パラジウム／金、銅／ニッケル／金、銅／パラジウム、銅／パラジウム／金、銅／スズ、銅／銀、インジウムスズ酸化物等の電極が挙げられる。第一の電極３２または第二の電極４２は、無電解めっき又は電解めっき又はスパッタ又は金属箔のエッチングで形成することができる。Specific examples of the first electrode 32 or the second electrode 42 include electrodes such as copper, copper/nickel, copper/nickel/gold, copper/nickel/palladium, copper/nickel/palladium/gold, copper/nickel/gold, copper/palladium, copper/palladium/gold, copper/tin, copper/silver, and indium tin oxide. The first electrode 32 or the second electrode 42 can be formed by electroless plating, electrolytic plating, sputtering, or etching of a metal foil.

本実施形態において、第一の電極３２及び第二の電極４２のうち少なくとも一方は金電極である。In this embodiment, at least one of the first electrode 32 and the second electrode 42 is a gold electrode.

接合部７０は、第一の電極３２と第二の電極４２とを接続する第一の領域７１と、第一の領域と接する第二の領域７２とを含んでいる。本実施形態では、溶融したはんだと金電極との接触により、金電極中の金の一部がはんだ中のスズと合金（スズ－金合金）を形成し、第一の領域７１が形成されると考えられる。また、これに伴い、はんだ中のビスマスは第一の領域７１から押し出され、第一の領域７１の周囲を囲む第二の領域７２が形成されると考えられる。The joint 70 includes a first region 71 that connects the first electrode 32 and the second electrode 42, and a second region 72 that contacts the first region. In this embodiment, it is believed that contact between the molten solder and the gold electrode causes some of the gold in the gold electrode to form an alloy (tin-gold alloy) with the tin in the solder, forming the first region 71. It is also believed that this causes the bismuth in the solder to be pushed out of the first region 71, forming the second region 72 that surrounds the periphery of the first region 71.

第一の領域７１は、スズ－金合金から構成されたものであってよく、第二の領域７２は、ビスマスから構成されたものであってよい。The first region 71 may be composed of a tin-gold alloy, and the second region 72 may be composed of bismuth.

第一の領域７１の体積Ｖ１に対する第二の領域７２の体積Ｖ２の比Ｖ２／Ｖ１は、例えば０．０５～２．０であってよく、０．１～１．５が好ましく、０．１８～１．０がより好ましい。 The ratio V 2 /V 1 of the volume V 2 of the second region 72 to the volume V 1 of the first region 71 may be, for example, 0.05 to 2.0, preferably 0.1 to 1.5, and more preferably 0.18 to 1.0.

接続構造体中に複数存在する接合部のうち、第一の領域７１及び第二の領域７２を含む接合部７０の割合は、９０％以上であり、好ましくは９５％以上であり、より好ましくは９９％以上であり、１００％であってもよい。なお、第一の領域７１及び第二の領域７２を含まない接合部としては、例えば、スズ－ビスマス合金から構成された柱状部を有する接合部等が挙げられる。Among the multiple joints present in the connection structure, the proportion of joints 70 including the first region 71 and the second region 72 is 90% or more, preferably 95% or more, more preferably 99% or more, and may be 100%. Note that examples of joints that do not include the first region 71 and the second region 72 include joints having columnar portions made of a tin-bismuth alloy.

図１５（ａ）、図１５（ｂ）、図１５（ｃ）、図１５（ｄ）、図１６（ａ）、図１６（ｂ）、図１６（ｃ）及び図１６（ｄ）は、それぞれ、第一の領域７１及び第二の領域７２を含む接合部の一例を模式的に示す積層方向の断面図である。 Figures 15(a), 15(b), 15(c), 15(d), 16(a), 16(b), 16(c) and 16(d) are cross-sectional views in the stacking direction that typically show an example of a joint including a first region 71 and a second region 72.

図１５（ａ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１を取り囲む円環状構造を有してよい。図１５（ａ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ａ）に示すような構造であってよい。15(a), in the joint 70, the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 72 may have an annular structure surrounding the first region 71. A cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 15(a) may have a structure as shown in FIG. 17(a), for example.

図１５（ｂ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１の一部と接する塊状であってよい。図１５（ｂ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｂ）に示すような構造であってよい。15(b), in the joint 70, the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 72 may be a block in contact with a part of the first region 71. A cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 15(b) may have a structure as shown in FIG. 17(b), for example.

図１５（ｃ）に示すように、接合部７０は、第一の電極３２と第二の電極４２とを連結する柱状構造を有する第一の領域７１を複数含んでいてよい。また、この接合部７０において、第二の領域７２は、複数の第一の領域７１の間に、複数の第一の領域７１同士を接続するように配置されていてよい。図１５（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば，図１７（ｃ）に示すような構造であってよい。As shown in FIG. 15(c), the joint 70 may include a plurality of first regions 71 having a columnar structure connecting the first electrode 32 and the second electrode 42. In addition, in this joint 70, the second region 72 may be disposed between the plurality of first regions 71 so as to connect the plurality of first regions 71 to each other. The cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 15(c) may have a structure as shown in FIG. 17(c), for example.

図１５（ｄ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよい。また、接合部７０は、柱状構造以外に更にスズ－金合金を含有する塊状体を有していてよい。当該塊状体は、図１５（ｄ）に示すように第一の領域７１と一体化して第一の領域７１の一部を構成して（すなわち、第一の領域７１が、柱状部と塊状部とを有して）いてよく、第一の領域７１と離間して存在していてもよい。前者の場合、第二の領域７２は、第一の領域７１の柱状部又は塊状部と接するように配置されていてよく、後者の場合、第二の領域７２が、第一の領域７１及び塊状体の両方に接するように配置されていてよい。図１５（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｃ）又は図１７（ｄ）に示すような構造であってよい。As shown in FIG. 15(d), in the joint 70, the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42. In addition, the joint 70 may have a mass containing a tin-gold alloy in addition to the columnar structure. The mass may be integrated with the first region 71 to form a part of the first region 71 (i.e., the first region 71 has a columnar portion and a mass portion) as shown in FIG. 15(d), or may be present apart from the first region 71. In the former case, the second region 72 may be arranged so as to contact the columnar portion or the mass portion of the first region 71, and in the latter case, the second region 72 may be arranged so as to contact both the first region 71 and the mass. The cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 15(c) may have a structure as shown in FIG. 17(c) or FIG. 17(d), for example.

図１６（ａ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１を取り囲む円環状構造を有していてよい。また、接合部７０は、円環状構造以外に、更にビスマスを含有する塊状体を有していてよい。当該塊状体は、図１６（ａ）に示すように第二の領域７２と一体化して第二の領域７２の一部を構成して（すなわち、第二の領域７２が、円環状部と塊状部とを有して）いてよく、円環状の第二の領域７２と離間して、もう一つの第二の領域７２として第一の領域７１と接していてもよい。図１６（ａ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｄ）に示すような構造であってよい。As shown in FIG. 16(a), in the joint 70, the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 72 may have a ring-shaped structure surrounding the first region 71. In addition, the joint 70 may further have a mass containing bismuth in addition to the ring-shaped structure. The mass may be integrated with the second region 72 as shown in FIG. 16(a) to form a part of the second region 72 (i.e., the second region 72 has a ring-shaped portion and a mass-shaped portion), or may be separated from the ring-shaped second region 72 and contact the first region 71 as another second region 72. The cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 16(a) may have a structure as shown in FIG. 17(d), for example.

図１６（ｂ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１の一部を取り囲む円環状構造を有していてよい。また、第一の領域７１は、第一の電極３２又は第二の電極４２の電極表面に沿って拡がっていてよい。16(b), in the junction 70, the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 72 may have an annular structure surrounding a part of the first region 71. In addition, the first region 71 may extend along the electrode surface of the first electrode 32 or the second electrode 42.

図１６（ｃ）又は図１６（ｄ）に示すように、接合部７０は、複数のはんだ粒子１（又ははんだバンプ）が合一化して形成されたものであってよい。図１６（ｃ）に示すように、接合部７０は、複数のはんだ粒子１の合一化によって形成された、柱状構造を有する第一の領域７１を含んでいてよく、当該第一の領域７１を取り囲む円環状の第二の領域７２を更に含んでいてよい。また、図１６（ｄ）に示すように、接合部７０は、複数のはんだ粒子１（又ははんだバンプ）のそれぞれ由来する複数の第一の領域７１を有していてよく、第二の領域７２によって複数の第一の領域７１が接続されていてよい。図１６（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｅ）に示すような構造であってよい。また、図１６（ｄ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｆ）に示すような構造であってよい。As shown in FIG. 16(c) or FIG. 16(d), the joint 70 may be formed by unifying a plurality of solder particles 1 (or solder bumps). As shown in FIG. 16(c), the joint 70 may include a first region 71 having a columnar structure formed by unifying a plurality of solder particles 1, and may further include a ring-shaped second region 72 surrounding the first region 71. Also, as shown in FIG. 16(d), the joint 70 may have a plurality of first regions 71 originating from a plurality of solder particles 1 (or solder bumps), and the plurality of first regions 71 may be connected by the second region 72. The cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 16(c) may have a structure as shown in FIG. 17(e), for example. Also, the cross section perpendicular to the stacking direction of the joint 70 shown in FIG. 16(d) may have a structure as shown in FIG. 17(f), for example.

次に、図１８（ａ）、図１８（ｂ）及び図１８（ｃ）、は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す積層方向の断面図である。Next, Figures 18(a), 18(b) and 18(c) are cross-sectional views in the stacking direction that typically show an example of a joint that does not include a first region and a second region.

図１８（ａ）に示す接合部９０では、スズ－金合金を含有する領域９１が、第一の電極３２側及び第二の電極４２側のそれぞれに偏在しており、第一の電極３２と第二の電極４２とを連結できていない。また、第一の電極３２側の領域９１と第二の電極４２側の領域９１との間に、ビスマスを含有する領域９２が形成されている。図１８（ａ）に示す接合部９０は、第一の領域を有しないため、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）又は図１９（ｃ）に示すような構造であってよい。In the joint 90 shown in FIG. 18(a), the region 91 containing the tin-gold alloy is unevenly distributed on each of the first electrode 32 side and the second electrode 42 side, and the first electrode 32 and the second electrode 42 cannot be connected. In addition, a region 92 containing bismuth is formed between the region 91 on the first electrode 32 side and the region 91 on the second electrode 42 side. The joint 90 shown in FIG. 18(a) does not have a first region, and therefore does not fall under the category of a "joint including a first region and a second region." The cross section perpendicular to the stacking direction of the joint 90 shown in FIG. 18(a) may have a structure as shown in, for example, FIG. 19(a), FIG. 19(b), or FIG. 19(c).

図１８（ｂ）に示す接合部９０では、スズ－金合金を含有する領域９１が、第二の電極４２側に偏在しており、領域９１と第一の電極３２との間に、ビスマスを含有する領域９２が形成されている。図１８（ｂ）に示す接合部９０は、領域９１が第一の電極３２と第二の電極４２とを連結しておらず、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）又は図１９（ｃ）に示すような構造であってよい。In the joint 90 shown in FIG. 18(b), a region 91 containing a tin-gold alloy is unevenly distributed on the second electrode 42 side, and a region 92 containing bismuth is formed between the region 91 and the first electrode 32. In the joint 90 shown in FIG. 18(b), the region 91 does not connect the first electrode 32 and the second electrode 42, and the joint does not correspond to a "joint including a first region and a second region." A cross section perpendicular to the stacking direction of the joint 90 shown in FIG. 18(a) may have a structure as shown in, for example, FIG. 19(a), FIG. 19(b), or FIG. 19(c).

図１８（ｃ）に示す接合部９０では、スズ－金合金を含有する領域９１とビスマス合金を有する領域９２とが第二の電極４２側に偏在しており、第一の電極３２と第二の電極４２とが電気的に接続されていない。また、図１８（ｃ）に示す接合部９０では、金とスズとの合金化が不十分で領域９２中に、スズを含む領域９３が形成されている。図１８（ｃ）に示す接合部９０は、領域９１が第一の電極３２と第二の電極４２とを連結しておらず、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）、図１９（ｃ）又は図１９（ｄ）に示すような構造であってよい。In the joint 90 shown in FIG. 18(c), a region 91 containing a tin-gold alloy and a region 92 containing a bismuth alloy are unevenly distributed on the second electrode 42 side, and the first electrode 32 and the second electrode 42 are not electrically connected. In the joint 90 shown in FIG. 18(c), the alloying of gold and tin is insufficient, and a region 93 containing tin is formed in the region 92. In the joint 90 shown in FIG. 18(c), the region 91 does not connect the first electrode 32 and the second electrode 42, and does not correspond to a "joint including a first region and a second region". The cross section perpendicular to the stacking direction of the joint 90 shown in FIG. 18(a) may have a structure as shown in, for example, FIG. 19(a), FIG. 19(b), FIG. 19(c), or FIG. 19(d).

＜接続構造体の製造方法＞
図１２（ａ）及び図１２（ｂ）を参照しながら、接続構造体の製造方法について説明する。これらの図は、図１１に示す接続構造体５０Ａを形成する過程の一例を模式的に示す断面図である。まず、図１に示す異方性導電フィルム１０を予め準備し、これを第一の回路部材３０と第二の回路部材４０とが対面するように配置する（図１２（ａ））。このとき、第一の回路部材３０の第一の電極３２と第二の回路部材４０の第二の電極４２とが対向するように設置する。その後、これらの部材の積層体の厚さ方向（図１２（ａ）に示す矢印Ａ及び矢印Ｂの方向）に加圧する。矢印Ａ及び矢印Ｂの方向に加圧する際に全体をはんだ粒子１の融点よりも高い温度（例えば１３０～２６０℃）に少なくとも加熱することによって、はんだ粒子１が溶融し、第一の電極３２と第二の電極４２の間に寄り集まって、接合部７０が形成され、その後、冷却することで第一の電極３２と第二の電極４２の間に接合部７０が固着され、第一の電極３２と第二の電極４２が電気的に接続される。 <Method of Manufacturing Connection Structure>
A method for manufacturing a connection structure will be described with reference to Figures 12(a) and 12(b). These figures are cross-sectional views that typically show an example of a process for forming a connection structure 50A shown in Figure 11. First, the anisotropic conductive film 10 shown in Figure 1 is prepared in advance, and is arranged so that the first circuit member 30 and the second circuit member 40 face each other (Figure 12(a)). At this time, the first electrode 32 of the first circuit member 30 and the second electrode 42 of the second circuit member 40 are placed so as to face each other. Then, pressure is applied in the thickness direction of the laminate of these members (the directions of arrows A and B shown in Figure 12(a)). When applying pressure in the directions of arrows A and B, the entire structure is heated to at least a temperature (e.g., 130 to 260°C) higher than the melting point of the solder particles 1, whereby the solder particles 1 melt and gather between the first electrode 32 and the second electrode 42 to form a joint 70, and then the joint 70 is fixed between the first electrode 32 and the second electrode 42 by cooling, and the first electrode 32 and the second electrode 42 are electrically connected.

絶縁性フィルム２を構成する絶縁性樹脂組成物が例えば熱硬化性樹脂を含む場合、矢印Ａ及び矢印Ｂの方向に加圧する際に全体を加熱することによって絶縁性樹脂組成物を硬化させることができる。これにより、絶縁性樹脂組成物の硬化物からなる絶縁樹脂層５５が回路部材３０，４０の間に形成される。When the insulating resin composition constituting the insulating film 2 contains, for example, a thermosetting resin, the insulating resin composition can be cured by heating the entire film while applying pressure in the directions of arrows A and B. As a result, an insulating resin layer 55 made of the cured product of the insulating resin composition is formed between the circuit members 30, 40.

図１３（ａ）及び図１３（ｂ）は、図１２（ａ）及び図１２（ｂ）に示す接続構造体５０Ａの製造方法の変形例を模式的に示す断面図である。この変形例に係る製造方法においては、はんだ粒子１の一部が電極３２,４２の融着に寄与せずに絶縁樹脂層５５内に残存しているものの、異方性導電フィルム１０において特定の位置にはんだ粒子１が配置されているに過ぎず、つまり、はんだ粒子１の密度が十分に低いため、絶縁信頼性を高く維持することができる。13(a) and 13(b) are cross-sectional views that show a schematic diagram of a modified manufacturing method of the connection structure 50A shown in Fig. 12(a) and 12(b). In the manufacturing method according to this modified example, although some of the solder particles 1 do not contribute to the fusion of the electrodes 32, 42 and remain in the insulating resin layer 55, the solder particles 1 are merely arranged at specific positions in the anisotropic conductive film 10, that is, the density of the solder particles 1 is sufficiently low, so that high insulation reliability can be maintained.

図１４（ａ）及び図１４（ｂ）は、図１２（ａ）及び図１２（ｂ）に示す接続構造体５０Ａの製造方法の変形例を模式的に示す断面図である。この変形例に係る製造方法においては、実質的に全てのはんだ粒子１が接合部７０となり、第一の回路部材３０の第一の電極３２と第二の回路部材４０の第二の電極４２を融着している。異方性導電フィルム１０におけるはんだ粒子１の配置をあらかじめ設計することで、融着に寄与せずに残存するはんだ粒子１を極力低減することが可能である。これにより、接続構造体の絶縁信頼性をより一層向上することができる。 Figures 14(a) and 14(b) are cross-sectional views that show a schematic modification of the manufacturing method of the connection structure 50A shown in Figures 12(a) and 12(b). In the manufacturing method of this modification, substantially all of the solder particles 1 become the joints 70, fusing the first electrode 32 of the first circuit member 30 and the second electrode 42 of the second circuit member 40. By designing the arrangement of the solder particles 1 in the anisotropic conductive film 10 in advance, it is possible to minimize the solder particles 1 that remain without contributing to fusion. This can further improve the insulation reliability of the connection structure.

以上、異方性導電フィルム１０を用いて本実施形態の接続構造体を製造する方法について説明したが、本実施形態の接続構造体は、異方性導電フィルムを使用しない方法によって製造してもよい。The above describes a method for manufacturing the connection structure of this embodiment using an anisotropic conductive film 10, but the connection structure of this embodiment may also be manufactured by a method that does not use an anisotropic conductive film.

例えば、本実施形態の接続構造体の製造方法の他の一態様では、第一の回路部材３０の第一の電極３２（又は第二の回路部材４０の第二の電極４２）の表面にはんだバンプを形成し、当該はんだバンプを形成した第一の電極３２（又は第二の電極４２）と第二の電極４２（又は第一の電極３２）とを対向する位置に配置し、加熱加圧して第一の電極３２と第二の電極４２とを接続し、接合部７０を製造してもよい。For example, in another aspect of the manufacturing method of the connection structure of this embodiment, a solder bump may be formed on the surface of the first electrode 32 of the first circuit member 30 (or the second electrode 42 of the second circuit member 40), the first electrode 32 (or the second electrode 42) with the solder bump formed thereon and the second electrode 42 (or the first electrode 32) may be arranged in opposing positions, and the first electrode 32 and the second electrode 42 may be connected by heating and pressurizing to manufacture the joint 70.

はんだバンプを形成する方法は特に限定されないが、例えば、凹部６２のそれぞれにはんだ粒子１が収容された基体６０を準備し、この基体６０の凹部６２の開口側の面に、第一の回路部材３０の第一の電極３２を対向させて配置し、基体の厚み方向に加圧しながら加熱処理することで、第一の電極３２の表面にはんだバンプを形成することができる。同様の方法で、第二の電極４２の表面にはんだバンプを形成することもできる。The method of forming the solder bumps is not particularly limited, but for example, a base 60 having solder particles 1 accommodated in each recess 62 is prepared, and the first electrode 32 of the first circuit member 30 is placed facing the surface of the opening side of the recess 62 of this base 60, and a heat treatment is performed while applying pressure in the thickness direction of the base, thereby forming a solder bump on the surface of the first electrode 32. A solder bump can also be formed on the surface of the second electrode 42 in a similar manner.

加熱処理は、例えば、脱酸素雰囲気又は還元雰囲気で実施することが好ましい。これにより、はんだ粒子の酸化が抑制され、第一の電極３２（又は第二の電極４２）への濡れ拡がりが進みやすくなり、はんだバンプをより確実に第一の電極３２（又は第二の電極４２）の表面に配置することができる。脱酸素雰囲気は、例えば、窒素、アルゴン等の不活性ガス雰囲気、真空状態等であってよい。The heat treatment is preferably carried out in, for example, a deoxidized or reduced atmosphere. This suppresses oxidation of the solder particles, facilitates spreading of the solder particles onto the first electrode 32 (or the second electrode 42), and allows the solder bump to be more reliably positioned on the surface of the first electrode 32 (or the second electrode 42). The deoxidized atmosphere may be, for example, an inert gas atmosphere such as nitrogen or argon, or a vacuum state.

はんだバンプをより確実に第一の電極３２（又は第二の電極４２）の表面に配置する観点から、はんだバンプの形成に際し、フラックス、粘性物質等を使用してもよい。また、これらは第一の電極３２と第二の電極４２との接続を阻害する場合や、はんだバンプ又は電極を酸化又は腐食させる場合があるため、バンプの形成後に、これらを除去する工程があってもよい。From the viewpoint of more reliably placing the solder bump on the surface of the first electrode 32 (or the second electrode 42), flux, viscous substances, etc. may be used when forming the solder bump. In addition, since these may impede the connection between the first electrode 32 and the second electrode 42 or may oxidize or corrode the solder bump or electrode, a process of removing these may be performed after the bump is formed.

第一の電極３２と第二の電極４２との接続は、例えば、脱酸素雰囲気又は還元雰囲気で実施することが好ましい。これにより、はんだ粒子の酸化が抑制され、第一の電極３２及び第二の電極４２への濡れ拡がりが進みやすくなり、より確実に第一の電極３２と第二の電極４２とを接続する接合部７０を形成することができる。脱酸素雰囲気は、例えば、窒素、アルゴン等の不活性ガス雰囲気、真空状態等であってよい。The connection between the first electrode 32 and the second electrode 42 is preferably performed in, for example, a deoxidized or reduced atmosphere. This suppresses oxidation of the solder particles, facilitates spreading of the solder to the first electrode 32 and the second electrode 42, and allows the formation of a joint 70 that connects the first electrode 32 and the second electrode 42 more reliably. The deoxidized atmosphere may be, for example, an inert gas atmosphere such as nitrogen or argon, or a vacuum state.

第一の電極３２と第二の電極４２とをより確実に製造する観点から、接合部７０の形成に際し、フラックス、粘性物質等を使用してもよい。また、これらは、接合部又は電極を酸化又は腐食させる場合、後述する絶縁樹脂層５５の形成に悪影響を与える場合があるため、接合部７０の形成後に、これらを除去する工程があってもよい。From the viewpoint of more reliably manufacturing the first electrode 32 and the second electrode 42, flux, viscous substances, etc. may be used when forming the joint 70. Furthermore, if these substances oxidize or corrode the joint or the electrodes, they may adversely affect the formation of the insulating resin layer 55 described below. Therefore, after the formation of the joint 70, a process of removing these substances may be performed.

接続構造体の製造方法の上記態様では、接合部７０の形成後に、第一の回路部材３０及び第二の回路部材４０の間に絶縁性樹脂材料を注入及び硬化させて、絶縁性樹脂層５５を形成してよい。In the above-described aspect of the method for manufacturing a connection structure, after the joint 70 is formed, an insulating resin material may be injected and cured between the first circuit member 30 and the second circuit member 40 to form an insulating resin layer 55.

接続構造体の製造方法の上記態様では、接合部７０の形成に際し、はんだバンプが形成された第一の電極３２を有する第一の回路部材３０と、第二の電極４２を有する第二の回路部材４０とを、第一の電極３２と第二の電極４２とが対向するように配置し、更に第一の回路部材３０及び第二の回路部材４０の間に絶縁性樹脂フィルムを配置して、厚み方向に加圧しながら加熱処理することで、接合部７０の形成と絶縁樹脂層５５の形成とを同時に行うこともできる。In the above-described aspect of the method for manufacturing a connection structure, when forming the joint 70, a first circuit member 30 having a first electrode 32 on which a solder bump is formed, and a second circuit member 40 having a second electrode 42 are arranged so that the first electrode 32 and the second electrode 42 face each other, and an insulating resin film is further arranged between the first circuit member 30 and the second circuit member 40, and heat treatment is performed while applying pressure in the thickness direction, thereby simultaneously forming the joint 70 and forming the insulating resin layer 55.

図２０、図２１、図２２及び図２３は、押圧及び加熱がなされる前の異方性導電フィルム１０のはんだ粒子１の位置と第一の電極３２の位置との関係を模式的に示す図である。図２０、図２１、図２２及び図２３は、はんだバンプの形成時における、基体６０中のはんだ粒子１の位置と第一の電極３２（又は第二の電極４２）の位置との関係を模式的に示す図、ということもできる。20, 21, 22, and 23 are diagrams that show the relationship between the position of the solder particle 1 on the anisotropic conductive film 10 and the position of the first electrode 32 before pressing and heating. 20, 21, 22, and 23 can also be said to be diagrams that show the relationship between the position of the solder particle 1 in the base 60 and the position of the first electrode 32 (or the second electrode 42) during the formation of the solder bump.

上述の実施形態及びそれらの変形例に係る接続構造体の適用対象としては、半導体メモリー、半導体ロジックチップなどの接続、半導体パッケージの一次実装や二次実装の接続部、ＣＭＯＳ画像素子、レーザー素子、ＬＥＤ発光素子などの接合体や、それらを用いたカメラ、センサー、液晶ディスプレイ、パーソナルコンピュータ、携帯電話、スマートフォン、タブレット等のデバイスが挙げられる。 Applications of the connection structures according to the above-mentioned embodiments and their modified examples include connections of semiconductor memories, semiconductor logic chips, etc., connections for primary and secondary mounting of semiconductor packages, junctions for CMOS imaging elements, laser elements, LED light-emitting elements, etc., and devices using these, such as cameras, sensors, liquid crystal displays, personal computers, mobile phones, smartphones, tablets, etc.

以上、本発明の好適な実施形態について説明したが、本発明は上記実施形態に限定されるものではない。 The above describes a preferred embodiment of the present invention, but the present invention is not limited to the above embodiment.

以下、実施例によって本発明を更に詳細に説明するが、本発明はこれらの実施例に限定されるものではない。The present invention will be described in further detail below with reference to examples, but the present invention is not limited to these examples.

＜はんだ粒子の作製＞
（作製例１）
（工程ａ１）はんだ微粒子の分級
Ｓｎ－Ｂｉはんだ微粒子（５Ｎ Ｐｌｕｓ社製、融点１３９℃、Ｔｙｐｅ８）１００ｇを、蒸留水に浸漬し、超音波分散させた後、静置し、上澄みに浮遊するはんだ微粒子を回収した。この操作を繰り返して、１０ｇのはんだ微粒子を回収した。得られたはんだ微粒子の平均粒子径は１．０μｍ、Ｃ．Ｖ．値は４２％であった。
（工程ｂ１）基体への配置
表１に示す、開口径２．３μｍφ、底部径２．０μｍφ、深さ２．０μｍ（底部径２．０μｍφは、開口を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を複数有する基体（ポリイミドフィルム、厚さ１００μｍ）を準備した。複数の凹部は、１．０μｍの間隔で規則的に配列させた。工程ａで得られたはんだ微粒子（平均粒子径１．０μｍ、Ｃ．Ｖ．値４２％）を基体の凹部に配置した。なお、基体の凹部が形成された面側を微粘着ローラーでこすることで余分なはんだ微粒子を取り除き、凹部内のみにはんだ微粒子が配置された基体を得た。
（工程ｃ１）はんだ粒子の形成
工程ｂ１で凹部にはんだ微粒子が配置された基体を、水素ラジカル還元炉（神港精機株式会社製、プラズマリフロー装置）に投入し、真空引き後、水素ガスを炉内に導入して、炉内を水素ガスで満たした。その後、炉内を１２０℃に調整し、５分間水素ラジカルを照射した。その後、真空引きにて炉内の水素ガスを除去し、１７０℃まで加熱した後、窒素を炉内に導入して大気圧に戻してから炉内の温度を室温まで下げることにより、はんだ粒子を形成した。
（工程ｄ１）はんだ粒子の回収
工程ｃ１を経た基体を凹部裏側よりタップすることで、凹部よりはんだ粒子を回収した。得られたはんだ粒子を、下記の方法で評価した。
＜はんだ粒子の評価＞
ＳＥＭ観察用台座表面に固定した導電テープ上に、得られたはんだ粒子を載せ、厚さ５ｍｍのステンレス板にＳＥＭ観察用台座をタップしてはんだ粒子を導電テープ上に万遍なく広げた。その後、導電テープ表面に圧縮窒素ガスを吹きかけ、はんだ粒子を導電テープ上に単層に固定した。ＳＥＭにてはんだ粒子の直径を３００個測定し、平均粒子径及びＣ．Ｖ．値を算出した。結果を表２に示す。 <Preparation of solder particles>
(Preparation Example 1)
(Step a1) Classification of solder particles 100 g of Sn-Bi solder particles (manufactured by 5N Plus, melting point 139°C, Type 8) were immersed in distilled water, ultrasonically dispersed, and then allowed to stand, and the solder particles floating in the supernatant were collected. This operation was repeated to collect 10 g of solder particles. The average particle size of the obtained solder particles was 1.0 μm, and the CV value was 42%.
(Step b1) Placement on the base A base (polyimide film, thickness 100 μm) having a plurality of recesses with an opening diameter of 2.3 μmφ, a bottom diameter of 2.0 μmφ, and a depth of 2.0 μm (the bottom diameter of 2.0 μmφ is located in the center of the opening diameter of 2.3 μmφ when the opening is viewed from the top) as shown in Table 1 was prepared. The plurality of recesses were regularly arranged at intervals of 1.0 μm. The solder fine particles (average particle diameter 1.0 μm, CV value 42%) obtained in step a were placed in the recesses of the base. In addition, the surface side of the base on which the recesses were formed was rubbed with a slightly adhesive roller to remove excess solder fine particles, and a base in which solder fine particles were placed only in the recesses was obtained.
(Step c1) Formation of solder particles The substrate with the solder particles arranged in the recesses in step b1 was placed in a hydrogen radical reduction furnace (plasma reflow device manufactured by Shinko Seiki Co., Ltd.), and after evacuation, hydrogen gas was introduced into the furnace to fill the furnace with hydrogen gas. The furnace was then adjusted to 120°C and irradiated with hydrogen radicals for 5 minutes. After that, the hydrogen gas in the furnace was removed by evacuation, and the furnace was heated to 170°C, and nitrogen was introduced into the furnace to return it to atmospheric pressure, and the temperature in the furnace was then lowered to room temperature to form solder particles.
(Step d1) Collection of Solder Particles The substrate that had been subjected to step c1 was tapped from the rear side of the recessed portion to collect the solder particles from the recessed portion. The obtained solder particles were evaluated by the following method.
<Evaluation of solder particles>
The obtained solder particles were placed on a conductive tape fixed to the surface of a SEM observation pedestal, and the SEM observation pedestal was tapped onto a 5 mm thick stainless steel plate to spread the solder particles evenly on the conductive tape. Compressed nitrogen gas was then sprayed onto the surface of the conductive tape to fix the solder particles in a single layer on the conductive tape. The diameter of 300 solder particles was measured using an SEM, and the average particle diameter and C.V. value were calculated. The results are shown in Table 2.

（作製例２～６）
凹部のサイズを表１に記載のとおり変更したこと以外は、作製例１と同様にしてはんだ粒子を作製し、評価した。結果を表２に示す。 (Preparation Examples 2 to 6)
Solder particles were produced and evaluated in the same manner as in Production Example 1, except that the size of the recesses was changed as shown in Table 1. The results are shown in Table 2.

＜実施例１＞
（Ａ）異方性導電フィルムの作製
（工程ｅ１）フラックスコートはんだ粒子の製造
作製例１と同じ方法ではんだ粒子を作製した。得られたはんだ粒子２０ｇと、アジピン酸４ｇと、アセトン７ｇとを３つ口フラスコに秤量し、次にはんだ粒子表面の水酸基とアジピン酸のカルボキシル基との脱水縮合反応を触媒するジブチルスズオキシド０．０３ｇを添加し、６０℃で４時間反応させた。その後、はんだ粒子を濾過して回収した。回収したはんだ粒子と、アジピン酸５ｇと、トルエン２０ｇと、パラトルエンスルホン酸０．０３ｇとを３つ口フラスコに秤量し、真空引き、及び還流を行いながら、１２０℃で、３時間反応させた。この際、ディーンスターク抽出装置を用いて、脱水縮合により生成した水を除去しながら反応させた。その後、濾過によりはんだ粒子を回収し、ヘキサンにて洗浄し、乾燥した。乾燥後のはんだ粒子を気流式解砕機で解砕し、音波篩によりメッシュを通すことで、フラックスコートはんだ粒子を得た。
（工程ｆ１）フラックスコートはんだ粒子の配置
開口径２．３μｍφ、底部径２．０μｍφ、深さ２．０μｍ（底部径２．０μｍφは、開口部を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を複数有する転写型（ポリイミドフィルム、厚さ１００μｍ）を準備した。なお、複数の凹部は、１．０μｍの間隔で規則的に配列させた。この転写型の凹部に、それぞれ工程ｅ１で得たフラックスコートはんだ粒子を配置した。
（工程ｇ１）接着フィルムの作製
フェノキシ樹脂（ユニオンカーバイド社製、商品名「ＰＫＨＣ」）１００ｇと、アクリルゴム（ブチルアクリレート４０質量部、エチルアクリレート３０質量部、アクリロニトリル３０質量部、グリシジルメタクリレート３質量部の共重合体、分子量：８５万）７５ｇとを、酢酸エチル４００ｇに溶解し、溶液を得た。この溶液に、マイクロカプセル型潜在性硬化剤を含有する液状エポキシ樹脂（エポキシ当量１８５、旭化成エポキシ株式会社製、商品名「ノバキュアＨＸ－３９４１」）３００ｇを加え、撹拌して接着剤溶液を得た。得られた接着剤溶液を、セパレータ（シリコーン処理したポリエチレンテレフタレートフィルム、厚さ４０μｍ）にロールコータを用いて塗布し、９０℃で１０分間の加熱することにより乾燥して、厚さ２、３、４、１０，１５及び２０μｍの接着フィルム（絶縁樹脂フィルム）をセパレータ上に作製した。
（工程ｈ１）フラックスコートはんだ粒子の転写
セパレータ上に形成された接着フィルムと、工程ｆ１でフラックスコートはんだ粒子が配置された転写型とを向かい合わせて配置し、接着フィルムにフラックスコートはんだ粒子を転写させた。
（工程ｉ１）異方性導電フィルムの作製
工程ｈ１で得た接着フィルムの転写面に、工程ｇ１と同様の方法で作製された接着フィルムを接触させ、５０℃、０．１ＭＰａ（１ｋｇｆ／ｃｍ２）で加熱・加圧させることで、フィルムの断面視において、フラックスコートはんだ粒子が層状に配列された異方性導電フィルムを得た。なお、厚さ２μｍのフィルムに対しては２μｍを重ね合わせ、同様に、３μｍには３μｍ、４μｍには４μｍ、１０μｍには１０μｍ、１５μｍには１５μｍ、２０μｍには２０μｍを重ね合わることで、４μｍ、６μｍ、８μｍ、２０μｍ、３０μｍ及び４０μｍの厚みの異方性導電フィルムを作製した。 Example 1
(A) Preparation of anisotropic conductive film (Step e1) Manufacturing of flux-coated solder particles Solder particles were prepared in the same manner as in Preparation Example 1. 20 g of the obtained solder particles, 4 g of adipic acid, and 7 g of acetone were weighed into a three-necked flask, and then 0.03 g of dibutyltin oxide, which catalyzes the dehydration condensation reaction between the hydroxyl groups on the surface of the solder particles and the carboxyl groups of adipic acid, was added and reacted at 60 ° C. for 4 hours. The solder particles were then collected by filtration. The collected solder particles, 5 g of adipic acid, 20 g of toluene, and 0.03 g of paratoluenesulfonic acid were weighed into a three-necked flask, and reacted at 120 ° C. for 3 hours while evacuating and refluxing. At this time, the reaction was carried out while removing the water generated by the dehydration condensation using a Dean-Stark extraction device. The solder particles were then collected by filtration, washed with hexane, and dried. The dried solder particles were crushed with an airflow crusher and passed through a mesh using an ultrasonic sieve to obtain flux-coated solder particles.
(Step f1) Arrangement of flux-coated solder particles A transfer mold (polyimide film, thickness 100 μm) having multiple recesses with an opening diameter of 2.3 μmφ, a bottom diameter of 2.0 μmφ, and a depth of 2.0 μm (the bottom diameter of 2.0 μmφ is located in the center of the opening diameter of 2.3 μmφ when the opening is viewed from above) was prepared. The multiple recesses were regularly arranged at intervals of 1.0 μm. The flux-coated solder particles obtained in step e1 were arranged in the recesses of this transfer mold.
(Step g1) Preparation of adhesive film 100g of phenoxy resin (manufactured by Union Carbide Corporation, trade name "PKHC") and 75g of acrylic rubber (a copolymer of 40 parts by mass of butyl acrylate, 30 parts by mass of ethyl acrylate, 30 parts by mass of acrylonitrile, and 3 parts by mass of glycidyl methacrylate, molecular weight: 850,000) were dissolved in 400g of ethyl acetate to obtain a solution. 300g of liquid epoxy resin (epoxy equivalent 185, manufactured by Asahi Kasei Epoxy Corporation, trade name "Novacure HX-3941") containing a microcapsule type latent curing agent was added to this solution and stirred to obtain an adhesive solution. The obtained adhesive solution was applied to a separator (a silicone-treated polyethylene terephthalate film, thickness 40 μm) using a roll coater, and dried by heating at 90 ° C. for 10 minutes to prepare adhesive films (insulating resin films) with thicknesses of 2, 3, 4, 10, 15 and 20 μm on the separator.
(Step h1) Transfer of flux-coated solder particles The adhesive film formed on the separator and the transfer mold on which the flux-coated solder particles were arranged in step f1 were placed face-to-face, and the flux-coated solder particles were transferred to the adhesive film.
(Step i1) Preparation of anisotropic conductive film An adhesive film prepared in the same manner as in step g1 was brought into contact with the transfer surface of the adhesive film obtained in step h1, and heated and pressed at 50°C and 0.1 MPa (1 kgf/ cm2 ) to obtain an anisotropic conductive film in which the flux-coated solder particles were arranged in layers in the cross-sectional view of the film. Note that a 2 μm thick film was overlapped with a 2 μm thick film, and similarly, anisotropic conductive films with thicknesses of 4 μm, 6 μm, 8 μm, 20 μm, 30 μm, and 40 μm were prepared by overlapping a 3 μm thick film with a 3 μm thick film, a 4 μm thick film with a 4 μm thick film, a 10 μm thick film with a 10 μm thick film, a 15 μm thick film with a 15 μm thick film, and a 20 μm thick film with a 20 μm thick film.

（Ｂ）接続構造体の作製
（工程ｊ１）評価チップの準備
下記に示す、７種類の金バンプ付きチップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）を準備した。
・チップＣ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：１０μｍ、バンプ数３６２
・チップＣ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：１０μｍ、バンプ数３６２
・チップＣ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：７μｍ、バンプ数３６２
・チップＣ４…面積３０μｍ×３０μｍ、スペース１２μｍ、高さ：６μｍ、バンプ数３６２
・チップＣ５…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：５μｍ、バンプ数３６２
・チップＣ６…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
（工程ｋ１）評価基板の準備
下記に示す、７種類の金バンプ付き基板（７０×２５ｍｍ、厚さ：０．５ｍｍ）を準備した。なお、これらの金バンプには抵抗測定用の引き出し配線も形成されている。
・基板Ｄ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ４…面積３０μｍ×３０μｍ、スペース１２μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ５…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ６…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
（工程ｌ１）
次に、工程ｉ１作製した異方性導電フィルムを用いて、評価チップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）と、評価基板（厚さ：０．５ｍｍ）との接続を、以下に示すｉ）～ｉｉｉ）の手順に従って行うことによって接続構造体を得た。
ｉ）異方性導電フィルム（３．５×１９ｍｍ）の片面のセパレータ（シリコーン処理したポリエチレンテレフタレートフィルム、厚さ４０μｍ）を剥がし、異方性導電フィルムと評価基板を接触させ、８０℃、０．９８ＭＰａ（１０ｋｇｆ／ｃｍ２）で貼り付けた。
ｉｉ）セパレータを剥離し、評価チップのバンプと評価基板のバンプの位置合わせを行った。
ｉｉｉ）１８０℃、４０ｇｆ／バンプ、１０秒の条件でチップ上方から加熱及び加圧を行い、本接続を行った。以下の（１）～（６）の「チップ／異方性導電フィルム／基板」の組み合わせで、（１）～（６）に係る計７種類の接続構造体をそれぞれ作製した。
（１）チップＣ１／４０μｍの厚みの異方性導電フィルム／基板Ｄ１
（２）チップＣ２／３０μｍの厚みの異方性導電フィルム／基板Ｄ２
（３）チップＣ３／２０μｍの厚みの異方性導電フィルム／基板Ｄ３
（４）チップＣ４／８μｍの厚みの異方性導電フィルム／基板Ｄ４
（５）チップＣ５／６μｍの厚みの異方性導電フィルム／基板Ｄ５
（６）チップＣ６／４μｍの厚みの異方性導電フィルム／基板Ｄ６ (B) Fabrication of Connection Structure (Step j1) Preparation of Evaluation Chip Seven types of chips with gold bumps (3.0×3.0 mm, thickness: 0.5 mm) shown below were prepared.
Chip C1: area 100 μm×100 μm, space 40 μm, height: 10 μm, number of bumps 362
Chip C2: area 75 μm×75 μm, space 20 μm, height: 10 μm, number of bumps 362
Chip C3: area 40 μm×40 μm, space 16 μm, height: 7 μm, number of bumps 362
Chip C4: area 30 μm×30 μm, space 12 μm, height: 6 μm, number of bumps 362
Chip C5: area 20 μm×20 μm, space 7 μm, height: 5 μm, number of bumps 362
Chip C6: area 10 μm×10 μm, space 6 μm, height: 3 μm, number of bumps 362
(Step k1) Preparation of Evaluation Substrates Seven types of gold bumped substrates (70×25 mm, thickness: 0.5 mm) were prepared as shown below. Note that these gold bumps also had lead wires formed thereon for resistance measurement.
Substrate D1: area 100 μm×100 μm, space 40 μm, height: 4 μm, number of bumps 362
Substrate D2: area 75 μm×75 μm, space 20 μm, height: 4 μm, number of bumps 362
Substrate D3: area 40 μm×40 μm, space 16 μm, height: 4 μm, number of bumps 362
Substrate D4: area 30 μm×30 μm, space 12 μm, height: 4 μm, number of bumps 362
Substrate D5: area 20 μm×20 μm, space 7 μm, height: 4 μm, number of bumps 362
Substrate D6: area 10 μm×10 μm, space 6 μm, height: 3 μm, number of bumps 362
(Step 11)
Next, using the anisotropic conductive film prepared in step i1, an evaluation chip (3.0 x 3.0 mm, thickness: 0.5 mm) and an evaluation substrate (thickness: 0.5 mm) were connected according to the steps i) to iii) below to obtain a connection structure.
i) The separator (silicone-treated polyethylene terephthalate film, thickness 40 μm) on one side of the anisotropic conductive film (3.5×19 mm) was peeled off, and the anisotropic conductive film was brought into contact with an evaluation substrate and attached at 80° C. and 0.98 MPa (10 kgf/cm 2 ).
ii) The separator was peeled off, and the bumps of the evaluation chip were aligned with the bumps of the evaluation substrate.
iii) Heat and pressure were applied from above the chip at 180°C, 40 gf/bump, and 10 seconds to complete the connection. A total of seven types of connection structures according to (1) to (6) were fabricated using the following combinations of "chip/anisotropic conductive film/substrate."
(1) Chip C1 / 40 μm thick anisotropic conductive film / substrate D1
(2) Chip C2 / 30 μm thick anisotropic conductive film / substrate D2
(3) Chip C3/20 μm thick anisotropic conductive film/substrate D3
(4) Chip C4 / 8 μm thick anisotropic conductive film / substrate D4
(5) Chip C5 / 6 μm thick anisotropic conductive film / substrate D5
(6) Chip C6 / 4 μm thick anisotropic conductive film / substrate D6

＜接続構造体の評価＞
得られた接続構造体の一部について、導通抵抗試験及び絶縁抵抗試験を以下のように行った。
（導通抵抗試験－吸湿耐熱試験）
金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と吸湿耐熱試験（温度８５℃、湿度８５％の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、それらの平均値を算出した。
得られた平均値から下記基準に従って導通抵抗を評価した。結果を表３に示す。なお、吸湿耐熱試験１０００時間後に、下記Ａ又はＢの基準を満たす場合は導通抵抗が良好といえる。
Ａ：導通抵抗の平均値が２Ω未満
Ｂ：導通抵抗の平均値が２Ω以上５Ω未満
Ｃ：導通抵抗の平均値が５Ω以上１０Ω未満
Ｄ：導通抵抗の平均値が１０Ω以上２０Ω未満
Ｅ：導通抵抗の平均値が２０Ω以上 <Evaluation of connection structure>
A conductive resistance test and an insulation resistance test were performed on some of the obtained connection structures as follows.
(Conductive resistance test - Moisture absorption and heat resistance test)
Regarding the conduction resistance between a chip (bump) with gold bumps and a substrate (bump) with gold bumps, the initial conduction resistance value and the value after a moisture absorption and heat resistance test (left for 100, 500, and 1000 hours under conditions of a temperature of 85° C. and a humidity of 85%) were measured for 20 samples, and the average value thereof was calculated.
The conduction resistance was evaluated from the obtained average value according to the following criteria. The results are shown in Table 3. It should be noted that the conduction resistance can be said to be good when the following criteria A or B are satisfied after 1000 hours of the moisture absorption and heat resistance test.
A: The average value of the conductive resistance is less than 2 Ω. B: The average value of the conductive resistance is 2 Ω or more and less than 5 Ω. C: The average value of the conductive resistance is 5 Ω or more and less than 10 Ω. D: The average value of the conductive resistance is 10 Ω or more and less than 20 Ω. E: The average value of the conductive resistance is 20 Ω or more.

（導通抵抗試験－高温放置試験）
金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と高温放置試験（温度１００℃の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定した。なお、高温放置後は、落下衝撃を加え、落下衝撃後のサンプルの導通抵抗を測定した。落下衝撃は、接続構造体を、金属板にネジ止め固定し、高さ５０ｃｍから落下させることで生じさせた。落下後、最も衝撃の大きいチップコーナーのはんだ接合部（４箇所）において直流抵抗値を測定し、測定値が初期抵抗から５倍以上増加したときに破断が生じたとみなして、評価を行った。なお、各サンプルにつき４箇所で、合計８０箇所の測定を行った。結果を表４に示す。落下回数２０回後に下記Ａ又はＢの基準を満たす場合をはんだ接続信頼性が良好であると評価した。
Ａ：初期抵抗から５倍以上増加したはんだ接続部が、０箇所であった。
Ｂ：初期抵抗から５倍以上増加したはんだ接続部が、１箇所以上５箇所以下であった。
Ｃ：初期抵抗から５倍以上増加したはんだ接続部が、６箇所以上２０箇所以下であった。
Ｄ：初期抵抗から５倍以上増加したはんだ接続部が、２１箇所以上であった。 (Conductive resistance test - high temperature storage test)
Regarding the conduction resistance between the gold bumped chip (bump) and the gold bumped substrate (bump), the initial value of the conduction resistance and the value after the high temperature storage test (100, 500, and 1000 hours at a temperature of 100 ° C.) were measured for 20 samples. After high temperature storage, a drop impact was applied, and the conduction resistance of the sample after the drop impact was measured. The drop impact was caused by fixing the connection structure to a metal plate with screws and dropping it from a height of 50 cm. After the drop, the DC resistance value was measured at the solder joint (4 places) of the chip corner that received the greatest impact, and when the measured value increased by 5 times or more from the initial resistance, it was considered that a break occurred, and evaluation was performed. Measurements were performed at 4 places for each sample, for a total of 80 places. The results are shown in Table 4. The solder connection reliability was evaluated as good when the following criteria A or B were met after 20 drops.
A: There were no solder joints where the resistance increased five times or more from the initial resistance.
B: The number of solder joints whose resistance increased by 5 times or more from the initial resistance was 1 to 5.
C: The number of solder joints whose resistance increased by 5 times or more from the initial resistance was 6 or more and 20 or less.
D: There were 21 or more solder connections whose resistance increased by 5 times or more from the initial resistance.

（絶縁抵抗試験）
チップ電極間の絶縁抵抗に関し、絶縁抵抗の初期値とマイグレーション試験（温度６０℃、湿度９０％、２０Ｖ印加の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、全２０サンプル中、絶縁抵抗値が１０９Ω以上となるサンプルの割合を算出した。得られた割合から下記基準に従って絶縁抵抗を評価した。結果を表５に示す。なお、マイグレーション試験１０００時間後に、下記Ａ又はＢの基準を満たした場合は絶縁抵抗が良好といえる。
Ａ：絶縁抵抗値１０９Ω以上の割合が１００％
Ｂ：絶縁抵抗値１０９Ω以上の割合が９０％以上１００％未満
Ｃ：絶縁抵抗値１０９Ω以上の割合が８０％以上９０％未満
Ｄ：絶縁抵抗値１０９Ω以上の割合が５０％以上８０％未満
Ｅ：絶縁抵抗値１０９Ω以上の割合が５０％未満 (Insulation Resistance Test)
Regarding the insulation resistance between the chip electrodes, the initial insulation resistance value and the value after migration testing (left for 100, 500, and 1000 hours under conditions of temperature 60°C, humidity 90%, and 20 V applied) were measured for 20 samples, and the percentage of samples out of all 20 samples with an insulation resistance value of 10 9 Ω or more was calculated. From the obtained percentage, the insulation resistance was evaluated according to the following criteria. The results are shown in Table 5. Note that if the following criteria A or B were met after 1000 hours of migration testing, the insulation resistance can be said to be good.
A: 100% of the samples have an insulation resistance of 10 9 Ω or more.
B: The percentage of insulation resistance values of 10 9 Ω or more is 90% or more and less than 100%. C: The percentage of insulation resistance values of 10 9 Ω or more is 80% or more and less than 90%. D: The percentage of insulation resistance values of 10 9 Ω or more is 50% or more and less than 80%. E: The percentage of insulation resistance values of 10 9 Ω or more is less than 50%.

＜実施例２～６＞
作製例２～６と同じ方法で作製したはんだ粒子を用いたこと、及び、転写型として作製例２～６のはんだ粒子作製に用いた基体と同じ形状の転写型を用いたこと以外は、実施例１と同じ方法で異方導電性フィルム及び接続構造体の作製を行った。 <Examples 2 to 6>
An anisotropic conductive film and a connection structure were prepared in the same manner as in Example 1, except that solder particles prepared in the same manner as in Preparation Examples 2 to 6 were used, and a transfer mold having the same shape as the base used to prepare the solder particles in Preparation Examples 2 to 6 was used as a transfer mold.

＜接続構造体の評価＞
評価に用いた接続構造体を、エポキシ注型樹脂で固めた後、リファインソーで切り出し、研磨紙を用いて、評価チップの金バンプ、はんだ粒子、評価基板の金バンプが見える接続断面部まで研磨した。その後、クライオミリング装置（ＩＢ－１９５２０ＣＣＰ、ＪＥＯＬ製）にて、－１２０℃以下、４．０ｋＶで、接続断面を平坦に加工した。この断面加工部にスパッタによりプラチナ層を５ｎｍ程度形成して、ＳＥＭ観察及びＥＤＸ分析を行った。その結果、実施例２の（５）では、接続構造体を形成した直後は、評価チップの金バンプと評価基板の金バンプとが、一定の距離を保っており、金とスズの合金層を介して接続していることが確認された。また、この合金層に接する位置に、ビスマス部が存在した。断面のＳＥＭ画像を図２５（ａ）、断面のＥＤＸ分析結果を図２５（ｂ）に示す。評価試験後の断面構造は、金とスズの合金層が各金バンプ側に広がっていたものの、試験前と概ね変わらなかった。 <Evaluation of connection structure>
The connection structure used in the evaluation was solidified with epoxy casting resin, cut out with a refiner saw, and polished with abrasive paper to the connection cross section where the gold bumps of the evaluation chip, solder particles, and gold bumps of the evaluation board were visible. Then, the connection cross section was processed flat at -120°C or less and 4.0 kV with a cryo-milling device (IB-19520CCP, manufactured by JEOL). A platinum layer of about 5 nm was formed on this cross section processing section by sputtering, and SEM observation and EDX analysis were performed. As a result, in Example 2 (5), it was confirmed that the gold bumps of the evaluation chip and the gold bumps of the evaluation board maintained a certain distance immediately after the connection structure was formed, and were connected via an alloy layer of gold and tin. In addition, a bismuth part was present at a position in contact with this alloy layer. A SEM image of the cross section is shown in FIG. 25(a), and the EDX analysis result of the cross section is shown in FIG. 25(b). The cross-sectional structure after the evaluation test was largely unchanged from before the test, although the gold-tin alloy layer had spread to each gold bump side.

実施例１～６では、絶縁樹脂部によるはんだ粒子の保持、金バンプ間のギャップ保持があり、適度な加熱時間により、はんだのスズ成分と金との合金化及びビスマスの再配置が進行して、安定した接続構造体が得られるものと考えられる。In Examples 1 to 6, the insulating resin holds the solder particles and maintains the gaps between the gold bumps, and it is believed that an appropriate heating time leads to alloying of the tin component of the solder with the gold and rearrangement of the bismuth, resulting in a stable connection structure.

＜はんだバンプ形成部材の作製＞
（作製例７）
（工程ｍ１）基体の作製
６インチのシリコンウエハ上に、液状感光性レジスト（昭和電工マテリアルズ株式会社製、ＡＨシリーズ）をスピンコート法にて１．５μｍの厚みに塗布した。このシリコンウエハ上の感光性レジストを露光・現像して、開口径２．３μｍφ、底部径２．０μｍφ、深さ１．５μｍ（底部径２．０μｍφは、開口を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を有する基体７を得た。なお、これらの凹部は評価用基板７の電極配置パターンに相対した位置に配置した。また、基体７の表面には、凹部形成と同時に３箇所のアライメントマークを配置した。基体７の概要を表６に示す。 <Preparation of Solder Bump Forming Member>
(Preparation Example 7)
(Step m1) Preparation of substrate A liquid photosensitive resist (Showa Denko Materials Co., Ltd., AH series) was applied to a thickness of 1.5 μm on a 6-inch silicon wafer by spin coating. The photosensitive resist on this silicon wafer was exposed and developed to obtain substrate 7 having a recess with an opening diameter of 2.3 μmφ, a bottom diameter of 2.0 μmφ, and a depth of 1.5 μm (the bottom diameter of 2.0 μmφ is located in the center of the opening diameter of 2.3 μmφ when viewed from above). These recesses were arranged in positions corresponding to the electrode arrangement pattern of evaluation substrate 7. In addition, three alignment marks were arranged on the surface of substrate 7 at the same time as the recesses were formed. An overview of substrate 7 is shown in Table 6.

工程ａ１と同様にはんだ微粒子を得て、基体７を用いたこと以外は工程ｂ１と同様に凹部内にはんだ微粒子を配置し、工程ｃ１により凹部内にはんだ粒子を有したはんだバンプ形成部材７を得た。Solder particles were obtained in the same manner as in process a1, and the solder particles were placed in the recesses in the same manner as in process b1, except that a base 7 was used, and a solder bump forming member 7 having solder particles in the recesses was obtained by process c1.

＜はんだバンプ形成部材の評価＞
はんだバンプ形成部材７の一部を、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、はんだ粒子の直径を３００個測定し、平均粒子径及びＣ．Ｖ．値を算出した。結果を表７に示す。また、はんだバンプ形成部材７の一部の表面形状を、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ ＯＬＳ５０００－ＳＡＦ）を用いて測定し、基体表面からのはんだ粒子の高さを測定し、３００個の平均値を算出した。結果を表７に示す。 <Evaluation of solder bump forming materials>
A part of the solder bump forming member 7 was fixed to the surface of a SEM observation pedestal, and the surface was subjected to platinum sputtering. The diameters of 300 solder particles were measured using the SEM, and the average particle diameter and C.V. value were calculated. The results are shown in Table 7. In addition, the surface shape of a part of the solder bump forming member 7 was measured using a laser microscope (LEXT OLS5000-SAF, manufactured by Olympus Corporation), the height of the solder particles from the substrate surface was measured, and the average value of 300 particles was calculated. The results are shown in Table 7.

（作製例８～１２）
感光性レジストの厚みを表６に示す深さの値に変更し、また凹部サイズも表６に記載のとおり変更し、凹部の配置位置は表６記載の評価用基板の電極配置パターンに相対した位置としたこと以外は、作製例７と同様にしてはんだバンプ形成部材を作製し、評価した。結果を表７に示す。 (Preparation Examples 8 to 12)
A solder bump-forming member was produced and evaluated in the same manner as in Preparation Example 7, except that the thickness of the photosensitive resist was changed to the depth value shown in Table 6, the size of the recess was also changed as shown in Table 6, and the position of the recess was set to a position relative to the electrode arrangement pattern of the evaluation substrate shown in Table 6. The results are shown in Table 7.

＜はんだバンプ付き評価チップの作製＞
（工程ｊ２）評価チップの準備
下記に示す、６種類の金バンプ付きチップ（５×５ｍｍ、厚さ：０．５ｍｍ）を準備した。
チップＣ７…電極サイズ：８μｍ×４μｍ、ピッチ：Ｘ方向１６μｍ、Ｙ方向８μｍ、バンプ数：１８万個
チップＣ８…電極サイズ：１６μｍ×８μｍ、ピッチ：Ｘ方向３２μｍ、Ｙ方向１６μｍ、バンプ数：４．６万個
チップＣ９…電極サイズ：２４μｍ×１２μｍ、ピッチ：Ｘ方向４８μｍ、Ｙ方向２４μｍ、バンプ数：１．５万個
チップＣ１０…電極サイズ：７２μｍ×３６μｍ、ピッチ：Ｘ方向１４４μｍ、Ｙ方向７２μｍ、バンプ数：３４００個
チップＣ１１…電極サイズ：９６μｍ×４８μｍ、ピッチ：Ｘ方向１９２μｍ、Ｙ方向９６μｍ、バンプ数：８５０個
チップＣ１２…電極サイズ：１４０μｍ×７０μｍ、ピッチ：Ｘ方向２８０μｍ、Ｙ方向１４０μｍ、バンプ数：４２０個
（工程ｎ１）はんだバンプ形成
ＦＣ３０００Ｗ（東レエンジニアリング製）のステージにはんだバンプ形成部材７を置き、評価チップＣ８をヘッドに装着してピックアップし、双方のアライメントマークを利用して、はんだバンプ形成部材７の凹部内に配置したはんだ粒子と評価チップＣ８の電極位置合わせを行い、はんだバンプ形成部材７の上に評価チップＣ７を仮置きした。その後、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置き、真空引きの後、ギ酸ガスを充填し、下部熱板を１４５℃に昇温し、１分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放し、評価チップＣ７の電極上にはんだ粒子を転写し、はんだバンプを形成した。 <Preparation of evaluation chip with solder bumps>
(Step j2) Preparation of Evaluation Chips Six types of chips with gold bumps (5×5 mm, thickness: 0.5 mm) shown below were prepared.
Chip C7... Electrode size: 8 μm x 4 μm, pitch: X direction 16 μm, Y direction 8 μm, number of bumps: 180,000 Chip C8... Electrode size: 16 μm x 8 μm, pitch: X direction 32 μm, Y direction 16 μm, number of bumps: 46,000 Chip C9... Electrode size: 24 μm x 12 μm, pitch: X direction 48 μm, Y direction 24 μm, number of bumps: 15,000 Chip C10... Electrode size Chip C11... Electrode size: 96 μm × 48 μm, pitch: X direction 192 μm, Y direction 96 μm, number of bumps: 850 Chip C12... Electrode size: 140 μm × 70 μm, pitch: X direction 280 μm, Y direction 140 μm, number of bumps: 420 (Process n1) Solder bump formation The solder bump forming member 7 was placed on the stage of an FC3000W (manufactured by Toray Engineering), the evaluation chip C8 was attached to the head and picked up, and the alignment marks of both were used to align the solder particles placed in the recesses of the solder bump forming member 7 with the electrodes of the evaluation chip C8, and the evaluation chip C7 was temporarily placed on the solder bump forming member 7. Thereafter, the chip was placed on the lower hot plate of a formic acid reflow furnace (a batch-type vacuum soldering device manufactured by Shinko Seiki Co., Ltd.), and after evacuation, formic acid gas was filled in, and the lower hot plate was heated to 145° C. and heated for 1 minute. Thereafter, the formic acid gas was discharged by evacuation, and nitrogen replacement was performed, the lower hot plate was returned to room temperature, and the furnace was opened to the atmosphere. Solder particles were transferred onto the electrodes of the evaluation chip C7, and solder bumps were formed.

＜はんだバンプの評価＞
工程ｎ１を経て得た評価チップを、３００個の電極に対して、はんだ粒子が転写出来た数（はんだバンプ数）を数え、転写率を算出した。また、はんだバンプの高さをレーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ ＯＬＳ５０００－ＳＡＦ）を用いて測定し、３００個の平均値を算出した。結果を表８に示す。 <Solder bump evaluation>
The number of solder particles transferred (solder bump number) to 300 electrodes of the evaluation chip obtained through step n1 was counted to calculate the transfer rate. The height of the solder bumps was also measured using a laser microscope (LEXT OLS5000-SAF, manufactured by Olympus Corporation) and the average value of 300 bumps was calculated. The results are shown in Table 8.

はんだバンプ形成フィルム８～１２と、評価チップＣ８～Ｃ１２を用いたこと以外は、工程ｎ１と同様にして、はんだバンプ形成を行った。更に、３００個の電極のはんだバンプを評価して、転写率と高さ平均値を算出した。結果を表８に示す。 Solder bump formation was performed in the same manner as in process n1, except that solder bump formation films 8 to 12 and evaluation chips C8 to C12 were used. Furthermore, the solder bumps of 300 electrodes were evaluated, and the transfer rate and average height were calculated. The results are shown in Table 8.

＜接続構造体の作製＞
（工程ｋ２）評価基板の準備
下記に示す、６種類の金バンプ付き評価基板（７０×２５ｍｍ、厚さ：０．５ｍｍ）を準備した。この金バンプは、前述の評価チップＣ７～Ｃ１２の金電極に対向した位置に配置されており、アライメントマークが配されている。また、金バンプの一部には抵抗測定用の引き出し配線も形成されている。
基板Ｄ７…面積８μｍ×４μｍ、ピッチ：Ｘ方向１６μｍ、Ｙ方向８μｍ、高さ：２μｍ、バンプ数：１８万個
基板Ｄ８…面積１６μｍ×８μｍ、ピッチ：Ｘ方向３２μｍ、Ｙ方向１６μｍ、高さ：３μｍ、バンプ数：４．６万個
基板Ｄ９…面積２４μｍ×１２μｍ、ピッチ：Ｘ方向４８μｍ、Ｙ方向２４μｍ、高さ：３μｍ、バンプ数：１．５万個
基板Ｄ１０…面積７２μｍ×３６μｍ、ピッチ：Ｘ方向１４４μｍ、Ｙ方向７２μｍ、高さ：３μｍ、バンプ数：３４００個
基板Ｄ１１…面積９６μｍ×４８μｍ、ピッチ：Ｘ方向１９２μｍ、Ｙ方向９６μｍ、高さ：３μｍ、バンプ数：８５０個
基板Ｄ１２…面積１４０μｍ×７０μｍ、ピッチ：Ｘ方向２８０μｍ、Ｙ方向１４０μｍ、高さ：３μｍ、バンプ数：４２０個
（工程及びｏ１）電極の接合
以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｎ１で作製したはんだバンプ付き評価チップと金バンプ付き評価基板とをはんだバンプを介して接続した。
ｉ）ＦＣ３０００Ｗ（東レエンジニアリング製）のステージに金バンプ付き評価基板Ｄ７を置き、はんだバンプ付き評価チップＣ７をヘッドでピックアップし、双方のアライメントマークを利用して金電極同士を対向させ、はんだバンプ付き評価チップＣ７を金バンプ付き評価基板Ｄ７上に配置し、接合前サンプル７を得た。
ｉｉ）ｉ）で得た接合前サンプル７を、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置いた。
ｉｉｉ）ギ酸真空リフロー炉を作動させ、真空引きの後、ギ酸ガスを充填し、下部熱板を１６０℃に昇温し、５分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放した。評価チップと評価基板の間に粘度を調整したアンダーフィル材（昭和電工マテリアルズ株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で３時間硬化させ、評価チップと評価基板の接続構造体を作製した。接続構造体の作製に用いた各材料の組合せは以下のとおりである。
（７）チップＣ７／はんだバンプ形成部材７／基板Ｄ７
（８）チップＣ８／はんだバンプ形成部材８／基板Ｄ８
（９）チップＣ９／はんだバンプ形成部材９／基板Ｄ９
（１０）チップＣ１０／はんだバンプ形成部材１０／基板Ｄ１０
（１１）チップＣ１１／はんだバンプ形成部材１１／基板Ｄ１１
（１２）チップＣ１２／はんだバンプ形成部材１２／基板Ｄ１２ <Preparation of Connection Structure>
(Step k2) Preparation of Evaluation Boards Six types of evaluation boards with gold bumps (70 x 25 mm, thickness: 0.5 mm) were prepared as shown below. The gold bumps were positioned opposite the gold electrodes of the evaluation chips C7 to C12, and alignment marks were provided. In addition, some of the gold bumps were also formed with lead wires for resistance measurement.
Substrate D7...area 8 μm x 4 μm, pitch: X direction 16 μm, Y direction 8 μm, height: 2 μm, number of bumps: 180,000 Substrate D8...area 16 μm x 8 μm, pitch: X direction 32 μm, Y direction 16 μm, height: 3 μm, number of bumps: 46,000 Substrate D9...area 24 μm x 12 μm, pitch: X direction 48 μm, Y direction 24 μm, height: 3 μm, number of bumps: 15,000 Substrate D10...area 72 μm Substrate D11... Area 96 μm × 48 μm, Pitch: X direction 192 μm, Y direction 96 μm, Height: 3 μm, Number of bumps: 850 Substrate D12... Area 140 μm × 70 μm, Pitch: X direction 280 μm, Y direction 140 μm, Height: 3 μm, Number of bumps: 420 (Step and o1) Bonding of Electrodes According to the following steps i) to iii), the evaluation chip with solder bumps produced in step n1 and the evaluation substrate with gold bumps were connected via solder bumps.
i) Evaluation substrate D7 with gold bumps was placed on the stage of an FC3000W (manufactured by Toray Engineering), evaluation chip C7 with solder bumps was picked up with the head, and the gold electrodes were faced to each other using the alignment marks on both chips. Evaluation chip C7 with solder bumps was then placed on evaluation substrate D7 with gold bumps, and pre-bonding sample 7 was obtained.
ii) The pre-bonding sample 7 obtained in i) was placed on the lower hot plate of a formic acid reflow furnace (batch-type vacuum soldering device manufactured by Shinko Seiki Co., Ltd.).
iii) The formic acid vacuum reflow furnace was operated, and after evacuation, formic acid gas was filled, and the lower hot plate was heated to 160 ° C. and heated for 5 minutes. After that, the formic acid gas was discharged by evacuation, and nitrogen replacement was performed, and the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere. An appropriate amount of viscosity-adjusted underfill material (manufactured by Showa Denko Materials Co., Ltd., CEL series) was placed between the evaluation chip and the evaluation board, and after filling by evacuation, it was cured at 125 ° C. for 3 hours to prepare a connection structure between the evaluation chip and the evaluation board. The combinations of each material used in the preparation of the connection structure are as follows.
(7) Chip C7 / solder bump forming member 7 / substrate D7
(8) Chip C8 / solder bump forming member 8 / substrate D8
(9) Chip C9 / solder bump forming member 9 / substrate D9
(10) Chip C10 / solder bump forming member 10 / substrate D10
(11) Chip C11 / solder bump forming member 11 / substrate D11
(12) Chip C12/solder bump forming member 12/substrate D12

＜接続構造体の評価＞
得られた接続構造体の一部について、前述同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表９、表１０及び表１１に示す。 <Evaluation of connection structure>
The results are shown in Tables 9, 10 and 11.

＜作製例１３～１８＞
工程ｍ１の基体の作製及び工程ｊ２の評価チップの準備、更に、工程ｎ１のはんだバンプ形成を経て、表８に示すはんだバンプ形成済みの評価チップＣ７～Ｃ１２を得た。 <Preparation Examples 13 to 18>
Through the production of a substrate in step m1, the preparation of an evaluation chip in step j2, and further the formation of solder bumps in step n1, the evaluation chips C7 to C12 with the solder bumps formed thereon shown in Table 8 were obtained.

＜接続構造体の作製＞
以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｎ１で作製したはんだバンプ付き評価チップと工程ｋ２で準備した金バンプ付き評価基板とをはんだバンプを介して接続した。
ｉ）金バンプ付き評価基板をスピンコータにセットし、液状フラックス（ＮＳ－３３４、日本スペリア社製）を金バンプ面側にコートした。
ｉｉ）ｉ）で得た金バンプ付き評価基板をＦＣ３０００Ｗ（東レエンジニアリング製）のステージに置き、はんだバンプ付き評価チップをヘッドでピックアップし、双方のアライメントマークを利用して金電極同士を対向させ、はんだバンプ付き評価チップを金バンプ付き評価基板上に配置し、接合前サンプル１３～１８を得た。
ｉｉｉ）接合前サンプルを、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置いた。
ｉｖ）ギ酸真空リフロー炉を作動させ、真空引きの後、窒素ガスを充填し、下部熱板を１６０℃に昇温し、３分加熱した。その後、真空引きした後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放した。
ｖ）接合サンプルをイソプロピルアルコール液内に浸してフラックス残渣を洗い流した。
ｖｉ）評価チップと評価基板の間に粘度を調整したアンダーフィル材（昭和電工マテリアルズ株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で３時間硬化させ、評価チップと評価基板の接続構造体を作製した。接続構造体の作製に用いた各材料の組合せは以下のとおりである。
（１３）チップＣ７／はんだバンプ形成部材７／基板Ｄ７
（１４）チップＣ８／はんだバンプ形成部材８／基板Ｄ８
（１５）チップＣ９／はんだバンプ形成部材９／基板Ｄ９
（１６）チップＣ１０／はんだバンプ形成部材１０／基板Ｄ１０
（１７）チップＣ１１／はんだバンプ形成部材１１／基板Ｄ１１
（１８）チップＣ１２／はんだバンプ形成部材１２／基板Ｄ１２
＜接続構造体の評価＞
得られた接続構造体の一部について、前述同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表１２、表１３及び表１４に示す。 <Preparation of Connection Structure>
According to the following steps i) to iii), the evaluation chip with solder bumps produced in step n1 and the evaluation substrate with gold bumps prepared in step k2 were connected via solder bumps.
i) The evaluation substrate with gold bumps was set on a spin coater, and the gold bump surface was coated with liquid flux (NS-334, manufactured by Nippon Superior Co., Ltd.).
ii) The evaluation substrate with gold bumps obtained in i) was placed on the stage of an FC3000W (manufactured by Toray Engineering), the evaluation chip with solder bumps was picked up by the head, and the gold electrodes were faced to each other using the alignment marks on both chips. The evaluation chip with solder bumps was then placed on the evaluation substrate with gold bumps, and pre-bonding samples 13 to 18 were obtained.
iii) The pre-bonded sample was placed on the lower heating plate of a formic acid reflow furnace (batch-type vacuum soldering device manufactured by Shinko Seiki Co., Ltd.).
iv) The formic acid vacuum reflow furnace was operated, and after evacuation, nitrogen gas was filled in, and the lower heating plate was heated to 160° C. and heated for 3 minutes. After that, the furnace was evacuated, and nitrogen replacement was performed, the lower heating plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere.
v) The bonded samples were immersed in isopropyl alcohol to wash away any flux residue.
vi) An appropriate amount of viscosity-adjusted underfill material (CEL series, manufactured by Showa Denko Materials Co., Ltd.) was placed between the evaluation chip and the evaluation substrate, filled by vacuum drawing, and then cured at 125° C. for 3 hours to prepare a connection structure between the evaluation chip and the evaluation substrate. The combination of each material used in the preparation of the connection structure is as follows.
(13) Chip C7 / solder bump forming member 7 / substrate D7
(14) Chip C8 / solder bump forming member 8 / substrate D8
(15) Chip C9 / solder bump forming member 9 / substrate D9
(16) Chip C10 / solder bump forming member 10 / substrate D10
(17) Chip C11 / solder bump forming member 11 / substrate D11
(18) Chip C12 / solder bump forming member 12 / substrate D12
<Evaluation of connection structure>
The results are shown in Tables 12, 13 and 14.

１…はんだ粒子、２…絶縁性フィルム、２ａ…絶縁性樹脂材料、２ｂ…第一の樹脂層、２ｃ…第一の樹脂層の表面、２ｄ…第二の樹脂層、１０…異方性導電フィルム、３０…第一の回路部材、３１…第一の回路基板、３２…第一の電極、４０…第二の回路部材、４１…第二の回路基板、４２…第二の電極、５５…絶縁樹脂層、６０…基体、６２…凹部、７０…接合部、７１…第一の領域、７２…第二の領域、８０…中間層、１１１…はんだ微粒子。 1...solder particles, 2...insulating film, 2a...insulating resin material, 2b...first resin layer, 2c...surface of first resin layer, 2d...second resin layer, 10...anisotropic conductive film, 30...first circuit member, 31...first circuit board, 32...first electrode, 40...second circuit member, 41...second circuit board, 42...second electrode, 55...insulating resin layer, 60...base, 62...recess, 70...joint, 71...first region, 72...second region, 80...intermediate layer, 111...solder particles.

Claims (6)

第一の電極を複数有する第一の回路部材と、
第二の電極を複数有する第二の回路部材と、
前記第一の電極と前記第二の電極とを電気的に接続する接合部を複数有する中間層と、
を備え、
前記接合部で接続される前記第一の電極及び前記第二の電極の少なくとも一方が金電極であり、
複数の前記接合部のうち９０％以上が、前記第一の電極と前記第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む、
接続構造体。 a first circuit member having a plurality of first electrodes;
a second circuit member having a plurality of second electrodes;
an intermediate layer having a plurality of joints electrically connecting the first electrode and the second electrode;
Equipped with
At least one of the first electrode and the second electrode connected at the junction is a gold electrode;
At least 90% of the plurality of joints include a first region containing a tin-gold alloy connecting the first electrode and the second electrode, and a second region containing bismuth in contact with the first region.
Connection structure. 前記中間層が、前記第一の回路部材と前記第二の回路部材との間を封止する絶縁性樹脂層を更に有する、請求項１に記載の接続構造体。The connection structure according to claim 1, wherein the intermediate layer further has an insulating resin layer that seals between the first circuit member and the second circuit member. 第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、異方性導電フィルムと、を準備する準備工程と、
前記第一の回路部材、前記第二の回路部材及び前記異方性導電フィルムを、前記第一の回路部材の前記第一の電極を有する面と前記第二の回路部材の前記第二の電極を有する面とが前記異方性導電フィルムを介して対向するように配置して、前記第一の回路部材、前記異方性導電フィルム及び前記第二の回路部材がこの順で積層した積層体を得る配置工程と、
前記積層体を厚み方向に押圧した状態で加熱することにより、前記第一の電極と前記第二の電極とを接合部を介して電気的に接続する接続工程と、
を含み、
前記第一の電極及び前記第二の電極のうち少なくとも一方が金電極であり、
前記異方性導電フィルムが、絶縁性樹脂組成物から構成される絶縁性フィルムと、前記絶縁性フィルム中に配置されている複数のはんだ粒子とを含み、
前記はんだ粒子がスズ－ビスマス合金を含有し、前記はんだ粒子の平均粒子径が１μｍ～３０μｍであり、前記はんだ粒子のＣ．Ｖ．値が２０％以下であり、
前記異方性導電フィルムの縦断面において、前記はんだ粒子が隣接する前記はんだ粒子と離隔した状態で横方向に並ぶように配置されており、
前記接続工程で形成される複数の前記接合部のうち９０％以上が、前記第一の電極と前記第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域と接する、ビスマスを含有する第二の領域と、を含む、
接続構造体の製造方法。 a preparation step of preparing a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and an anisotropic conductive film;
an arrangement step of arranging the first circuit member, the second circuit member, and the anisotropic conductive film such that a surface of the first circuit member having the first electrode and a surface of the second circuit member having the second electrode face each other via the anisotropic conductive film to obtain a laminate in which the first circuit member, the anisotropic conductive film, and the second circuit member are laminated in this order;
a connecting step of electrically connecting the first electrode and the second electrode via a joint by heating the laminate while being pressed in a thickness direction;
Including,
At least one of the first electrode and the second electrode is a gold electrode;
the anisotropic conductive film includes an insulating film made of an insulating resin composition and a plurality of solder particles disposed in the insulating film;
The solder particles contain a tin-bismuth alloy, the average particle size of the solder particles is 1 μm to 30 μm, and the CV value of the solder particles is 20% or less;
In a longitudinal section of the anisotropic conductive film, the solder particles are arranged so as to be spaced apart from adjacent solder particles and aligned in a lateral direction,
90% or more of the joints formed in the connecting step include a first region containing a tin-gold alloy connecting the first electrode and the second electrode, and a second region containing bismuth in contact with the first region.
A method for manufacturing a connection structure. 前記はんだ粒子が、
複数の凹部を有する基体と、スズ－ビスマス合金を含有するはんだ微粒子と、を準備するはんだ微粒子準備工程と、
前記はんだ微粒子の少なくとも一部を、前記凹部に収容する収容工程と、
前記凹部に収容された前記はんだ微粒子を融合させて、前記凹部の内部にはんだ粒子を形成する融合工程と、
を含む方法により製造されたはんだ粒子である、請求項３に記載の製造方法。 The solder particles are
a solder particle preparation step of preparing a base having a plurality of recesses and solder particles containing a tin-bismuth alloy;
a receiving step of receiving at least a portion of the solder particles in the recess;
a fusing step of fusing the solder particles contained in the recesses to form solder particles inside the recesses;
The method of claim 3 , wherein the solder particles are produced by a method comprising the steps of: 前記はんだ微粒子準備工程で準備される前記はんだ微粒子のＣ．Ｖ．値が２０を超える、請求項４に記載の製造方法。The manufacturing method according to claim 4, wherein the C.V. value of the solder particles prepared in the solder particle preparation step exceeds 20. 前記異方性導電フィルムが、
前記はんだ粒子が収容された凹部を複数有する基体の、前記凹部の開口側に絶縁性樹脂組成物を接触させて、前記はんだ粒子が転写された第一の樹脂層を得る転写工程と、
前記はんだ粒子が転写された側の前記第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、
を含む方法により製造された異方性導電フィルムである、請求項３～５のいずれか一項に記載の製造方法。 The anisotropic conductive film is
a transfer step of contacting an insulating resin composition with an opening side of a substrate having a plurality of recesses in which the solder particles are accommodated, to obtain a first resin layer to which the solder particles are transferred;
a lamination step of forming a second resin layer made of an insulating resin composition on the surface of the first resin layer on the side to which the solder particles are transferred, thereby obtaining an anisotropic conductive film;
The method according to any one of claims 3 to 5, wherein the anisotropic conductive film is produced by a method comprising the steps of:
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