JP7447480B2 - 電子回路、半導体モジュール及び半導体装置 - Google Patents
電子回路、半導体モジュール及び半導体装置 Download PDFInfo
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- JP7447480B2 JP7447480B2 JP2019232117A JP2019232117A JP7447480B2 JP 7447480 B2 JP7447480 B2 JP 7447480B2 JP 2019232117 A JP2019232117 A JP 2019232117A JP 2019232117 A JP2019232117 A JP 2019232117A JP 7447480 B2 JP7447480 B2 JP 7447480B2
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- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Description
(1)経路を構成するボンディングワイヤ(以下「第1の導電性ワイヤ」と記す。)は、当該経路よりも順方向電圧が高いショットキバリアダイオードが配置された経路を構成するボンディングワイヤ(以下「第2の導電性ワイヤ」と記す。)よりも全長が長い、
(2)第1の導電性ワイヤは、第2の導電性ワイヤよりも断面積が小さい、
(3)経路を構成する配線パターン(以下「第1の配線パターン」と記す。)は、当該経路よりも順方向電圧が高いショットキバリアダイオードが配置された経路を構成する配線パターン(以下「第2の配線パターン」と記す。)よりも全長が長い、
(4)第1の配線パターンは、第2の配線パターンよりも断面積が小さい。
(L1A+L1B)-(L2A+L2B)=2Y×β/α(nH:ナノヘンリー)・・・(3)
(1)前記第1の導電性ワイヤは、前記第2の導電性ワイヤよりも全長が長い、
(2)前記第1の導電性ワイヤは、前記第2の導電性ワイヤよりも断面積が小さい。
(3)前記第1の配線パターンは、前記第2の配線パターンよりも全長が長い、
(4)前記第1の配線パターンは、前記第2の配線パターンよりも断面積が小さい。
2 :積層基板
10 :ベース板
12 :ケース部材
13,14 :端子部材
20 :絶縁層
21 :第1回路板
22 :第2回路板
23 :第3回路板
31 :P端子(正電位点)
32 :U端子(中間電位点)
33 :N端子(負電位点)
BD1~BD8 :ダイオード
BW1~BW8 :ボンディングワイヤ
L1A~L8A,L1B~L8B :インダクタンス
MOS1~MOS8 :スイッチング素子
P1~P8 :経路
SBD1~SBD8 :ダイオード
T1~T8 :電極
W1A~W8A,W1B~W8B :配線部材
Claims (11)
- 第1のダイオードと、前記第1のダイオードよりも順方向電圧が高い第2のダイオードを含む、複数のダイオードが並列に接続された電子回路であって、
第1端子から前記第1のダイオードを経由して第2端子に至る第1経路のインダクタンスが、前記第1端子から前記第2のダイオードを経由して前記第2端子に至る第2経路のインダクタンスよりも大きい、電子回路。 - 前記複数のダイオードの各々を経由する、前記第1端子から前記第2端子までの各経路は、順方向電圧が低いダイオードを経由する経路ほどインダクタンスが大きい、請求項1に記載の電子回路。
- 前記インダクタンスは、アノード側のインダクタンスである、請求項1又は請求項2に記載の電子回路。
- 第1のダイオードと、前記第1のダイオードよりも順方向電圧が高い第2のダイオードを含む、複数のダイオードが並列に接続された電子回路を有する半導体モジュールであって、
第1端子から前記第1のダイオードを経由して第2端子に至る第1経路をなす配線部材のインダクタンスが、前記第1端子から前記第2のダイオードを経由して前記第2端子に至る第2経路をなす配線部材のインダクタンスよりも大きい、半導体モジュール。 - 前記電子回路が実装された基板を備え、
前記第1経路の配線部材は、前記基板に配置された前記第1端子又は前記第2端子と前記第1のダイオードとを接続する第1の導電性ワイヤを含み、
前記第2経路の配線部材は、前記基板に配置された前記第1端子又は前記第2端子と前記第2のダイオードとを接続する第2の導電性ワイヤを含み、
前記第1の導電性ワイヤのインダクタンスが、前記第2の導電性ワイヤのインダクタンスよりも大きい、請求項4に記載の半導体モジュール。 - 次の条件(1)~(2)の少なくとも1つを満たす、
(1)前記第1の導電性ワイヤは、前記第2の導電性ワイヤよりも全長が長い、
(2)前記第1の導電性ワイヤは、前記第2の導電性ワイヤよりも断面積が小さい、請求項5に記載の半導体モジュール。 - 前記電子回路が実装された基板を備え、
前記第1経路の配線部材は、前記基板に配置された前記第1端子又は前記第2端子と前記第1のダイオードとを接続する第1の配線パターンを含み、
前記第2経路の配線部材は、前記基板に配置された前記第1端子又は前記第2端子と前記第2のダイオードとを接続する第2の配線パターンを含み、
前記第1の配線パターンのインダクタンスが、前記第2の配線パターンのインダクタンスよりも大きい、請求項4に記載の半導体モジュール。 - 次の条件(3)~(4)の少なくとも1つを満たす、
(3)前記第1の配線パターンは、前記第2の配線パターンよりも全長が長い、
(4)前記第1の配線パターンは、前記第2の配線パターンよりも断面積が小さい、請求項7に記載の半導体モジュール。 - 前記複数のダイオードは、同一構造を有するダイオードである、請求項4から請求項8のいずれかに記載の半導体モジュール。
- 前記複数のダイオードは、炭化ケイ素(SiC)を用いて作成されたダイオードである、請求項4から請求項9のいずれかに記載の半導体モジュール。
- 請求項4から請求項10のいずれかに記載の半導体モジュールであって、一対の端子間に並列に接続された複数の半導体モジュールを備え、
前記複数の半導体モジュールの各々を経由する、前記一対の端子の一方から前記一対の端子の他方までの各経路は、順方向電圧が低い半導体モジュールを経由する経路ほどインダクタンスが大きい、半導体装置。
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