JP7435415B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP7435415B2 JP7435415B2 JP2020190395A JP2020190395A JP7435415B2 JP 7435415 B2 JP7435415 B2 JP 7435415B2 JP 2020190395 A JP2020190395 A JP 2020190395A JP 2020190395 A JP2020190395 A JP 2020190395A JP 7435415 B2 JP7435415 B2 JP 7435415B2
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- electrode
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- insulating substrate
- semiconductor device
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Description
図1は、実施の形態1に係る半導体装置を示す断面図である。絶縁基板1は、絶縁板2と、絶縁板2の下面の金属パターン3と、絶縁板2の上面の回路パターン4,5とを有する。絶縁板2は、AlN又はSiNなどのセラミックであり、樹脂絶縁でもよい。
図6は、実施の形態2に係る半導体装置を示す断面図である。ケース11は、絶縁基板1及び半導体素子8を囲む四角い枠である外壁11aと、外壁11aから外壁11aの内側に突出した突出部11bとを有する。外壁11aの内側に引き出された電極12の接続部12cは上方向に変位するが、突出部11bの下面に接触して押し下げられる。これにより、電極12は回路パターン4に押接される力を受ける。これにより、実施の形態1と同様に、温度サイクル時の反りにより電極12と回路パターン4の接合部に生じる引張応力を減少させることができる。
図9は、実施の形態3に係る半導体装置を示す断面図である。ケース11は絶縁基板1に直接的に接着され、固定されている。その他の構成は実施の形態1と同様である。この場合でも電極12,13はケース11により回路パターン4,5に押接され、実施の形態1と同様の効果を得ることができる。
図10は、実施の形態4に係る半導体装置を示す断面図である。図11は図10のI-IIに沿った拡大断面図である。回路パターン4に凹部16が設けられている。凹部16は、回路パターン4を貫通して絶縁板2まで達している必要はない。突起12dは凹部16に嵌合されている。これにより、回路パターン4とはんだ14の接合領域が増加するため、接合の信頼性が向上する。
図12は、実施の形態5に係る半導体装置を示す断面図である。他の電極17が電極12に対して平行に配置されている。電流の向きが逆である2つの電極12,17を近接して平行に配置すると、互いに磁界を打ち消し合うため、インダクタンスを低減することができる。また、2つの電極12,17が同電位の場合は電極密度を増加させることができるため、通電能力が向上する。
図13は、実施の形態6に係る電極の立ち上がり部を示す側面図である。電極12の立ち上がり部12bの側面に切れ込み12eが設けられている。切れ込み12eで電極12の剛性が低下する。従って、電極12の変形によるはんだ14への応力が減少するため、はんだ接合の信頼性が向上する。
Claims (13)
- 回路パターンを有する絶縁基板と、
前記絶縁基板の上に実装され、前記回路パターンに電気的に接続された半導体素子と、
前記絶縁基板及び前記半導体素子を収容するケースと、
前記ケースに設けられた電極とを備え、
前記電極の先端面が前記回路パターンにはんだ接合され、
前記電極は前記ケースにより前記回路パターンに押接され、
前記先端面に突起が設けられ、
前記電極は、前記ケースに固定された固定部と、前記回路パターンの上に立ち上がっている立ち上がり部とを有し、
前記電極の前記立ち上がり部の上端の高さは前記固定部の高さよりも高いことを特徴とする半導体装置。 - 回路パターンを有する絶縁基板と、
前記絶縁基板の上に実装され、前記回路パターンに電気的に接続された半導体素子と、
前記絶縁基板及び前記半導体素子を収容するケースと、
前記ケースに設けられた電極とを備え、
前記電極の先端面が前記回路パターンにはんだ接合され、
前記電極は前記ケースにより前記回路パターンに押接され、
前記先端面に突起が設けられ、
前記ケースは、前記絶縁基板及び前記半導体素子を囲む外壁と、前記外壁から前記外壁の内側に突出した突出部とを有し、
前記電極は、前記突出部の下面に接触して押し下げられることで前記回路パターンに押接される力を受けることを特徴とする半導体装置。 - 回路パターンを有する絶縁基板と、
前記絶縁基板の上に実装され、前記回路パターンに電気的に接続された半導体素子と、
前記絶縁基板及び前記半導体素子を収容するケースと、
前記ケースに設けられた電極とを備え、
前記電極の先端面が前記回路パターンにはんだ接合され、
前記電極は前記ケースにより前記回路パターンに押接され、
前記先端面に突起が設けられ、
前記突起は2つ以上であることを特徴とする半導体装置。 - 回路パターンを有する絶縁基板と、
前記絶縁基板の上に実装され、前記回路パターンに電気的に接続された半導体素子と、
前記絶縁基板及び前記半導体素子を収容するケースと、
前記ケースに設けられた電極とを備え、
前記電極の先端面が前記回路パターンにはんだにより接合され、
前記電極は前記ケースにより前記回路パターンに押接され、
前記先端面に突起が設けられ、
前記電極が接合された前記回路パターンに前記半導体素子又は配線が接合され、
前記電極と前記回路パターンの接合部から前記回路パターンの端部、前記半導体素子又は前記配線までの距離が前記はんだの高さ以上であることを特徴とする半導体装置。 - ベース板を更に備え、
前記絶縁基板は前記ベース板の上面に接合され、
前記ケースは前記ベース板の上面に接着されていることを特徴とする請求項1~4の何れか1項に記載の半導体装置。 - 前記ケースは前記絶縁基板に直接的に接着されていることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- 前記回路パターンに凹部が設けられ、
前記突起は前記凹部に嵌合されていることを特徴とする請求項1~6の何れか1項に記載の半導体装置。 - 前記電極に平行に配置された他の電極を更に備えることを特徴とする請求項1~7の何れか1項に記載の半導体装置。
- 前記突起は前記先端面の外周部に設けられていないことを特徴とする請求項1~8の何れか1項に記載の半導体装置。
- 前記電極の前記立ち上がり部の側面に切れ込みが設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記電極の前記立ち上がり部の厚みが部分的に薄くなっていることを特徴とする請求項1に記載の半導体装置。
- 前記絶縁基板、前記半導体素子及び前記電極を封止する樹脂を更に備えることを特徴とする請求項1~11の何れか1項に記載の半導体装置。
- 前記半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~12の何れか1項に記載の半導体装置。
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