JP7352753B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP7352753B2 JP7352753B2 JP2022557280A JP2022557280A JP7352753B2 JP 7352753 B2 JP7352753 B2 JP 7352753B2 JP 2022557280 A JP2022557280 A JP 2022557280A JP 2022557280 A JP2022557280 A JP 2022557280A JP 7352753 B2 JP7352753 B2 JP 7352753B2
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- Japan
- Prior art keywords
- conductive
- semiconductor element
- semiconductor
- input terminal
- semiconductor module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000015572 biosynthetic process Effects 0.000 description 2
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- Inverter Devices (AREA)
Description
厚さ方向の一方側を向く主面、および前記主面とは反対側を向く裏面を有する導電基板と、
前記主面に電気的に接合され、スイッチング機能を有する半導体素子と、
前記半導体素子によってスイッチングされる主回路電流の経路を構成する導通部材と、
前記導電基板に対し、前記厚さ方向に対して直角である第1方向の一方側に配置された第1入力端子、第2入力端子、および第3入力端子と、
前記導電基板に対して前記第1方向の他方側に配置された出力端子と、を備え、
前記導電基板は、第1導電部および第2導電部を含み、
前記半導体素子は、前記第1導電部に電気的に接合された第1半導体素子と、前記第2導電部に電気的に接合された第2半導体素子と、を含み、
前記第2入力端子および前記第3入力端子は、前記第1入力端子を挟んで、前記厚さ方向および前記第1方向の双方に直角である第2方向の一方側および他方側に配置されており、
前記第1入力端子は正極と負極とのうちの一方の極であり、かつ前記第1導電部に電気的に接続されており、
前記第2入力端子および前記第3入力端子は正極と負極とのうちの他方の極である、半導体モジュール。
付記2.
前記第1入力端子は、前記第1導電部に電気的に接続されており、
前記出力端子は、前記第2導電部に電気的に接続されており、
前記導通部材は、前記第1半導体素子と前記第2導電部とに接続された第1導通部材と、前記第2半導体素子と前記第2入力端子および前記第3入力端子とに接続され、かつ前記厚さ方向に見て前記第1半導体素子と重なる第2導通部材と、を含む、付記1に記載の半導体モジュール。
付記3.
前記第1導電部および前記第2導電部は、前記第1方向一方側および前記第1方向他方側に配置されており、
前記第2導通部材は、前記第2入力端子に接続され、かつ前記第1方向に延びる第1配線部と、前記第3入力端子に接続され、かつ前記第1方向に延びる第2配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第2方向に延びており、前記第2半導体素子に接続される第3配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第3配線部に対して前記第1方向一方側に位置し、前記厚さ方向に見て前記第1半導体素子と重なる第4配線部と、を含む、付記2に記載の半導体モジュール。
付記4.
前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くソース電極および前記厚さ方向他方側を向くドレイン電極をそれぞれ有しており、
前記第1導通部材は、前記第1半導体素子の前記ソース電極に接続されており、
前記第1導電部は、前記第1半導体素子の前記ドレイン電極に接続されており、
前記第3配線部は、前記第2半導体素子の前記ソース電極に接続されており、
前記第2導電部は、前記第2半導体素子の前記ドレイン電極に接続されている、付記3に記載の半導体モジュール。
付記5.
前記第1半導体素子と前記第2半導体素子とは、前記第1方向に見て互いに重なる、付記4に記載の半導体モジュール。
付記6.
前記第4配線部は、第1帯状部および第2帯状部を有し、
前記第1帯状部は、前記第1方向において前記第3配線部と離間し、かつ前記第1配線部および前記第2配線部の双方に繋がって前記第2方向に延びており、前記厚さ方向に見て前記第1半導体素子と重なっており、
前記第2帯状部は、前記厚さ方向に見て、一端が前記第1帯状部に対して互いに隣接する前記第1半導体素子の間に繋がり、かつ他端が前記第3配線部に対して互いに隣接する前記第2半導体素子の間において繋がる、付記5に記載の半導体モジュール。
付記7.
前記第1帯状部は、前記厚さ方向に見て前記第1半導体素子と重なり、他の部位よりも前記厚さ方向一方側に突き出た凸状領域を有する、付記6に記載の半導体モジュール。
付記8.
前記第3配線部は、他の部位よりも前記厚さ方向他方側に突き出た凹状領域を有し、
前記凹状領域は、前記第2半導体素子と接合されている、付記3ないし7のいずれかに記載の半導体モジュール。
付記9.
前記第1半導体素子および前記第2半導体素子を制御するための第1制御端子および第2制御端子を備え、
前記第1制御端子および前記第2制御端子は、各々、前記主面上に配置され、かつ前記厚さ方向に沿って延びる、付記3ないし8のいずれかに記載の半導体モジュール。
付記10.
前記第1制御端子は、前記第1導電部に支持され、かつ前記第1半導体素子よりも前記第1方向一方側に配置されており、
前記第2制御端子は、前記第2導電部に支持され、かつ前記第2半導体素子よりも前記第1方向他方側に配置されている、付記9に記載の半導体モジュール。
付記11.
前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くゲート電極をそれぞれ有しており、
前記第1制御端子は、導電性の第1ワイヤを介して前記第1半導体素子の前記ゲート電極に接続されており、
前記第2制御端子は、導電性の第2ワイヤを介して前記第2半導体素子の前記ゲート電極に接続されている、付記10に記載の半導体モジュール。
付記12.
前記第1入力端子、前記第2入力端子および前記第3入力端子は、前記第2方向に見て互いに重なる、付記1ないし11のいずれかに記載の半導体モジュール。
付記13.
前記導通部材は、金属製の板材により構成される、付記1ないし12のいずれかに記載の半導体モジュール。
付記14.
前記第1入力端子、前記第2入力端子、および前記第3入力端子は、それぞれ、前記第1方向の一方側に向かって延び、かつ前記厚さ方向の一方側に向く入力側接合面を含み、
前記出力端子は、前記第1方向の他方側に向かって延び、かつ、前記厚さ方向の一方側に向く出力側接合面を含む、付記1ないし13のいずれかに記載の半導体モジュール。
付記15.
前記第1入力端子、前記第2入力端子、および前記第3入力端子は、それぞれ、前記厚さ方向に見て前記入力側接合面の周縁に位置し、かつ当該入力側接合面と交差する方向を向く入力側側面と、当該入力側側面に形成された入力側加工痕と、を有し、
前記出力端子は、前記厚さ方向に見て前記出力側接合面の周縁に位置し、かつ当該出力側接合面と交差する方向を向く出力側側面と、当該出力側側面に形成された出力側加工痕と、を有する、付記1ないし14のいずれかに記載の半導体モジュール。
付記16.
前記導電基板の少なくとも一部と、前記半導体素子と、前記導通部材と、を覆う封止樹脂をさらに備える、付記1ないし15のいずれかに記載の半導体モジュール。
付記17.
前記第2方向に間隔を隔てて配置された複数の前記第1半導体素子と、
前記第2方向に間隔を隔てて配置された複数の前記第2半導体素子と、を備える、付記3ないし12のいずれかに記載の半導体モジュール。
付記18.
厚さ方向の一方側を向く主面、および前記主面とは反対側を向く裏面を有する導電基板と、
前記主面に電気的に接合され、スイッチング機能を有する半導体素子と、
前記半導体素子によってスイッチングされる主回路電流の経路を構成し、前記主面から前記厚さ方向の一方側に離間する導通部材と、
前記導電基板に対し、前記厚さ方向に対して直角である第1方向の一方側に配置された第1入力端子、第2入力端子、および第3入力端子と、
前記導電基板に対して前記第1方向の他方側に配置された出力端子と、を備え、
前記導電基板は、前記厚さ方向に見て互いに離間する第1導電部および第2導電部を含み、
前記半導体素子は、前記第1導電部に電気的に接合された複数の第1半導体素子と、前記第2導電部に電気的に接合された複数の第2半導体素子と、を含み、
前記第2入力端子および前記第3入力端子は、前記第1入力端子を挟んで、前記厚さ方向および前記第1方向の双方に直角である第2方向の一方側および他方側に配置されており、
前記第1入力端子は、前記第1導電部に繋がっており、
前記出力端子は、前記第2導電部に繋がっており、
前記導通部材は、前記複数の第1半導体素子と前記第2導電部とに接続された第1導通部材と、前記複数の第2半導体素子と前記第2入力端子および前記第3入力端子とに接続され、かつ前記厚さ方向に見て前記第1半導体素子と重なる第2導通部材と、を含む、半導体モジュール。
付記19.
前記第1導電部および前記第2導電部は、前記第1方向一方側および前記第1方向他方側に配置されており、
前記複数の第1半導体素子および前記複数の第2半導体素子は、それぞれ、前記第2方向に沿って間隔を隔てて配置されており、
前記第2導通部材は、前記第2入力端子に接続され、かつ前記第1方向に延びる第1配線部と、前記第3入力端子に接続され、かつ前記第1方向に延びる第2配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第2方向に延びており、前記複数の第2半導体素子それぞれに接続される第3配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第3配線部に対して前記第1方向一方側に位置し、前記厚さ方向に見て前記複数の第1半導体素子と重なる第4配線部と、を含む、付記18に記載の半導体モジュール。
付記20.
前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くソース電極および前記厚さ方向他方側を向くドレイン電極をそれぞれ有しており、
前記第1導通部材は、前記第1半導体素子の前記ソース電極に接続されており、
前記第1導電部は、前記第1半導体素子の前記ドレイン電極に接続されており、
前記第3配線部は、前記第2半導体素子の前記ソース電極に接続されており、
前記第2導電部は、前記第2半導体素子の前記ドレイン電極に接続されている、付記19に記載の半導体モジュール。
付記21.
前記複数の第1半導体素子と前記複数の第2半導体素子とは、前記第1方向に見て互いに重なる、付記20に記載の半導体モジュール。
付記22.
前記第4配線部は、第1帯状部および第2帯状部を有し、
前記第1帯状部は、前記第1方向において前記第3配線部と離間し、かつ前記第1配線部および前記第2配線部の双方に繋がって前記第2方向に延びており、前記厚さ方向に見て前記複数の第1半導体素子と重なっており、
前記第2帯状部は、前記厚さ方向に見て、一端が前記第1帯状部に対して互いに隣接する前記第1半導体素子の間に繋がり、かつ他端が前記第3配線部に対して互いに隣接する前記第2半導体素子の間において繋がる、付記21に記載の半導体モジュール。
付記23.
前記第1帯状部は、前記厚さ方向に見て前記各第1半導体素子と重なり、他の部位よりも前記厚さ方向一方側に突き出た複数の凸状領域を有する、付記22に記載の半導体モジュール。
付記24.
前記第3配線部は、他の部位よりも前記厚さ方向他方側に突き出た複数の凹状領域を有し、
前記各凹状領域は、前記複数の第2半導体素子のいずれかと接合されている、付記19ないし23のいずれかに記載の半導体モジュール。
付記25.
前記複数の第1半導体素子および前記複数の第2半導体素子を制御するための複数の第1制御端子および複数の第2制御端子を備え、
前記複数の第1制御端子および前記複数の第2制御端子は、各々、前記主面上に配置され、かつ前記厚さ方向に沿って延びる、付記19ないし24のいずれかに記載の半導体モジュール。
付記26.
前記複数の第1制御端子は、前記第1導電部に支持され、かつ前記複数の第1半導体素子よりも前記第1方向一方側において前記第2方向に間隔を隔てて配置されており、
前記複数の第2制御端子は、前記第2導電部に支持され、かつ前記複数の第2半導体素子よりも前記第1方向他方側において前記第2方向に間隔を隔てて配置されている、付記25に記載の半導体モジュール。
付記27.
前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くゲート電極をそれぞれ有しており、
前記第1制御端子は、導電性の第1ワイヤを介して前記第1半導体素子の前記ゲート電極に接続されており、
前記第2制御端子は、導電性の第2ワイヤを介して前記第2半導体素子の前記ゲート電極に接続されている、付記26に記載の半導体モジュール。
付記28.
前記第1入力端子、前記第2入力端子および前記第3入力端子は、前記第2方向に見て互いに重なる、付記18ないし27のいずれかに記載の半導体モジュール。
付記29.
前記第1導通部材および前記第2導通部材は、金属製の板材により構成される、付記18ないし28のいずれかに記載の半導体モジュール。
10A:第1半導体素子 10B:第2半導体素子
101:素子主面 102:素子裏面
11:第1主面電極(ゲート電極)
12:第2主面電極(ソース電極)
13:第3主面電極 14:第4主面電極
15:裏面電極(ドレイン電極) 16:第5主面電極
171,172,173,174,181,182,183,184:角
191:第1辺 192:第2辺
193:第3辺 194:第4辺
2:導電基板 2A:第1導電部
2B:第2導電部 201:主面
201a:凹部 201b:凹部端縁
202:裏面 21:基材
22:主面接合層 23:裏面接合層
3:支持基板 301:支持面
302:底面 31:絶縁層
32:第1金属層 32A:第1部
32B:第2部 321:第1接合層
33:第2金属層 41:入力端子(第1入力端子)
411:入力側接合面 412:入力側側面
413:先端面 414:側方面
42:入力端子(第2入力端子) 421:入力側接合面
422:入力側側面 423:先端面
424:側方面 43:入力端子(第3入力端子)
431:入力側接合面 432:入力側側面
433:先端面 434:側方面
44:出力端子 441:出力側接合面
442:出力側側面 443:先端面
444:側方面 45:制御端子
451:ホルダ 452:金属ピン 459:導電性接合材
46A,46B,46C,46D,46E:第1制御端子
47A,47B,47C,47D:第2制御端子
5:制御端子支持体 51:絶縁層
52:第1金属層 521:第1部
522:第2部 523:第3部
524:第4部 525:第5部
53:第2金属層 59:接合材
6:導通部材 601:第1部
61:第1導通部材 61h:開口
62:第2導通部材 62A:第1部
62B:第2部 621:第1配線部
622:第2配線部 623:第3配線部
623a:凹状領域 623h:開口
624:第4配線部 625:第1帯状部
625a:凸状領域 625h:開口
626:第2帯状部 627:第1端縁
628:第2端縁 63:開口
69:導電性接合材 71:第1導電性接合材
711:第1基層 712:第1層
713:第2層 72:第2導電性接合材
721:第2基層 722:第3層
723:第4層
731:ワイヤ(ゲート電極と第1金属層との接続用)
731a:第1ワイヤ 731b:第2ワイヤ
732,733,734,735:ワイヤ 8:封止樹脂
81:樹脂主面 82:樹脂裏面
831,832:樹脂側面 832a:凹部
833,834:樹脂側面 851:第1突出部(突出部)
851a:第1突出端面(突出端面) 851b:凹部
851c:内壁面 852:第2突出部
86:樹脂空隙部 861:樹脂空隙部端縁
87:樹脂部 88:樹脂充填部
91:金型 911:押さえピン
Claims (16)
- 厚さ方向の一方側を向く主面、および前記主面とは反対側を向く裏面を有する導電基板と、
前記主面に電気的に接合され、スイッチング機能を有する半導体素子と、
前記半導体素子によってスイッチングされる主回路電流の経路を構成する導通部材と、
前記導電基板に対し、前記厚さ方向に対して直角である第1方向の一方側に配置された第1入力端子、第2入力端子、および第3入力端子と、
前記導電基板に対して前記第1方向の他方側に配置された出力端子と、を備え、
前記導電基板は、第1導電部および第2導電部を含み、
前記半導体素子は、前記第1導電部に電気的に接合された第1半導体素子と、前記第2導電部に電気的に接合された第2半導体素子と、を含み、
前記第2入力端子および前記第3入力端子は、前記第1入力端子を挟んで、前記厚さ方向および前記第1方向の双方に直角である第2方向の一方側および他方側に配置されており、
前記第1入力端子は、正極と負極とのうちの一方の極であり、かつ前記第1導電部に電気的に接続されており、
前記第2入力端子および前記第3入力端子は、正極と負極とのうちの他方の極であり、
前記出力端子は、前記第2導電部に電気的に接続されており、
前記導通部材は、前記第1半導体素子と前記第2導電部とに接続された第1導通部材と、前記第2半導体素子と前記第2入力端子および前記第3入力端子とに接続され、かつ前記厚さ方向に見て前記第1半導体素子と重なる第2導通部材と、を含む、半導体モジュール。 - 前記第1導電部および前記第2導電部は、前記第1方向一方側および前記第1方向他方側に配置されており、
前記第2導通部材は、前記第2入力端子に接続され、かつ前記第1方向に延びる第1配線部と、前記第3入力端子に接続され、かつ前記第1方向に延びる第2配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第2方向に延びており、前記第2半導体素子に接続される第3配線部と、前記第1配線部および前記第2配線部の双方に繋がり、かつ前記第3配線部に対して前記第1方向一方側に位置し、前記厚さ方向に見て前記第1半導体素子と重なる第4配線部と、を含む、請求項1に記載の半導体モジュール。 - 前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くソース電極および前記厚さ方向他方側を向くドレイン電極をそれぞれ有しており、
前記第1導通部材は、前記第1半導体素子の前記ソース電極に接続されており、
前記第1導電部は、前記第1半導体素子の前記ドレイン電極に接続されており、
前記第3配線部は、前記第2半導体素子の前記ソース電極に接続されており、
前記第2導電部は、前記第2半導体素子の前記ドレイン電極に接続されている、請求項2に記載の半導体モジュール。 - 前記第1半導体素子と前記第2半導体素子とは、前記第1方向に見て互いに重なる、請求項3に記載の半導体モジュール。
- 前記第4配線部は、第1帯状部および第2帯状部を有し、
前記第1帯状部は、前記第1方向において前記第3配線部と離間し、かつ前記第1配線部および前記第2配線部の双方に繋がって前記第2方向に延びており、前記厚さ方向に見て前記第1半導体素子と重なっており、
前記第2帯状部は、前記厚さ方向に見て、一端が前記第1帯状部に対して互いに隣接する前記第1半導体素子の間に繋がり、かつ他端が前記第3配線部に対して互いに隣接する前記第2半導体素子の間において繋がる、請求項4に記載の半導体モジュール。 - 前記第1帯状部は、前記厚さ方向に見て前記第1半導体素子と重なり、他の部位よりも前記厚さ方向一方側に突き出た凸状領域を有する、請求項5に記載の半導体モジュール。
- 前記第3配線部は、他の部位よりも前記厚さ方向他方側に突き出た凹状領域を有し、
前記凹状領域は、前記第2半導体素子と接合されている、請求項2に記載の半導体モジュール。 - 前記第1半導体素子および前記第2半導体素子を制御するための第1制御端子および第2制御端子を備え、
前記第1制御端子および前記第2制御端子は、各々、前記主面上に配置され、かつ前記厚さ方向に沿って延びる、請求項2に記載の半導体モジュール。 - 前記第1制御端子は、前記第1導電部に支持され、かつ前記第1半導体素子よりも前記第1方向一方側に配置されており、
前記第2制御端子は、前記第2導電部に支持され、かつ前記第2半導体素子よりも前記第1方向他方側に配置されている、請求項8に記載の半導体モジュール。 - 前記第1半導体素子および前記第2半導体素子は、前記厚さ方向一方側を向くゲート電極をそれぞれ有しており、
前記第1制御端子は、導電性の第1ワイヤを介して前記第1半導体素子の前記ゲート電極に接続されており、
前記第2制御端子は、導電性の第2ワイヤを介して前記第2半導体素子の前記ゲート電極に接続されている、請求項9に記載の半導体モジュール。 - 前記第1入力端子、前記第2入力端子および前記第3入力端子は、前記第2方向に見て互いに重なる、請求項1ないし10のいずれかに記載の半導体モジュール。
- 前記導通部材は、金属製の板材により構成される、請求項1ないし10のいずれかに記載の半導体モジュール。
- 前記第1入力端子、前記第2入力端子、および前記第3入力端子は、それぞれ、前記第1方向の一方側に向かって延び、かつ前記厚さ方向の一方側に向く入力側接合面を含み、
前記出力端子は、前記第1方向の他方側に向かって延び、かつ、前記厚さ方向の一方側に向く出力側接合面を含む、請求項1ないし10のいずれかに記載の半導体モジュール。 - 前記第1入力端子、前記第2入力端子、および前記第3入力端子は、それぞれ、前記厚さ方向に見て前記入力側接合面の周縁に位置し、かつ当該入力側接合面と交差する方向を向く入力側側面と、当該入力側側面に形成された入力側加工痕と、を有し、
前記出力端子は、前記厚さ方向に見て前記出力側接合面の周縁に位置し、かつ当該出力側接合面と交差する方向を向く出力側側面と、当該出力側側面に形成された出力側加工痕と、を有する、請求項13に記載の半導体モジュール。 - 前記導電基板の少なくとも一部と、前記半導体素子と、前記導通部材と、を覆う封止樹脂をさらに備える、請求項1ないし10のいずれかに記載の半導体モジュール。
- 前記第2方向に間隔を隔てて配置された複数の前記第1半導体素子と、
前記第2方向に間隔を隔てて配置された複数の前記第2半導体素子と、を備える、請求項2ないし10のいずれかに記載の半導体モジュール。
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