JP7330357B2 - 水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 - Google Patents
水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 Download PDFInfo
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- JP7330357B2 JP7330357B2 JP2022504247A JP2022504247A JP7330357B2 JP 7330357 B2 JP7330357 B2 JP 7330357B2 JP 2022504247 A JP2022504247 A JP 2022504247A JP 2022504247 A JP2022504247 A JP 2022504247A JP 7330357 B2 JP7330357 B2 JP 7330357B2
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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Description
102 第1の半導体構造体
104 第2の半導体構造体
106 ボンディング界面
108 水素ブロッキング層
110 水素ブロッキング層
200 3Dメモリデバイス
201 3Dメモリデバイス
202 第1の半導体構造体
204 第2の半導体構造体
205 第2の半導体構造体
206 ボンディング界面
208 基板
210 メモリスタック
212 導電性層
214 誘電体層
216 3D NANDメモリストリング
218 メモリフィルム
220 半導体チャネル
222 プラグ
224 プラグ
226 相互接続層
228 ボンディング層
230 ボンディングコンタクト
232 ボンディング層
234 ボンディングコンタクト
236 相互接続層
238 デバイス層
240 トランジスタ
242 半導体層
246 水素ブロッキング層
248 パッドアウト相互接続層
250 コンタクト
251 水素ブロッキングスペーサ
254 接触パッド
256 不動態化層
258 水素ブロッキング層
260 ボンディングコンタクト
302 シリコン基板
304 トランジスタ
306 デバイス層
308 相互接続層
310 ボンディング層
312 ボンディングコンタクト
402 シリコン基板
404 メモリスタック
406 導電性層
408 誘電体層
410 3D NANDメモリストリング
412 プラグ
414 メモリフィルム
416 半導体層
418 プラグ
420 相互接続層
422 ボンディング層
424 ボンディングコンタクト
502 ボンディング界面
504 半導体層
506 水素ブロッキング層
508 誘電体層
509 パッドアウト相互接続層
510 コンタクト
511 水素ブロッキングスペーサ
512 パッドコンタクト
514 不動態化層
Claims (19)
- メモリデバイスであって、
メモリアレイと、
前記メモリアレイの上方の複数のロジックデバイスと、
前記ロジックデバイスの上方にあり、前記ロジックデバイスと接触している半導体層と、
前記半導体層の上方のパッドアウト相互接続層と、
垂直方向に前記半導体層と前記パッドアウト相互接続層との間のブロッキング層と
を含み、
前記半導体層は、垂直方向に前記複数のロジックデバイスと前記ブロッキング層との間にあり、
前記ブロッキング層は、高誘電率(高k)誘電材料を含む、メモリデバイス。 - 前記ブロッキング層の厚さは、約1nmから約100nmの間にある、請求項1に記載のメモリデバイス。
- 前記ブロッキング層は、横方向に延在し、前記半導体層を被覆している、請求項1に記載のメモリデバイス。
- 前記ブロッキング層は、前記メモリデバイスの製作の間に、前記ロジックデバイスから前記パッドアウト相互接続層の中への、または前記パッドアウト相互接続層を越える水素のガス放出を阻止するように構成されている、請求項1に記載のメモリデバイス。
- 前記メモリアレイの上方の第1のボンディング層であって、複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックデバイスの下方の、および前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項1に記載のメモリデバイス。 - 前記メモリデバイスは、
垂直方向に前記メモリアレイと前記第1のボンディング層との間の第1の相互接続層と、
垂直方向に前記第2のボンディング層と前記ロジックデバイスとの間の第2の相互接続層と
をさらに含み、
前記ロジックデバイスは、前記第1および第2の相互接続層および前記第1および第2のボンディングコンタクトを通して、前記メモリアレイに電気的に接続されている、請求項5に記載のメモリデバイス。 - 前記メモリデバイスは、コンタクトであって、前記ブロッキング層および前記半導体層を通って垂直方向に延在し、前記パッドアウト相互接続層および前記第2の相互接続層を電気的に接続するコンタクトと、
前記コンタクトと前記ブロッキング層との間にブロッキングスペーサと、をさらに含む、請求項6に記載のメモリデバイス。 - 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項1に記載のメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項1に記載のメモリデバイス。
- メモリデバイスであって、
第1のブロッキング層と、
前記第1のブロッキング層の上方の複数のロジックデバイスと、
前記ロジックデバイスの上方にあり、前記ロジックデバイスに接触している半導体層と、
前記半導体層の上方の第2のブロッキング層であって、前記半導体層は、垂直方向に前記複数のロジックデバイスと前記第2のブロッキング層との間にある、第2のブロッキング層と、
前記第2のブロッキング層の上方のパッドアウト相互接続層と
を含み、
前記第2のブロッキング層は、高誘電率(高k)誘電材料を含む、メモリデバイス。 - 前記第1のブロッキング層は、高誘電率(高k)誘電材料を含む、請求項10に記載のメモリデバイス。
- 前記第1および第2のブロッキング層は、横方向に延在し、垂直方向に前記ロジックデバイスをカプセル化している、請求項10に記載のメモリデバイス。
- 前記第1および第2のブロッキング層のそれぞれの厚さは、約1nmから約100nmの間にある、請求項10に記載のメモリデバイス。
- 前記メモリデバイスは、
複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックデバイスの下方の、および前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項10に記載のメモリデバイス。 - 前記第1のブロッキング層は、垂直方向に前記第2のボンディング層と前記ロジックデバイスとの間にある、請求項14に記載のメモリデバイス。
- 前記メモリデバイスは、コンタクトをさらに含み、前記コンタクトは、前記第2のブロッキング層および前記半導体層を通って垂直方向に延在している、請求項14に記載のメモリデバイス。
- 前記コンタクトと前記第2のブロッキング層との間にブロッキングスペーサをさらに含む、請求項16に記載のメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項10に記載のメモリデバイス。
- 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項10に記載のメモリデバイス。
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11189600B2 (en) * | 2019-12-11 | 2021-11-30 | Samsung Electronics Co., Ltd. | Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding |
CN111937149B (zh) * | 2020-07-16 | 2021-07-09 | 长江存储科技有限责任公司 | 用于键合半导体结构及其半导体器件的方法 |
CN116076163A (zh) * | 2020-09-29 | 2023-05-05 | 华为技术有限公司 | 三维存储器及其制备方法、电子设备 |
KR20220096017A (ko) * | 2020-12-30 | 2022-07-07 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
CN112909007B (zh) * | 2021-03-24 | 2022-05-10 | 长江存储科技有限责任公司 | 三维存储器器件及其制造方法 |
CN113097212A (zh) * | 2021-03-30 | 2021-07-09 | 长江存储科技有限责任公司 | 一种半导体器件及其制造方法 |
CN113224071B (zh) * | 2021-05-06 | 2024-04-19 | 长江先进存储产业创新中心有限责任公司 | 半导体器件及其制备方法 |
CN115836387A (zh) | 2021-06-30 | 2023-03-21 | 长江存储科技有限责任公司 | 三维存储器装置及其形成方法 |
CN116058100A (zh) | 2021-06-30 | 2023-05-02 | 长江存储科技有限责任公司 | 三维存储器装置及其形成方法 |
CN115803882A (zh) | 2021-06-30 | 2023-03-14 | 长江存储科技有限责任公司 | 三维存储器装置及其形成方法 |
CN113711356B (zh) * | 2021-06-30 | 2024-06-14 | 长江存储科技有限责任公司 | 三维存储器器件及其形成方法 |
JP2024500456A (ja) | 2021-06-30 | 2024-01-09 | 長江存儲科技有限責任公司 | 三次元メモリデバイスおよびシステム |
EP4200908A4 (en) * | 2021-06-30 | 2024-01-31 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL MEMORY DEVICES AND THEIR FORMATION METHODS |
WO2023272552A1 (en) * | 2021-06-30 | 2023-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
KR20230030344A (ko) | 2021-08-25 | 2023-03-06 | 삼성전자주식회사 | 웨이퍼-투-웨이퍼 본딩을 이용하는 3차원 스토리지 장치 |
TWI817395B (zh) * | 2021-12-28 | 2023-10-01 | 南亞科技股份有限公司 | 具有堆疊結構的半導體元件 |
US11996390B2 (en) | 2021-12-28 | 2024-05-28 | Nanya Technology Corporation | Semiconductor device with stacking structure |
US11901350B2 (en) | 2021-12-28 | 2024-02-13 | Nanya Technology Corporation | Method for fabricating semiconductor device with stacking structure |
CN116456713A (zh) * | 2022-01-06 | 2023-07-18 | 长鑫存储技术有限公司 | 半导体器件的制造方法及半导体器件 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150171066A1 (en) | 2013-12-18 | 2015-06-18 | Renesas Electronics Corporation | Semiconductor device |
US20180277497A1 (en) | 2017-03-24 | 2018-09-27 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
JP2019161162A (ja) | 2018-03-16 | 2019-09-19 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
CN110291631A (zh) | 2019-05-17 | 2019-09-27 | 长江存储科技有限责任公司 | 具有静态随机存取存储器的三维存储器件 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5915167A (en) * | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
JP3950290B2 (ja) * | 1999-09-10 | 2007-07-25 | 三星電子株式会社 | キャパシタ保護膜を含む半導体メモリ素子及びその製造方法 |
US6958508B2 (en) * | 2000-10-17 | 2005-10-25 | Matsushita Electric Industrial Co., Ltd. | Ferroelectric memory having ferroelectric capacitor insulative film |
JP5251129B2 (ja) * | 2005-12-28 | 2013-07-31 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8384190B2 (en) * | 2009-03-06 | 2013-02-26 | Texas Instruments Incorporated | Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers |
CN102005414B (zh) * | 2009-08-28 | 2012-12-12 | 中芯国际集成电路制造(上海)有限公司 | Cmos图像传感器像素、制造方法及图像捕获设备 |
CN103250251A (zh) * | 2010-12-09 | 2013-08-14 | 德克萨斯仪器股份有限公司 | 使用氢阻挡层包封的铁电电容器 |
JP6827328B2 (ja) * | 2016-01-15 | 2021-02-10 | 株式会社半導体エネルギー研究所 | 半導体装置及び電子機器 |
US10002787B2 (en) * | 2016-11-23 | 2018-06-19 | Lam Research Corporation | Staircase encapsulation in 3D NAND fabrication |
US10319635B2 (en) * | 2017-05-25 | 2019-06-11 | Sandisk Technologies Llc | Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof |
US10290645B2 (en) * | 2017-06-30 | 2019-05-14 | Sandisk Technologies Llc | Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof |
US10622369B2 (en) * | 2018-01-22 | 2020-04-14 | Sandisk Technologies Llc | Three-dimensional memory device including contact via structures that extend through word lines and method of making the same |
CN109564923B (zh) * | 2018-06-28 | 2020-04-28 | 长江存储科技有限责任公司 | 具有屏蔽层的三维存储器器件以及用于制造其的方法 |
WO2020220280A1 (en) * | 2019-04-30 | 2020-11-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with embedded dynamic random-access memory |
WO2020210928A1 (en) * | 2019-04-15 | 2020-10-22 | Yangtze Memory Technologies Co., Ltd. | Integration of three-dimensional nand memory devices with multiple functional chips |
-
2019
- 2019-10-12 JP JP2022504247A patent/JP7330357B2/ja active Active
- 2019-10-12 WO PCT/CN2019/110752 patent/WO2021068229A1/en active Application Filing
- 2019-10-12 CN CN201980002378.6A patent/CN110876281B/zh active Active
- 2019-10-12 CN CN202011527127.0A patent/CN112635476B/zh active Active
- 2019-12-24 TW TW108147292A patent/TWI716232B/zh active
- 2019-12-26 US US16/727,870 patent/US11152277B2/en active Active
-
2021
- 2021-02-04 US US17/168,160 patent/US11594461B2/en active Active
- 2021-09-22 US US17/482,361 patent/US11728236B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150171066A1 (en) | 2013-12-18 | 2015-06-18 | Renesas Electronics Corporation | Semiconductor device |
JP2015119038A (ja) | 2013-12-18 | 2015-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20180277497A1 (en) | 2017-03-24 | 2018-09-27 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
JP2018163970A (ja) | 2017-03-24 | 2018-10-18 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
JP2019161162A (ja) | 2018-03-16 | 2019-09-19 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
CN110291631A (zh) | 2019-05-17 | 2019-09-27 | 长江存储科技有限责任公司 | 具有静态随机存取存储器的三维存储器件 |
WO2020232573A1 (en) | 2019-05-17 | 2020-11-26 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with static random-access memory |
US20200402562A1 (en) | 2019-05-17 | 2020-12-24 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with static random-access memory |
JP2022528897A (ja) | 2019-05-17 | 2022-06-16 | 長江存儲科技有限責任公司 | 3次元メモリデバイス、3次元メモリデバイスを形成するための方法および3次元メモリデバイスを動作させるための方法 |
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