JP7316224B2 - 差動入力レシーバを実現するための回路および方法 - Google Patents
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Description
以下で説明される回路および方法は、レシーバ(RX)入力パッドに結合されるレシーバ回路に配置され得るインターフェース回路を開示する。インターフェース回路は、従来の50オーム終端に適合し、信号コモンモードを最適なトランスミッタ(TX)のレベル(すなわちレシーバ入力パッドにおいて受信されるレベル)からレシーバの信号処理回路(たとえば連続時間線形イコライザ(CTLE:continuous time linear equalizer))のための最適なレベルに変換しながら、広帯域特性を有する入力信号を、レシーバ入力パッドから入力レシーバチェーン回路へ伝達するか、または結合し得る。
Claims (12)
- 差動入力レシーバを実現するための回路であって、
入力回路と、
第1出力回路と、
第2出力回路と、
第1出力抵抗と、
第2出力抵抗と、
制御回路とを備え、
前記入力回路は、差動の入力信号を受けるように構成された第1入力ノードおよび第2入力ノードを有し、
前記第1出力回路は、前記第1入力ノードおよび第1出力ノードの間に結合された第1キャパシタと、前記第2入力ノードおよび第2出力ノードの間に結合された第2キャパシタとを有し、第1周波数範囲内に前記差動の入力信号がある場合、前記第1出力ノードおよび前記第2出力ノードにおいて出力信号を生成し、
前記第2出力回路は、増幅器を含み、前記増幅器は、前記第1入力ノードに結合された第1増幅器入力と、前記第2入力ノードに結合された第2増幅器入力とを有し、前記第2出力回路は、前記第1周波数範囲よりも低い範囲に延在する第2周波数範囲に前記差動の入力信号がある場合、第1増幅器出力および第2増幅器出力において出力信号を生成し、
前記第1出力抵抗は、前記第1増幅器出力および前記第1キャパシタの間において前記第1出力ノードに結合され、
前記第2出力抵抗は、前記第2増幅器出力および前記第2キャパシタの間において前記第2出力ノードに結合され、
前記制御回路は、前記第1出力抵抗における電圧および前記第2出力抵抗における電圧の対を参照電圧と比較して、前記第1出力ノードおよび前記第2出力ノードにおけるコモンモード電圧を前記増幅器によって生成するための制御信号を前記増幅器に出力するように構成され、
前記第1周波数範囲は、前記第1出力抵抗の値、前記第1キャパシタの値、前記第2出力抵抗の値、および前記第2キャパシタの値に基づいている、回路。 - 前記第1入力ノードおよび前記第1増幅器入力の間に結合された第1抵抗と、
前記第1増幅器入力および前記第1増幅器出力の間に結合された第2抵抗と、
前記第2入力ノードおよび前記第2増幅器入力の間に結合された第3抵抗と、
前記第2増幅器入力および前記第2増幅器出力の間に結合された第4抵抗とをさらに備える、請求項1に記載の回路。 - 前記第1増幅器出力において第1電圧を生成するように構成された第1オフセット補償回路をさらに備える、請求項2に記載の回路。
- 前記第2抵抗は、第1抵抗分割回路網を形成する第1直列接続抵抗を含み、
前記第1オフセット補償回路は、前記第1抵抗分割回路網のノードにおける第1オフセット電圧を制御するように構成された電流源を含む、請求項3に記載の回路。 - 前記第2増幅器出力において第2電圧を生成するように構成された第2オフセット補償回路をさらに備える、請求項4に記載の回路。
- 前記第3抵抗は、第2抵抗分割回路網を形成する第2直列接続抵抗を含み、
前記第2オフセット補償回路は、前記第2抵抗分割回路網のノードにおける第2オフセット電圧を制御するように構成された電流源を含む、請求項5に記載の回路。 - 差動入力レシーバを実現する方法であって、
差動の入力信号を受けるように第1入力ノードおよび第2入力ノードを構成することと、
前記第1入力ノードおよび第1出力ノードの間に第1キャパシタを結合することと、
前記第2入力ノードおよび第2出力ノードの間に第2キャパシタを結合することと、
第1周波数範囲に前記差動の入力信号がある場合、前記第1出力ノードおよび前記第2出力ノードにおいて出力信号を生成することと、
増幅器の第1増幅器入力を前記第1入力ノードに結合するとともに前記増幅器の第2増幅器入力を前記第2入力ノードに結合することと、
前記第1周波数範囲よりも低い範囲に延在する第2周波数範囲に前記差動の入力信号がある場合、第1増幅器出力および第2増幅器出力において前記増幅器の出力に基づいて出力信号を生成することと、
前記第1増幅器出力および前記第1キャパシタの間において前記第1出力ノードに第1出力抵抗を結合することと、
前記第2増幅器出力および前記第2キャパシタの間において前記第2出力ノードに第2出力抵抗を結合することと、
制御回路が、前記第1出力抵抗における電圧および前記第2出力抵抗における電圧の対を参照電圧と比較することと、
前記制御回路が、前記第1出力ノードおよび前記第2出力ノードにおけるコモンモード電圧を前記増幅器によって生成するための制御信号を前記増幅器に出力することと
を含み、
前記第1周波数範囲は、前記第1出力抵抗の値、前記第1キャパシタの値、前記第2出力抵抗の値、および前記第2キャパシタの値に基づいている、方法。 - 前記第1入力ノードおよび前記第1増幅器入力の間に第1抵抗を結合することと、
前記第1増幅器入力および第1増幅器出力の間に第2抵抗を結合することと、
前記第2入力ノードおよび前記第2増幅器入力の間に第3抵抗を結合することと、
前記第2増幅器入力および第2増幅器出力の間に第4抵抗を結合することとをさらに含む、請求項7に記載の方法。 - 前記第1増幅器出力において第1電圧を生成するように第1オフセット補償回路を構成することをさらに含む、請求項8に記載の方法。
- 前記第2抵抗は、第1抵抗分割回路網を形成する第1直列接続抵抗を含み、
前記第1オフセット補償回路は、前記第1抵抗分割回路網のノードにおける第1オフセット電圧を制御するように構成された電流源を含む、請求項9に記載の方法。 - 前記第2増幅器出力において第2電圧を生成するように第2オフセット補償回路を構成することをさらに含む、請求項10に記載の方法。
- 前記第3抵抗は、第2抵抗分割回路網を形成する第2直列接続抵抗を含み、
前記第2オフセット補償回路は、前記第2抵抗分割回路網のノードにおける第2オフセット電圧を制御するように構成された電流源を含む、請求項11に記載の方法。
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US15/612,826 US9966908B1 (en) | 2017-06-02 | 2017-06-02 | Circuit for and method of implementing a differential input receiver |
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PCT/US2018/034952 WO2018222621A1 (en) | 2017-06-02 | 2018-05-29 | Circuit for and method of implementing a differential input receiver |
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US10826810B1 (en) | 2019-09-30 | 2020-11-03 | International Business Machines Corporation | Versatile signal detector circuit using common mode shift with all-pass characteristics |
US11031070B1 (en) * | 2020-01-27 | 2021-06-08 | Micron Technology, Inc. | Apparatus and method for performing continuous time linear equalization on a command/address signal |
US11431531B2 (en) | 2020-03-18 | 2022-08-30 | Qualcomm Incorporated | Termination for high-frequency transmission lines |
KR20220045371A (ko) | 2020-10-05 | 2022-04-12 | 삼성전자주식회사 | 아날로그 프론트 앤드 수신기 및 상기 수신기를 포함한 전자 장치 |
US11398934B1 (en) * | 2021-09-18 | 2022-07-26 | Xilinx, Inc. | Ultra-high-speed PAM-N CMOS inverter serial link |
JP2023045027A (ja) | 2021-09-21 | 2023-04-03 | キオクシア株式会社 | 半導体集積回路及び受信装置 |
KR102557685B1 (ko) | 2021-10-15 | 2023-07-19 | 고려대학교 산학협력단 | 액티브 인덕터 연속 시간 선형 등화기와 기준 전압 선택 등화기를 포함하는 단일 신호법 수신기 및 그 동작방법 |
US11601309B1 (en) | 2022-02-14 | 2023-03-07 | 1-Via Ltd | Multi-stage continuous time linear equalizer with reconfigurable inductor scheme |
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- 2018-05-29 KR KR1020197038699A patent/KR102574325B1/ko active IP Right Grant
- 2018-05-29 EP EP18731330.9A patent/EP3631982A1/en active Pending
- 2018-05-29 CN CN201880046666.7A patent/CN110915135B/zh active Active
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WO2018222621A1 (en) | 2018-12-06 |
CN110915135A (zh) | 2020-03-24 |
US9966908B1 (en) | 2018-05-08 |
CN110915135B (zh) | 2023-10-27 |
KR102574325B1 (ko) | 2023-09-04 |
KR20200013245A (ko) | 2020-02-06 |
EP3631982A1 (en) | 2020-04-08 |
JP2020522931A (ja) | 2020-07-30 |
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