JP7200121B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7200121B2 JP7200121B2 JP2019551771A JP2019551771A JP7200121B2 JP 7200121 B2 JP7200121 B2 JP 7200121B2 JP 2019551771 A JP2019551771 A JP 2019551771A JP 2019551771 A JP2019551771 A JP 2019551771A JP 7200121 B2 JP7200121 B2 JP 7200121B2
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- Prior art keywords
- oxide
- insulator
- conductor
- transistor
- oxygen
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Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図1(A)、図1(B)、図1(C)、および図1(D)は、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図1に示すように、トランジスタ200は、基板(図示しない。)の上に配置された 絶縁体222と、絶縁体222の上に配置された絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a1、および酸化物230a2)、および酸化物230bと、酸化物230b上に、互いに離して配置された導電体242a、および導電体242bと、導電体242a、および導電体242bの上にそれぞれ設けられた絶縁体273a、および絶縁体273bと、酸化物230、導電体242a、導電体242b、絶縁体273a、および絶縁体273bの上に配置された酸化物230cと、酸化物230cの上に配置された絶縁体250と、絶縁体250の上に配置され、少なくとも一部が導電体242aと導電体242bの間に重なるように配置された導電体260と、絶縁体250の上に設けられ、かつ導電体260を覆って配置された絶縁体274と、絶縁体274の上に配置された絶縁体280と、絶縁体280の上に配置された絶縁体282と、を有する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(c-axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)、および非晶質酸化物半導体などがある。
がある。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
続いて、上記金属酸化物をトランジスタのチャネル形成領域に用いる場合について説明する。
ここで、金属酸化物中における各不純物の影響について説明する。
ここでは、金属酸化物に含まれる、弱いZn-O結合について説明し、該結合を構成する酸素原子および亜鉛原子を低減する方法の一例について示す。
以下では、図2乃至図4を用いて、先の<半導体装置の構成例>で示したものとは異なる、本発明の一態様に係るトランジスタを有する半導体装置の一例について説明する。
次に、図1に示すトランジスタ200を有する半導体装置について、作製方法を図6乃至図10を用いて説明する。また、図6乃至図10において、各図の(A)は上面図を示す。また、各図の(B)は、(A)に示すA1-A2の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル長方向の断面図でもある。また、各図の(C)は、(A)にA3-A4の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。また、各図の(D)は、(A)にA5-A6の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。なお、各図の(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
本実施の形態では、記憶装置1として機能する半導体装置の一形態を、図11を用いて説明する。
図11(A)に示す記憶装置は、トランジスタ300と、トランジスタ200、容量素子100を有している。図11(A)は、トランジスタ200、およびトランジスタ300のチャネル長方向の断面図である。図11(B)には、トランジスタ300近傍のトランジスタ300のチャネル幅方向の断面図を示す。なお、以降の説明において、トランジスタ300、トランジスタ200、および容量素子100を有する記憶装置について説明する。
本発明の一態様の記憶装置は、図11(A)に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200は、トランジスタ300の上方に設けられる。また、容量素子100は、トランジスタ300、およびトランジスタ200の上方に設けられている。
本実施の形態では、上記実施の形態とは異なる、記憶装置として機能する半導体装置の一形態を、図12および図13を用いて説明する。図12および図13は、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある。)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある。)を示している。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図12(A)にOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、コントロールロジック回路1460を有する。
図13(A)乃至図13(C)に、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図13(A)に示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(フロントゲートと呼ぶ場合がある。)、及びバックゲートを有する。
図13(D)乃至図13(H)に、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図13(D)に示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、フロントゲート(単にゲートと呼ぶ場合がある。)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図14を用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図15にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本発明の一態様に係る半導体装置は、CPUやGPUなどのプロセッサ、またはチップに用いることができる。図16に、本発明の一態様に係るCPUやGPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るGPU又はチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係る集積回路又はチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図16(B)には、デスクトップ型情報端末5300が図示されている。デスクトップ型情報端末5300は、情報端末の本体5301と、ディスプレイ5302と、キーボード5303と、を有する。
図16(C)は、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
本発明の一態様のGPU又はチップは、移動体である自動車、及び自動車の運転席周辺に適用することができる。
本発明の一態様のGPU又はチップは、放送システムに適用することができる。
以下では、金属酸化物中に負の固定電荷が存在する場合の、トランジスタの電気特性について評価した。
以下では、上記実施例1とは異なる金属酸化物中に負の固定電荷が存在する場合の、トランジスタの電気特性について評価した。
Claims (10)
- 第1の絶縁体と、
前記第1の絶縁体の上に配置された、第1の酸化物と、
前記第1の酸化物の上に配置された、第2の酸化物と、
前記第2の酸化物上に、互いに離して配置された、第1の導電体、および第2の導電体と、
前記第2の酸化物、前記第1の導電体、および前記第2の導電体の上に配置された、第3の酸化物と、
前記第3の酸化物の上に配置された第2の絶縁膜と、
前記第3の酸化物、および前記第2の絶縁膜を間に挟み、前記第2の酸化物上に配置された第3の導電体と、を有し、
前記第3の酸化物は、金属元素と、窒素を含み、
前記金属元素は窒素と結合している半導体装置。 - 請求項1において、
前記第3の酸化物は、固定電荷を保持する層である半導体装置。 - 請求項1、または請求項2において、
前記第3の酸化物において、窒素の原子数比率が、0.1atomic%未満である半導体装置。 - 第1の絶縁体と、
前記第1の絶縁体の上に配置された、第1の酸化物と、
前記第1の酸化物の上に配置された、第2の酸化物と、
前記第2の酸化物上に、互いに離して配置された、第1の導電体、および第2の導電体と、
前記第2の酸化物、前記第1の導電体、および前記第2の導電体の上に配置された、第3の酸化物と、
前記第3の酸化物の上に配置された第2の絶縁膜と、
前記第3の酸化物、および前記第2の絶縁膜を間に挟み、前記第2の酸化物上に配置された第3の導電体と、を有し、
前記第1の酸化物は、第1の層と、第2の層を有し、
前記第2の層は、金属元素と、窒素を含み、
前記金属元素は窒素と結合している半導体装置。 - 請求項4において、
前記第2の層は、固定電荷を保持する層である半導体装置。 - 請求項4、または請求項5において、
前記第2の層において、窒素の原子数比率が、0.1atomic%未満である半導体装置。 - 請求項4乃至請求項6のいずれか一項において、
前記第1の層は、前記第2の層より酸素濃度が高く、
前記第2の層は、前記第1の層より窒素濃度が高い半導体装置。 - 請求項1乃至請求項7のいずれか一項において、
前記第1の酸化物、前記第2の酸化物、および前記第3の酸化物は、Inと、元素M(MはAl、Ga、Y、またはSn)と、Znと、を有する半導体装置。 - 請求項1乃至請求項8のいずれか一項において、
前記金属元素は、In、元素M(MはAl、Ga、Y、またはSn)、およびZnから選ばれた一つである半導体装置。 - 請求項6において、
前記第2の層において、窒素の原子数比率が、0.02atomic%以上である半導体装置。
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JPWO2019092541A1 (ja) | 2020-11-19 |
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