JP5942713B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

Info

Publication number
JP5942713B2
JP5942713B2 JP2012197105A JP2012197105A JP5942713B2 JP 5942713 B2 JP5942713 B2 JP 5942713B2 JP 2012197105 A JP2012197105 A JP 2012197105A JP 2012197105 A JP2012197105 A JP 2012197105A JP 5942713 B2 JP5942713 B2 JP 5942713B2
Authority
JP
Japan
Prior art keywords
heat transfer
semiconductor
metal plate
heat
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012197105A
Other languages
Japanese (ja)
Other versions
JP2014053457A (en
Inventor
宗彦 増谷
宗彦 増谷
繁和 東元
繁和 東元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyota Industries Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Industries Corp filed Critical Toyota Industries Corp
Priority to JP2012197105A priority Critical patent/JP5942713B2/en
Publication of JP2014053457A publication Critical patent/JP2014053457A/en
Application granted granted Critical
Publication of JP5942713B2 publication Critical patent/JP5942713B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、第１の半導体素子と第２の半導体素子を備える半導体モジュールに関する。   The present invention relates to a semiconductor module including a first semiconductor element and a second semiconductor element.

複数の半導体素子を積層した半導体モジュールとしては、例えば、特許文献１に記載の積層型半導体装置が知られている。
特許文献１に記載の積層型半導体装置は、第１主面側に第１の主電極を有し、第２主面側に第２の主電極を有する半導体チップが複数積層されて構成されている。各半導体チップの第１主面及び第２主面は、それぞれ、金属配線層に電気的に接続され、半導体チップの間では、向かい合う主面側同士が共通の金属配線層に接合されている。これにより、上下に二つの半導体チップが設けられ、下側の半導体チップに対して上側の半導体チップが積層されている。そして、半導体チップの駆動時には、各半導体チップが発熱し、この熱は、金属配線層に伝導する。 As a semiconductor module in which a plurality of semiconductor elements are stacked, for example, a stacked semiconductor device described in Patent Document 1 is known.
The stacked semiconductor device described in Patent Document 1 is configured by laminating a plurality of semiconductor chips each having a first main electrode on the first main surface side and a second main electrode on the second main surface side. Yes. The first main surface and the second main surface of each semiconductor chip are electrically connected to the metal wiring layer, and the main surface sides facing each other are bonded to a common metal wiring layer between the semiconductor chips. Thus, two semiconductor chips are provided on the upper and lower sides, and the upper semiconductor chip is stacked on the lower semiconductor chip. When the semiconductor chip is driven, each semiconductor chip generates heat, and this heat is conducted to the metal wiring layer.

特許第４０３９２０２号公報Japanese Patent No. 4039202

ところで、積層型半導体装置においては、半導体チップが積層されていることから、それぞれの半導体チップが発した熱の影響を互いに受けやすく、半導体チップに対する冷却効率が低下するおそれがある。   By the way, in the stacked semiconductor device, since the semiconductor chips are stacked, the semiconductor chips are easily affected by the heat generated by the respective semiconductor chips, and the cooling efficiency of the semiconductor chips may be reduced.

本発明は、このような従来技術の問題点に鑑みてなされたものであり、その目的は、半導体素子に対する冷却効率を向上させることができる半導体モジュールを提供することにある。   The present invention has been made in view of such problems of the prior art, and an object thereof is to provide a semiconductor module capable of improving the cooling efficiency for a semiconductor element.

上記課題を解決するため、請求項１に記載の発明は、第１の半導体素子と、前記第１の半導体素子が接合された第１の配線層と、前記第１の半導体素子の前記第１の配線層に接合された面と反対側の面に接合された第２の配線層と、前記第２の配線層の前記第１の半導体素子が接合された面と反対側の面に接合された第２の半導体素子と、を備え、前記第２の半導体素子が発した熱を、前記第１の半導体素子を含む第１の伝熱経路を介して前記第１の配線層に伝導させる半導体モジュールであって、前記第２の半導体素子が発した熱が伝導され、前記第２の半導体素子に対して前記第２の配線層が配置される側に配置される伝熱層を備え、前記伝熱層と前記第２の配線層の間には、前記第１の配線層と絶縁されるとともに、前記第２の半導体素子が発した熱を前記伝熱層に伝導させる前記第１の伝熱経路とは異なる第２の伝熱経路が設けられ、前記第１の配線層の前記第１の半導体素子が接合された面と反対側の面には、絶縁層が設けられるとともに、前記絶縁層の前記第１の配線層が設けられる面と同一面上には、前記第１の配線層と電気的に分離された前記伝熱層が設けられ、前記伝熱層と前記第２の配線層の間には、出力電極が設けられ、前記出力電極が前記第２の伝熱経路を兼ねることを要旨とする。 In order to solve the above problem, the invention according to claim 1 is a first semiconductor element, a first wiring layer to which the first semiconductor element is bonded, and the first semiconductor element. A second wiring layer bonded to a surface opposite to the surface bonded to the wiring layer, and a surface opposite to the surface of the second wiring layer opposite to the surface where the first semiconductor element is bonded. And a second semiconductor element that conducts heat generated by the second semiconductor element to the first wiring layer through a first heat transfer path including the first semiconductor element. A heat transfer layer disposed on a side where the second wiring layer is disposed with respect to the second semiconductor element, wherein the heat generated by the second semiconductor element is conducted, Between the heat transfer layer and the second wiring layer, the second semiconductor layer is insulated from the first wiring layer and the second semiconductor layer. Child different second heat transfer path is provided between the first heat transfer path for conducting the heat transfer layer of heat emitted is, the first of said first semiconductor element wiring layers are joined An insulating layer is provided on the surface opposite to the surface, and the insulating layer is electrically separated from the first wiring layer on the same surface as the surface on which the first wiring layer is provided. The summary is that the heat transfer layer is provided, an output electrode is provided between the heat transfer layer and the second wiring layer, and the output electrode also serves as the second heat transfer path .

これによれば、第２の半導体素子が発熱すると、この熱は第１の伝熱経路を介して第１の配線層に伝導する。更に、第２の半導体素子で発した熱は、第２の伝熱経路を介して伝熱層に伝導する。このため、第２の半導体素子が発した熱を複数の伝熱経路で第１の配線層及び伝熱層に伝熱させることができ、第２の半導体素子に対する冷却効率を向上させることができる。また、第２の半導体素子に対する冷却効率が向上されることで、第１の伝熱経路を伝導する熱量が少なくなり、第１の半導体素子に対する冷却効率も向上させることができる。
また、これによれば、出力電極が第２の伝熱経路の一部を兼ねるため、第２の伝熱経路を形成するための部材を別途用意する必要がなく、部品点数の削減が図られる。 According to this, when the second semiconductor element generates heat, this heat is conducted to the first wiring layer through the first heat transfer path. Furthermore, the heat generated by the second semiconductor element is conducted to the heat transfer layer through the second heat transfer path. For this reason, the heat generated by the second semiconductor element can be transferred to the first wiring layer and the heat transfer layer through a plurality of heat transfer paths, and the cooling efficiency for the second semiconductor element can be improved. . Further, since the cooling efficiency for the second semiconductor element is improved, the amount of heat conducted through the first heat transfer path is reduced, and the cooling efficiency for the first semiconductor element can also be improved.
Also, according to this, since the output electrode also serves as a part of the second heat transfer path, it is not necessary to separately prepare a member for forming the second heat transfer path, and the number of parts can be reduced. .

請求項２に記載の発明は、請求項１に記載の半導体モジュールであって、前記第２の伝熱経路は、少なくとも一つの前記第２の半導体素子の複数方向に設けられることを要旨とする。   The invention described in claim 2 is the semiconductor module according to claim 1, wherein the second heat transfer path is provided in a plurality of directions of at least one of the second semiconductor elements. .

これによれば、第２の半導体素子が発する熱は、第２の半導体素子を中心として複数方向に拡散していくため、複数方向に第２の伝熱経路を設けることで、第２の半導体素子が発する熱を効率よく伝熱層に伝導させることができる。   According to this, since the heat generated by the second semiconductor element diffuses in a plurality of directions around the second semiconductor element, the second semiconductor element is provided by providing the second heat transfer path in the plurality of directions. Heat generated by the element can be efficiently conducted to the heat transfer layer.

請求項３に記載の発明は、請求項１又は請求項２に記載の半導体モジュールであって、前記伝熱層には、前記伝熱層に伝導した熱の放熱を行う放熱部材が接合されることを特徴とする。   Invention of Claim 3 is a semiconductor module of Claim 1 or Claim 2, Comprising: The thermal radiation member which thermally radiates the heat | fever conducted to the said heat transfer layer is joined to the said heat transfer layer. It is characterized by that.

これによれば、伝熱層に伝導した熱は、放熱部材に伝導して放熱部材で放熱される。このため、第１の半導体素子及び第２の半導体素子に対する冷却効率が向上される。 According to this, the heat conducted to the heat transfer layer is conducted to the heat radiating member and radiated by the heat radiating member. For this reason, the cooling efficiency with respect to the first semiconductor element and the second semiconductor element is improved .

本発明によれば、半導体素子に対する冷却効率を向上させることができる。   ADVANTAGE OF THE INVENTION According to this invention, the cooling efficiency with respect to a semiconductor element can be improved.

第１の実施形態における半導体モジュールを示す分解斜視図。The disassembled perspective view which shows the semiconductor module in 1st Embodiment. 第１の実施形態における第２の半導体素子と第２の伝熱経路の関係を示す平面図。The top view which shows the relationship between the 2nd semiconductor element and 2nd heat-transfer path | route in 1st Embodiment. 第１の実施形態における半導体モジュールを示す図１の３−３線断面図。FIG. 3 is a sectional view taken along line 3-3 of FIG. 1 showing the semiconductor module according to the first embodiment. 第１の実施形態における半導体モジュールを示す図１の４−４線断面図。FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 1 illustrating the semiconductor module according to the first embodiment. 第２の実施形態における半導体モジュールを示す分解斜視図。The disassembled perspective view which shows the semiconductor module in 2nd Embodiment. 第２の実施形態における半導体モジュールを示す図５の６−６線断面図。FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. 5 illustrating the semiconductor module according to the second embodiment.

（第１の実施形態）
以下、本発明を具体化した第１の実施形態について、図１〜図４にしたがって説明する。 (First embodiment)
Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS.

図１に示すように、半導体モジュール１０は、絶縁層としての絶縁基板１１と、絶縁基板１１に積層された第１の配線金属板１３に設けられた第１の半導体素子２１，２２と、第１の半導体素子２１，２２に積層された第２の配線金属板２５に設けられた第２の半導体素子２６，２７とを有している。本実施形態の半導体モジュール１０は、第１の半導体素子２１，２２に対して第２の半導体素子２６，２７を積層した積層型半導体モジュールである。   As shown in FIG. 1, the semiconductor module 10 includes an insulating substrate 11 as an insulating layer, first semiconductor elements 21 and 22 provided on a first wiring metal plate 13 stacked on the insulating substrate 11, And second semiconductor elements 26 and 27 provided on a second wiring metal plate 25 stacked on one semiconductor element 21 and 22. The semiconductor module 10 of the present embodiment is a stacked semiconductor module in which second semiconductor elements 26 and 27 are stacked on first semiconductor elements 21 and 22.

絶縁基板１１は、矩形平板状をなしている。絶縁基板１１としては、例えば窒化アルミニウム、アルミナ、窒化ケイ素等からなるセラミック基板が用いられる。絶縁基板１１の上面には、第１の半導体素子２１，２２が接合される第１の配線層としての第１の配線金属板１３と、第１の配線金属板１３と電気的に分離して設けられた伝熱層としての金属板１４が形成されている。第１の配線金属板１３と金属板１４は、同一面上に設けられている。   The insulating substrate 11 has a rectangular flat plate shape. As the insulating substrate 11, for example, a ceramic substrate made of aluminum nitride, alumina, silicon nitride, or the like is used. A first wiring metal plate 13 as a first wiring layer to which the first semiconductor elements 21 and 22 are bonded is electrically separated from the upper surface of the insulating substrate 11 and the first wiring metal plate 13. A metal plate 14 is formed as a provided heat transfer layer. The first wiring metal plate 13 and the metal plate 14 are provided on the same surface.

金属板１４は、平面視Ｌ字状に形成されている。具体的にいえば、金属板１４は、矩形平板状をなす第１の延設部１４ａと、第１の延設部１４ａから第１の延設部１４ａの短手方向に水平に延びる第２の延設部１４ｂからなる。第１の延設部１４ａは、絶縁基板１１の一つの角部から、絶縁基板１１の長手方向に直線状に延びている。第２の延設部１４ｂは、上記した角部から絶縁基板１１の短手方向に直線状に延びている。第１の延設部１４ａの長さは、絶縁基板１１の長手方向の長さよりも短い。第２の延設部１４ｂの長さは、絶縁基板１１の短手方向の長さよりも短い。   The metal plate 14 is formed in an L shape in plan view. Specifically, the metal plate 14 includes a first extending portion 14a having a rectangular flat plate shape, and a second extending horizontally from the first extending portion 14a in the short direction of the first extending portion 14a. The extending portion 14b. The first extending portion 14 a extends linearly from one corner of the insulating substrate 11 in the longitudinal direction of the insulating substrate 11. The second extending portion 14 b extends linearly from the corner portion described above in the short direction of the insulating substrate 11. The length of the first extending portion 14 a is shorter than the length of the insulating substrate 11 in the longitudinal direction. The length of the second extending portion 14 b is shorter than the length of the insulating substrate 11 in the short direction.

第１の配線金属板１３は、略矩形平板状をなしている。第１の配線金属板１３は、その長手方向が絶縁基板１１の長手方向と一致し、短手方向が絶縁基板１１の短手方向と一致するように設けられている。そして、第１の配線金属板１３は、その短手方向の縁部が第１の延設部１４ａから若干離間して設けられるとともに、長手方向の縁部が第２の延設部１４ｂから若干離間して設けられている。これにより、第１の配線金属板１３と金属板１４は、電気的に分離されている。また、第１の配線金属板１３は、絶縁基板１１の上面において、金属板１４が設けられていない面の略全面に形成されている。   The first wiring metal plate 13 has a substantially rectangular flat plate shape. The first wiring metal plate 13 is provided such that its longitudinal direction coincides with the longitudinal direction of the insulating substrate 11 and its short direction coincides with the short direction of the insulating substrate 11. The first wiring metal plate 13 is provided with a short edge portion slightly spaced from the first extending portion 14a, and a long edge portion slightly extending from the second extending portion 14b. They are spaced apart. Thereby, the 1st wiring metal plate 13 and the metal plate 14 are electrically isolate | separated. Further, the first wiring metal plate 13 is formed on substantially the entire surface of the upper surface of the insulating substrate 11 where the metal plate 14 is not provided.

第１の配線金属板１３の上面には、二つの第１の半導体素子２１，２２が第１の配線金属板１３の長手方向に並んで設けられている。第１の半導体素子２１，２２は、半田などの接合材によって接合されている。第１の半導体素子２１，２２は、例えば、絶縁ゲートバイポーラ型トランジスタ（insulated gate bipolar transistor：ＩＧＢＴ）やパワーＭＯＳＦＥＴ（metal oxide semiconductor field effect transistor）等のスイッチング素子や、ダイオードなどである。また、第１の配線金属板１３の上面には、電源に接続される第１の入力電極３１が接合されている。   On the upper surface of the first wiring metal plate 13, two first semiconductor elements 21 and 22 are provided side by side in the longitudinal direction of the first wiring metal plate 13. The first semiconductor elements 21 and 22 are bonded by a bonding material such as solder. The first semiconductor elements 21 and 22 are, for example, switching elements such as insulated gate bipolar transistors (IGBTs) and power MOSFETs (metal oxide semiconductor field effect transistors), diodes, and the like. A first input electrode 31 connected to a power source is joined to the upper surface of the first wiring metal plate 13.

図１及び図３に示すように、金属板１４の上面には、出力電極３２が半田などの接合材によって接合されている。出力電極３２は、金属板１４に接合される接合部３３を有している。接合部３３は、矩形平板状をなす第１の接合部３３ａと、第１の接合部３３ａから第１の接合部３３ａの短手方向に水平に延びる第２の接合部３３ｂからなる。第１の接合部３３ａは、長手方向及び短手方向の寸法が、第１の延設部１４ａの長手方向及び短手方向の寸法と同一となっている。第２の接合部３３ｂは、長手方向及び短手方向の寸法が、第２の延設部１４ｂの長手方向及び短手方向の寸法と同一となっている。第１の接合部３３ａは、第１の延設部１４ａに接合され、第２の接合部３３ｂは、第２の延設部１４ｂに接合されている。第１の接合部３３ａには、第２の接合部３３ｂが延びる方向と逆方向に水平に延びるとともに、負荷（例えば、電気自動車などに搭載される三相モータ）に接続される接続部３４が形成されている。   As shown in FIGS. 1 and 3, the output electrode 32 is bonded to the upper surface of the metal plate 14 by a bonding material such as solder. The output electrode 32 has a joint portion 33 that is joined to the metal plate 14. The joint portion 33 includes a first joint portion 33a having a rectangular flat plate shape and a second joint portion 33b extending horizontally from the first joint portion 33a in the lateral direction of the first joint portion 33a. The first joint portion 33a has the same longitudinal and lateral dimensions as those of the first extending portion 14a in the longitudinal and lateral directions. The dimensions of the second joint portion 33b in the longitudinal direction and the lateral direction are the same as the dimensions of the second extending portion 14b in the longitudinal direction and the lateral direction. The first joint portion 33a is joined to the first extension portion 14a, and the second joint portion 33b is joined to the second extension portion 14b. The first joint portion 33a has a connection portion 34 that extends horizontally in a direction opposite to the direction in which the second joint portion 33b extends and is connected to a load (for example, a three-phase motor mounted on an electric vehicle or the like). Is formed.

第１の半導体素子２１，２２の上面（第１の半導体素子２１，２２の第１の配線金属板１３に接合された面と反対側の面）には、半田層２３が設けられている。出力電極３２の接合部３３の上面には、接合部３３と同一形状をなす半田層２４が接合されている。それぞれの半田層２３，２４の上面には、第２の配線層としての第２の配線金属板２５が接合されている。すなわち、第１の半導体素子２１，２２の上面には、半田層２３，２４によって第２の配線金属板２５が接合されている。第２の配線金属板２５の上面（第２の配線金属板２５の第１の半導体素子２１，２２が接合された面と反対側の面）には、二つの第２の半導体素子２６，２７が半田などの接合材によって接合されている。第２の半導体素子２６，２７は、第１の半導体素子２１，２２に積層されている。金属板１４（伝熱層）は、第２の半導体素子２６，２７に対して第２の配線金属板２５が配置される側に配置されている。   A solder layer 23 is provided on the upper surfaces of the first semiconductor elements 21 and 22 (surfaces opposite to the surfaces bonded to the first wiring metal plate 13 of the first semiconductor elements 21 and 22). A solder layer 24 having the same shape as the bonding portion 33 is bonded to the upper surface of the bonding portion 33 of the output electrode 32. A second wiring metal plate 25 as a second wiring layer is joined to the upper surfaces of the respective solder layers 23 and 24. That is, the second wiring metal plate 25 is joined to the upper surfaces of the first semiconductor elements 21 and 22 by the solder layers 23 and 24. On the upper surface of the second wiring metal plate 25 (the surface opposite to the surface where the first semiconductor elements 21 and 22 of the second wiring metal plate 25 are joined), two second semiconductor elements 26 and 27 are provided. Are joined by a joining material such as solder. The second semiconductor elements 26 and 27 are stacked on the first semiconductor elements 21 and 22. The metal plate 14 (heat transfer layer) is disposed on the side where the second wiring metal plate 25 is disposed with respect to the second semiconductor elements 26 and 27.

図２に示すように、二つの第２の半導体素子２６，２７のうち、一方の第２の半導体素子２６は、平面視したときに、第２の半導体素子２６の一辺が出力電極３２の第１の接合部３３ａ上に位置し、この一辺と交わる辺が出力電極３２の第２の接合部３３ｂ上に位置するように設けられている。第２の半導体素子２７は、平面視したときに、第２の半導体素子２７の一辺が出力電極３２の第１の接合部３３ａ上に位置するように設けられている。また、同時に第２の半導体素子２６，２７は、平面視したときに第１の半導体素子２１，２２上にも位置するように設けられている。   As shown in FIG. 2, of the two second semiconductor elements 26, 27, one second semiconductor element 26 has one side of the second semiconductor element 26 of the output electrode 32 when viewed in plan. It is located on the first joint 33 a and the side intersecting with this one side is located on the second joint 33 b of the output electrode 32. The second semiconductor element 27 is provided such that one side of the second semiconductor element 27 is positioned on the first joint portion 33 a of the output electrode 32 when viewed in plan. At the same time, the second semiconductor elements 26 and 27 are also provided so as to be positioned on the first semiconductor elements 21 and 22 when viewed in plan.

第２の半導体素子２６，２７は、第１の半導体素子２１，２２の発熱量を考慮して配置位置が決められる。二つの第１の半導体素子２１，２２の発熱量に偏りがあり、二つの第２の半導体素子２６，２７の発熱量にも偏りがある場合、二つの第２の半導体素子２６，２７のうち、発熱量の多い第２の半導体素子２６，２７が、二つの第１の半導体素子２１，２２のうち、発熱量の少ない第１の半導体素子２１，２２に積層される。また、発熱量の少ない第２の半導体素子２６，２７が発熱量の多い第１の半導体素子２１，２２に積層される。第２の半導体素子２６，２７は、例えば、絶縁ゲートバイポーラ型トランジスタ（insulated gate bipolar transistor：ＩＧＢＴ）やパワーＭＯＳＦＥＴ（metal oxide semiconductor field effect transistor）等のスイッチング素子や、ダイオードなどである。   The arrangement positions of the second semiconductor elements 26 and 27 are determined in consideration of the heat generation amount of the first semiconductor elements 21 and 22. If the heat generation amounts of the two first semiconductor elements 21 and 22 are biased and the heat generation amounts of the two second semiconductor elements 26 and 27 are also biased, of the two second semiconductor elements 26 and 27 The second semiconductor elements 26 and 27 that generate a large amount of heat are stacked on the first semiconductor elements 21 and 22 that generate a small amount of heat, out of the two first semiconductor elements 21 and 22. Further, the second semiconductor elements 26 and 27 having a small heat generation amount are stacked on the first semiconductor elements 21 and 22 having a large heat generation amount. The second semiconductor elements 26 and 27 are, for example, switching elements such as insulated gate bipolar transistors (IGBTs) and power MOSFETs (metal oxide semiconductor field effect transistors), diodes, and the like.

図４に示すように、第２の半導体素子２６，２７が発する熱は、矢印Ｙ１にしたがって第１の配線金属板１３に伝導する。第２の半導体素子２６，２７で発した熱は、第２の配線金属板２５に伝導し、半田層２３及び第１の半導体素子２１，２２を介して第１の配線金属板１３に伝導する。したがって、半田層２３及び第１の半導体素子２１，２２が第１の配線金属板１３に熱を伝導させる第１の伝熱経路を形成している。   As shown in FIG. 4, the heat generated by the second semiconductor elements 26 and 27 is conducted to the first wiring metal plate 13 in accordance with the arrow Y1. The heat generated by the second semiconductor elements 26 and 27 is conducted to the second wiring metal plate 25, and is conducted to the first wiring metal plate 13 through the solder layer 23 and the first semiconductor elements 21 and 22. . Therefore, the solder layer 23 and the first semiconductor elements 21 and 22 form a first heat transfer path for conducting heat to the first wiring metal plate 13.

また、第２の半導体素子２６，２７が発する熱は、矢印Ｙ２にしたがって第２の配線金属板２５に伝導し、半田層２４及び出力電極３２を介して金属板１４にも伝導する。したがって、金属板１４と第２の配線金属板２５の間に設けられた半田層２４及び出力電極３２が第２の伝熱経路を形成している。第２の伝熱経路は、二つの第２の半導体素子２６，２７のうち、一方の第２の半導体素子２６の二辺と重なり合うように設けられている。すなわち、第２の半導体素子２６の複数方向（２方向）に第２の伝熱経路が設けられている。具体的にいえば、第１の接合部３３ａと第１の接合部３３ａの上面に設けられた半田層２４からなる第２の伝熱経路と、第２の接合部３３ｂと第２の接合部３３ｂの上面に設けられた半田層２４からなる第２の伝熱経路が第２の半導体素子２６の２方向に位置する第２の伝熱経路となる。一方、第２の伝熱経路は、第２の半導体素子２７の一方向に設けられている。しがたって、第２の半導体素子２７は、第２の半導体素子２６に比べて冷却されにくい。このため、第２の半導体素子２６として、第２の半導体素子２７よりも発熱量が多い半導体素子を使用することが望ましい。例えば、第２の半導体素子２６として、ＩＧＢＴを使用し、第２の半導体素子２７としてダイオードを使用すればよい。なお、第２の伝熱経路は、絶縁基板１１によって第１の配線金属板１３と電気的に絶縁されている。   Further, the heat generated by the second semiconductor elements 26 and 27 is conducted to the second wiring metal plate 25 in accordance with the arrow Y2, and is also conducted to the metal plate 14 through the solder layer 24 and the output electrode 32. Therefore, the solder layer 24 and the output electrode 32 provided between the metal plate 14 and the second wiring metal plate 25 form a second heat transfer path. The second heat transfer path is provided so as to overlap two sides of one of the second semiconductor elements 26 and 27. That is, the second heat transfer path is provided in a plurality of directions (two directions) of the second semiconductor element 26. More specifically, the second heat transfer path composed of the first bonding portion 33a and the solder layer 24 provided on the upper surface of the first bonding portion 33a, the second bonding portion 33b, and the second bonding portion. The second heat transfer path formed of the solder layer 24 provided on the upper surface of 33 b is a second heat transfer path positioned in two directions of the second semiconductor element 26. On the other hand, the second heat transfer path is provided in one direction of the second semiconductor element 27. Therefore, the second semiconductor element 27 is less likely to be cooled than the second semiconductor element 26. Therefore, it is desirable to use a semiconductor element that generates more heat than the second semiconductor element 27 as the second semiconductor element 26. For example, an IGBT may be used as the second semiconductor element 26 and a diode may be used as the second semiconductor element 27. The second heat transfer path is electrically insulated from the first wiring metal plate 13 by the insulating substrate 11.

第２の半導体素子２６，２７の上面には、半田層２８が設けられている。半田層２８の上面には、電源と接続される第２の入力電極３５が接合されている。
第１の配線金属板１３の下面には、絶縁基板１１を介して平板状の放熱部材３６が接合されている。放熱部材３６は、半田などの接合材によって接合されている。放熱部材３６は、銅やアルミニウムなどの金属材料からなる。放熱部材３６は、周囲に存在する空気と熱交換を行うことで、放熱部材３６に伝導した熱を放熱する。 A solder layer 28 is provided on the upper surfaces of the second semiconductor elements 26 and 27. A second input electrode 35 connected to the power source is joined to the upper surface of the solder layer 28.
A flat heat dissipation member 36 is joined to the lower surface of the first wiring metal plate 13 via the insulating substrate 11. The heat radiating member 36 is joined by a joining material such as solder. The heat dissipation member 36 is made of a metal material such as copper or aluminum. The heat dissipating member 36 dissipates heat conducted to the heat dissipating member 36 by exchanging heat with the air present around it.

次に、本実施形態の半導体モジュール１０の作用について説明する。
本実施形態の半導体モジュール１０は、例えばインバータに適用される。このインバータは第１の入力電極３１及び第２の入力電極３５から入力されたバッテリの直流電力を交流電力に変換して出力電極３２から負荷に出力するためのものである。本実施形態の半導体モジュール１０は、３相インバータの１相分の上下アームを構成している。 Next, the operation of the semiconductor module 10 of this embodiment will be described.
The semiconductor module 10 of this embodiment is applied to an inverter, for example. This inverter is for converting the DC power of the battery input from the first input electrode 31 and the second input electrode 35 into AC power and outputting it from the output electrode 32 to the load. The semiconductor module 10 of this embodiment constitutes upper and lower arms for one phase of a three-phase inverter.

上述のとおり、第１の半導体素子２１，２２と第２の半導体素子２６，２７は積層構造であり、放熱部材３６は、第１の半導体素子２１，２２側のみに配置されている。
半導体モジュール１０が駆動するときには、第１の半導体素子２１，２２及び第２の半導体素子２６，２７が発熱する。第１の半導体素子２１，２２が発熱すると、この熱は、第１の配線金属板１３に伝導する。第１の配線金属板１３に伝導した熱は、絶縁基板１１を介して放熱部材３６に伝導し、これにより第１の半導体素子２１，２２で発した熱が放熱される。 As described above, the first semiconductor elements 21 and 22 and the second semiconductor elements 26 and 27 have a stacked structure, and the heat dissipation member 36 is disposed only on the first semiconductor elements 21 and 22 side.
When the semiconductor module 10 is driven, the first semiconductor elements 21 and 22 and the second semiconductor elements 26 and 27 generate heat. When the first semiconductor elements 21 and 22 generate heat, the heat is conducted to the first wiring metal plate 13. The heat conducted to the first wiring metal plate 13 is conducted to the heat radiating member 36 through the insulating substrate 11, whereby the heat generated by the first semiconductor elements 21 and 22 is radiated.

第２の半導体素子２６，２７が発熱すると、この熱は、第１の伝熱経路を介して第１の配線金属板１３に伝導する。第１の配線金属板１３に伝導した熱は、絶縁基板１１を介して放熱部材３６に伝導し、これにより第２の半導体素子２６，２７で発した熱が放熱される。   When the second semiconductor elements 26 and 27 generate heat, this heat is conducted to the first wiring metal plate 13 through the first heat transfer path. The heat conducted to the first wiring metal plate 13 is conducted to the heat radiating member 36 through the insulating substrate 11, whereby the heat generated by the second semiconductor elements 26 and 27 is radiated.

また、第２の半導体素子２６，２７が発した熱は、第２の伝熱経路を介して金属板１４にも伝導する。金属板１４に伝導した熱は、絶縁基板１１を介して放熱部材３６に伝導し、これにより第２の半導体素子２６，２７で発した熱が放熱される。すなわち、第２の半導体素子２６，２７で発した熱は、複数の伝熱経路を介して放熱部材３６に伝導する。   Further, the heat generated by the second semiconductor elements 26 and 27 is also conducted to the metal plate 14 through the second heat transfer path. The heat conducted to the metal plate 14 is conducted to the heat radiating member 36 through the insulating substrate 11, whereby the heat generated by the second semiconductor elements 26 and 27 is radiated. That is, the heat generated by the second semiconductor elements 26 and 27 is conducted to the heat radiating member 36 through a plurality of heat transfer paths.

したがって、上記実施形態によれば、以下のような効果を得ることができる。
（１）第２の半導体素子２６，２７が発した熱は、第１の伝熱経路を介して第１の配線金属板１３に伝導するのに加えて、第２の伝熱経路を介して金属板１４に伝導する。第２の半導体素子２６，２７が発した熱を第１の配線金属板１３及び金属板１４に伝導させる伝熱経路を複数設けることで、第１の半導体素子２１，２２側のみから放熱される積層構造でも、第２の半導体素子２６，２７に対する冷却効率を向上させることができる。また、第２の半導体素子２６，２７に対する冷却効率を向上させることで、第１の伝熱経路を伝導する熱量が少なくなり、第１の半導体素子２１，２２に伝導する熱量が少なくなる。このため、第１の半導体素子２１，２２に対する冷却効率も向上される。 Therefore, according to the above embodiment, the following effects can be obtained.
(1) The heat generated by the second semiconductor elements 26 and 27 is conducted to the first wiring metal plate 13 through the first heat transfer path, and also through the second heat transfer path. Conducted to the metal plate 14. By providing a plurality of heat transfer paths for conducting the heat generated by the second semiconductor elements 26 and 27 to the first wiring metal plate 13 and the metal plate 14, heat is radiated from only the first semiconductor elements 21 and 22 side. Even in the stacked structure, the cooling efficiency for the second semiconductor elements 26 and 27 can be improved. In addition, by improving the cooling efficiency for the second semiconductor elements 26 and 27, the amount of heat conducted through the first heat transfer path is reduced, and the amount of heat conducted to the first semiconductor elements 21 and 22 is reduced. For this reason, the cooling efficiency with respect to the 1st semiconductor elements 21 and 22 is also improved.

（２）第２の半導体素子２６，２７の複数方向に第２の伝熱経路を設けることで、第２の半導体素子２６，２７が発した熱が伝導しやすく、第２の半導体素子２６，２７に対する冷却効率が更に向上される。   (2) By providing the second heat transfer path in a plurality of directions of the second semiconductor elements 26 and 27, the heat generated by the second semiconductor elements 26 and 27 can be easily conducted. The cooling efficiency with respect to 27 is further improved.

（３）絶縁基板１１には、放熱部材３６が設けられている。このため、第１の配線金属板１３及び金属板１４に伝導した熱は、絶縁基板１１を介して放熱部材３６に伝導し、放熱部材３６によってこの熱を適切に放熱することができる。したがって、第１の半導体素子２１，２２及び第２の半導体素子２６，２７に対する冷却効率が向上される。   (3) The heat radiating member 36 is provided on the insulating substrate 11. For this reason, the heat conducted to the first wiring metal plate 13 and the metal plate 14 is conducted to the heat radiating member 36 through the insulating substrate 11, and this heat can be appropriately radiated by the heat radiating member 36. Therefore, the cooling efficiency for the first semiconductor elements 21 and 22 and the second semiconductor elements 26 and 27 is improved.

（４）出力電極３２は、第２の伝熱経路の一部を兼ねている。したがって、第２の伝熱経路を形成するための部材を別途用意する必要が無く、部品点数の削減が図られる。
（５）第１の半導体素子２１，２２の発熱量を考慮して第２の半導体素子２６，２７の位置を決めている。このため、第１の半導体素子２１，２２間の温度差及び第２の半導体素子２６，２７間の温度差が小さくなる。 (4) The output electrode 32 also serves as a part of the second heat transfer path. Therefore, it is not necessary to separately prepare a member for forming the second heat transfer path, and the number of parts can be reduced.
(5) The positions of the second semiconductor elements 26 and 27 are determined in consideration of the amount of heat generated by the first semiconductor elements 21 and 22. For this reason, the temperature difference between the first semiconductor elements 21 and 22 and the temperature difference between the second semiconductor elements 26 and 27 are reduced.

（６）半導体モジュール１０を積層構造とすることで、第１の配線金属板１３と第２の配線金属板２５が、その厚み方向に対向している。第１の配線金属板１３を流れる電流と第２の配線金属板２５を流れる電流の向きは、逆向きとなるため、相互誘導作用によって半導体モジュール１０のインダクタンスを低減させることができる。   (6) Since the semiconductor module 10 has a laminated structure, the first wiring metal plate 13 and the second wiring metal plate 25 face each other in the thickness direction. Since the direction of the current flowing through the first wiring metal plate 13 and the direction of the current flowing through the second wiring metal plate 25 are opposite, the inductance of the semiconductor module 10 can be reduced by the mutual induction action.

（７）半導体モジュール１０を積層構造とすることで、半導体素子を水平方向に並べて配置した半導体モジュール１０に比べると、平面視したときの面積を約３割小さくすることができる。   (7) Since the semiconductor module 10 has a laminated structure, the area when viewed in plan can be reduced by about 30% compared to the semiconductor module 10 in which semiconductor elements are arranged in a horizontal direction.

（第２の実施形態）
次に、本発明を具体化した第２の実施形態について図５及び図６にしたがって説明する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.

図５に示すように、半導体モジュール４０は、絶縁層としての第１の絶縁基板４１を有している。第１の絶縁基板４１は矩形平板状をなしている。第１の絶縁基板４１の上面には、第１の配線層及び伝熱層としての第１の配線金属板４２が接合されている。   As shown in FIG. 5, the semiconductor module 40 has a first insulating substrate 41 as an insulating layer. The first insulating substrate 41 has a rectangular flat plate shape. A first wiring metal plate 42 serving as a first wiring layer and a heat transfer layer is bonded to the upper surface of the first insulating substrate 41.

第１の配線金属板４２の上面には、第２の絶縁基板４３が設けられている。第２の絶縁基板４３は、第１の配線金属板４２の長手方向に３つ並んで設けられている。各第２の絶縁基板４３は、同一形状をなしている。第２の絶縁基板４３は、矩形平板状をなす本体部４４と、本体部４４の長手方向両端から本体部４４の短手方向両側に向けて延びる第１の延設部４５及び第２の延設部４６とからなる。第２の延設部４６の一方は、他方よりも（上面が）広くなるように設けられている。また、第１の配線金属板４２の上面には、電源に接続される第１の入力電極７１が接合されている。   A second insulating substrate 43 is provided on the upper surface of the first wiring metal plate 42. Three second insulating substrates 43 are provided side by side in the longitudinal direction of the first wiring metal plate 42. Each second insulating substrate 43 has the same shape. The second insulating substrate 43 includes a main body 44 having a rectangular flat plate shape, a first extending portion 45 and a second extension extending from both longitudinal ends of the main body 44 toward both lateral sides of the main body 44. And an installation portion 46. One of the second extending portions 46 is provided so as to be wider (upper surface) than the other. A first input electrode 71 connected to the power source is joined to the upper surface of the first wiring metal plate 42.

第１の配線金属板４２の上面には、第１の半導体素子６１，６２が接合されている。第１の半導体素子６１は、各第２の絶縁基板４３の本体部４４と二つの第１の延設部４５に囲まれる領域のそれぞれに、一個ずつ設けられている。第１の半導体素子６２は、本体部４４と二つの第２の延設部４６に囲まれる領域のそれぞれに、一個ずつ設けられている。   First semiconductor elements 61 and 62 are joined to the upper surface of the first wiring metal plate 42. One first semiconductor element 61 is provided in each of the regions surrounded by the main body 44 and the two first extending portions 45 of each second insulating substrate 43. One first semiconductor element 62 is provided in each of the regions surrounded by the main body 44 and the two second extending portions 46.

第２の絶縁基板４３の上面には、第２の絶縁基板４３と相似の金属板４７が設けられている。金属板４７の上面には、金属板４７と同一形状をなす半田層４８が設けられている。また、各第１の半導体素子６１，６２の上面（第１の半導体素子６１，６２の第１の配線金属板４２が接合された面と反対側の面）には、半田層４９が設けられている。   A metal plate 47 similar to the second insulating substrate 43 is provided on the upper surface of the second insulating substrate 43. On the upper surface of the metal plate 47, a solder layer 48 having the same shape as the metal plate 47 is provided. Also, a solder layer 49 is provided on the upper surface of each first semiconductor element 61, 62 (the surface opposite to the surface where the first wiring metal plate 42 of the first semiconductor element 61, 62 is joined). ing.

それぞれの半田層４８，４９の上面には、第２の配線層としての第２の配線金属板５０が一つずつ設けられている。すなわち、第１の半導体素子６１，６２、金属板４７の上面には、半田層４８，４９を介して第２の配線金属板５０が接合されている。それぞれの第２の配線金属板５０は、電気的に分離されている。第２の配線金属板５０の上面には、第２の半導体素子６３，６４が二個ずつ設けられている。第２の半導体素子６３は、第１の半導体素子６１に対して積層されている。第２の半導体素子６４は、第１の半導体素子６２に積層されている。本実施形態でも、第１の実施形態と同様に、発熱量の多い第１の半導体素子６１に対して発熱量の少ない第２の半導体素子６３が積層され、発熱量の少ない第１の半導体素子６２に対して発熱量の多い第２の半導体素子６４が積層される。第１の配線金属板４２は、第２の半導体素子６３，６４に対して第２の配線金属板５０が配置される側に配置されている。   On the upper surfaces of the solder layers 48 and 49, one second wiring metal plate 50 as a second wiring layer is provided. That is, the second wiring metal plate 50 is bonded to the upper surfaces of the first semiconductor elements 61 and 62 and the metal plate 47 via the solder layers 48 and 49. Each second wiring metal plate 50 is electrically separated. Two second semiconductor elements 63 and 64 are provided on the upper surface of the second wiring metal plate 50. The second semiconductor element 63 is stacked on the first semiconductor element 61. The second semiconductor element 64 is stacked on the first semiconductor element 62. Also in the present embodiment, as in the first embodiment, the second semiconductor element 63 having a small heat generation amount is stacked on the first semiconductor element 61 having a large heat generation amount, and the first semiconductor element having a small heat generation amount is stacked. A second semiconductor element 64 having a larger calorific value than 62 is stacked. The first wiring metal plate 42 is disposed on the side where the second wiring metal plate 50 is disposed with respect to the second semiconductor elements 63 and 64.

第２の半導体素子６３は、平面視したときに、第２の半導体素子６３の一辺に第２の絶縁基板４３の本体部４４が沿い、この一辺と交わる二辺に第１の延設部４５が沿うように配置されている。第２の半導体素子６４は、平面視したときに、第２の半導体素子６４の一辺に本体部４４が沿い、この一辺と交わる二辺に第２の延設部４６が沿うように配置されている。また、発熱量の少ない第１の半導体素子６２をオフセットして配置し、第２の延設部４６の一方を他方より広く設け、発熱量の多い第２の半導体素子６４を逆にオフセットして配置している。従って、オフセットしない場合より、平面視したときに発熱量の多い第２の半導体素子６４が広く設けた第２の延設部４６の上に広く配置されるとともに、第２の配線金属板５０の上面に後述の出力電極５１の配置スペースを確保している。   When the second semiconductor element 63 is viewed in plan, the main body portion 44 of the second insulating substrate 43 extends along one side of the second semiconductor element 63, and the first extending portion 45 is formed along two sides that intersect the one side. Is arranged along. When viewed in plan, the second semiconductor element 64 is arranged such that the main body portion 44 is along one side of the second semiconductor element 64 and the second extending portion 46 is along two sides that intersect the one side. Yes. In addition, the first semiconductor element 62 with a small amount of heat generation is offset and disposed, one of the second extending portions 46 is provided wider than the other, and the second semiconductor element 64 with a large amount of heat generation is reversely offset. It is arranged. Therefore, the second semiconductor element 64 that generates a large amount of heat when seen in a plan view is widely disposed on the second extending portion 46 that is widely provided, and the second wiring metal plate 50 has a larger amount than the case where it is not offset. An arrangement space for an output electrode 51 described later is secured on the upper surface.

図６に示すように、第２の半導体素子６３，６４が発する熱は、矢印Ｙ３にしたがって第２の配線金属板５０に伝導し、半田層４９及び第１の半導体素子６１，６２を介して第１の配線金属板４２に伝導する。したがって、第１の伝熱経路は、半田層４９及び第１の半導体素子６１，６２から形成されている。   As shown in FIG. 6, the heat generated by the second semiconductor elements 63 and 64 is conducted to the second wiring metal plate 50 in accordance with the arrow Y <b> 3 and passes through the solder layer 49 and the first semiconductor elements 61 and 62. Conducted to the first wiring metal plate 42. Therefore, the first heat transfer path is formed by the solder layer 49 and the first semiconductor elements 61 and 62.

また、矢印Ｙ４に示すように、第２の半導体素子６３，６４が発する熱は、矢印Ｙ４にしたがって第２の配線金属板５０に伝導し、半田層４８、金属板４７及び第２の絶縁基板４３を介して第１の配線金属板４２に伝導する。したがって、第２の伝熱経路は、半田層４８、金属板４７及び第２の絶縁基板４３から形成されている。第２の伝熱経路は、全ての第２の半導体素子６３，６４の３方向に設けられている。具体的にいえば、本体部４４と本体部４４の上面に設けられた半田層４８からなる第２の伝熱経路と、二つの第１の延設部４５と第１の延設部４５の上面に設けられた半田層４８からなる第２の伝熱経路が第２の半導体素子６３の３方向に位置する第２の伝熱経路となる。また、本体部４４と本体部４４の上面に設けられた半田層４８からなる第２の伝熱経路と、二つの第２の延設部４６と第２の延設部４６の上面に設けられた半田層４８からなる第２の伝熱経路が第２の半導体素子６４の３方向に位置する第２の伝熱経路となる。なお、金属板４７と第１の配線金属板４２との間に、第２の絶縁基板４３を介在させることで、金属板４７と第１の配線金属板４２との電気的な接続を防止し、第２の伝熱経路と第１の配線金属板４２との電気的な絶縁を図っている。   Further, as indicated by the arrow Y4, the heat generated by the second semiconductor elements 63 and 64 is conducted to the second wiring metal plate 50 according to the arrow Y4, and the solder layer 48, the metal plate 47, and the second insulating substrate. Conducted to the first wiring metal plate 42 through 43. Therefore, the second heat transfer path is formed by the solder layer 48, the metal plate 47, and the second insulating substrate 43. The second heat transfer path is provided in three directions of all the second semiconductor elements 63 and 64. Specifically, the main body 44 and the second heat transfer path formed of the solder layer 48 provided on the upper surface of the main body 44, the two first extending portions 45, and the first extending portion 45 The second heat transfer path formed of the solder layer 48 provided on the upper surface becomes the second heat transfer path located in the three directions of the second semiconductor element 63. Further, the second heat transfer path including the main body 44 and the solder layer 48 provided on the upper surface of the main body 44, and the upper surfaces of the two second extending portions 46 and the second extending portion 46 are provided. The second heat transfer path formed of the solder layer 48 becomes the second heat transfer path located in the three directions of the second semiconductor element 64. The second insulating substrate 43 is interposed between the metal plate 47 and the first wiring metal plate 42 to prevent electrical connection between the metal plate 47 and the first wiring metal plate 42. The second heat transfer path and the first wiring metal plate 42 are electrically insulated.

各第２の配線金属板５０の上面には、負荷に接続される出力電極５１が接合されている。全ての第２の半導体素子６３，６４の上面には、半田層６５が設けられている。半田層６５の上面には、電源に接続される第２の入力電極７２が接合されている。第２の入力電極７２は、矩形平板状をなす本体部７３と、本体部７３の長手方向に沿って３箇所に形成されるとともに本体部７３の短手方向に延びる接続部７４とからなる。各接続部７４は、各第２の配線金属板５０に接合された二つの第２の半導体素子６３，６４の上面に接合されている。   An output electrode 51 connected to a load is joined to the upper surface of each second wiring metal plate 50. A solder layer 65 is provided on the upper surfaces of all the second semiconductor elements 63 and 64. A second input electrode 72 connected to a power source is joined to the upper surface of the solder layer 65. The second input electrode 72 includes a main body portion 73 having a rectangular flat plate shape, and connection portions 74 that are formed at three locations along the longitudinal direction of the main body portion 73 and extend in the short direction of the main body portion 73. Each connection portion 74 is joined to the upper surfaces of the two second semiconductor elements 63 and 64 joined to each second wiring metal plate 50.

第１の配線金属板４２の下面には、第１の絶縁基板４１を介して、放熱部材７５が接合されている。放熱部材７５の内部には、直線状に延びる複数の冷媒通路７６が区画されている。放熱部材７５には、図示しない冷媒流入部及び冷媒流出部が形成されており、冷媒流入部から流入した液状の冷媒が、冷媒通路７６を流通して冷媒流出部から流出するように構成されている。   A heat dissipation member 75 is bonded to the lower surface of the first wiring metal plate 42 via the first insulating substrate 41. Inside the heat radiating member 75, a plurality of refrigerant passages 76 extending linearly are defined. The heat dissipating member 75 is formed with a refrigerant inflow portion and a refrigerant outflow portion (not shown), and the liquid refrigerant flowing from the refrigerant inflow portion flows through the refrigerant passage 76 and flows out from the refrigerant outflow portion. Yes.

次に、半導体モジュール４０の作用について説明する。
本実施形態の半導体モジュール４０は、３相インバータの３相分の上下アームを構成している。半導体モジュール４０が駆動すると、第１の半導体素子６１，６２及び第２の半導体素子６３，６４が発熱する。第２の半導体素子６３，６４が発した熱は、第１の伝熱経路及び第２の伝熱経路を介して第１の配線金属板４２に伝導する。したがって、本実施形態では、第１の配線金属板４２が伝熱層としても機能している。すなわち、伝熱層は、配線層と個別に設けられていなくてもよく、配線層を伝熱層として兼用してもよい。第１の配線金属板４２に伝導した熱は、第１の絶縁基板４１を介して放熱部材７５に伝導し、放熱部材７５の内部（冷媒通路７６）を流通する冷媒と熱交換される。 Next, the operation of the semiconductor module 40 will be described.
The semiconductor module 40 of this embodiment constitutes upper and lower arms for three phases of a three-phase inverter. When the semiconductor module 40 is driven, the first semiconductor elements 61 and 62 and the second semiconductor elements 63 and 64 generate heat. The heat generated by the second semiconductor elements 63 and 64 is conducted to the first wiring metal plate 42 through the first heat transfer path and the second heat transfer path. Therefore, in the present embodiment, the first wiring metal plate 42 also functions as a heat transfer layer. That is, the heat transfer layer may not be provided separately from the wiring layer, and the wiring layer may also be used as the heat transfer layer. The heat conducted to the first wiring metal plate 42 is conducted to the heat radiating member 75 through the first insulating substrate 41 and is heat-exchanged with the refrigerant flowing through the heat radiating member 75 (refrigerant passage 76).

したがって、上記実施形態によれば、第１の実施形態の効果（１）〜（３）、（５）（７）に加えて、以下のような効果を得ることができる。
（８）第２の伝熱経路は、全ての第２の半導体素子６３，６４の複数方向に設けられている。したがって、全ての第２の半導体素子６３，６４を冷却しやすく、第２の半導体素子６３，６４を効率よく冷却することができる。 Therefore, according to the above embodiment, in addition to the effects (1) to (3), (5) and (7) of the first embodiment, the following effects can be obtained.
(8) The second heat transfer path is provided in a plurality of directions of all the second semiconductor elements 63 and 64. Therefore, it is easy to cool all the second semiconductor elements 63 and 64, and the second semiconductor elements 63 and 64 can be efficiently cooled.

（９）第１の配線金属板４２と第２の入力電極７２は、その厚み方向に対向している。第１の配線金属板４２を流れる電流の向きと、第２の入力電極７２に流れる電流の向きは、逆向きとなるため、相互誘導作用によって半導体モジュール４０のインダクタンスを低減させることができる。   (9) The first wiring metal plate 42 and the second input electrode 72 are opposed to each other in the thickness direction. Since the direction of the current flowing through the first wiring metal plate 42 and the direction of the current flowing through the second input electrode 72 are opposite, the inductance of the semiconductor module 40 can be reduced by the mutual induction action.

（１０）第１の配線金属板４２は、配線層及び伝熱層として機能している。このため、伝熱層を別個に設ける必要がなく、部品点数の削減が図られている。
なお、実施形態は、以下のように変更してもよい。 (10) The first wiring metal plate 42 functions as a wiring layer and a heat transfer layer. For this reason, it is not necessary to provide a heat transfer layer separately, and the number of parts is reduced.
In addition, you may change embodiment as follows.

○ 各実施形態において、半導体素子を更に積層してもよい。
○ 各実施形態において、それぞれの第１の半導体素子２１，２２，６１，６２の発熱量の偏りがない場合や、発熱量の偏りが無視できるほど小さい場合には、第１の半導体素子２１，２２，６１，６２の発熱量を考慮して第２の半導体素子２６，２７，６３，６４の位置を決めなくてもよい。また、第１の半導体素子、第２の半導体素子それぞれ２個ずつ用いたが、用途に応じて１個でも、３個以上用いてもよい。 In each embodiment, semiconductor elements may be further stacked.
In each embodiment, when there is no bias in the heat generation amount of each of the first semiconductor elements 21, 22, 61, 62, or when the bias in the heat generation amount is so small that it can be ignored, the first semiconductor elements 21, The positions of the second semiconductor elements 26, 27, 63, 64 may not be determined in consideration of the heat generation amounts 22, 61, 62. Further, although two each of the first semiconductor element and the second semiconductor element are used, one or three or more may be used depending on the application.

○ 各実施形態において、十分に放熱が行える場合には、放熱部材３６，７５を設けなくてもよい。
○ 各実施形態において、放熱部材３６，７５が絶縁性の材料から形成されている場合や、絶縁性の材料でコーティングされている場合には、絶縁基板１１及び第１の絶縁基板４１を設けず、第１の配線金属板１３，４２の下面に放熱部材３６，７５を直接接合してもよい。 In each embodiment, if sufficient heat dissipation can be performed, the heat dissipation members 36 and 75 may not be provided.
In each embodiment, when the heat radiating members 36 and 75 are formed of an insulating material or coated with an insulating material, the insulating substrate 11 and the first insulating substrate 41 are not provided. The heat radiating members 36 and 75 may be directly joined to the lower surfaces of the first wiring metal plates 13 and 42.

○ 各実施形態において、絶縁層として、絶縁性を有する樹脂からなるシートを用いてもよい。
○ 第１の実施形態において、第２の半導体素子２７の複数方向に第２の伝熱経路を設けてもよい。 In each embodiment, a sheet made of an insulating resin may be used as the insulating layer.
In the first embodiment, second heat transfer paths may be provided in a plurality of directions of the second semiconductor element 27.

○ 第１の実施形態において、伝熱層として、金属板１４以外を用いてもよい。例えば、熱伝導率の高い樹脂などを用いてもよい。
○ 第２の実施形態において、第２の半導体素子６３，６４の３方向に第２の伝熱経路を設けたが、第２の半導体素子６３，６４の４方向に第２の伝熱経路を設けてもよい。 In 1st Embodiment, you may use other than the metal plate 14 as a heat-transfer layer. For example, a resin having high thermal conductivity may be used.
In the second embodiment, the second heat transfer path is provided in the three directions of the second semiconductor elements 63 and 64. However, the second heat transfer path is provided in the four directions of the second semiconductor elements 63 and 64. It may be provided.

○ 第２の実施形態において、第２の絶縁基板４３の下面にも金属板を接合しても良い。
○ 第１の実施形態において、半導体モジュール１０は、３相インバータの１相分の上下アームを構成したが、絶縁基板１１や放熱部材３６を共通として３相分の上下アームのモジュールとしてもよい。また、第２の実施形態において、半導体モジュール４０は、３相分の上下アームのモジュールであったが、第１の配線金属板４２を分割し、第１の入力電極７１、第２の入力電極７２をそれぞれ設けて１相分の上下アームのモジュールとしてもよい。 In the second embodiment, a metal plate may be bonded to the lower surface of the second insulating substrate 43.
In the first embodiment, the semiconductor module 10 is configured as the upper and lower arms for one phase of the three-phase inverter. In the second embodiment, the semiconductor module 40 is a module having upper and lower arms for three phases. However, the first wiring metal plate 42 is divided into the first input electrode 71 and the second input electrode. 72 may be provided as upper and lower arm modules for one phase.

次に、上記実施形態及び別例から把握できる技術的思想について以下に追記する。
（イ）前記配線層は、前記伝熱層を兼ねることを特徴とする請求項１〜請求項３のうちいずれか一項に記載の半導体モジュール。 Next, the technical idea that can be grasped from the above embodiment and other examples will be described below.
(A) The semiconductor module according to any one of claims 1 to 3, wherein the wiring layer also serves as the heat transfer layer.

１０，４０…半導体モジュール、１１…絶縁基板、１３，４２…第１の配線金属板、１４…金属板、２１，２２，６１，６２…第１の半導体素子、２５，５０…第２の配線金属板、２６，２７，６３，６４…第２の半導体素子、３２…出力電極、３６，７５…放熱部材、４１…第１の絶縁基板、４７…金属板。   DESCRIPTION OF SYMBOLS 10,40 ... Semiconductor module, 11 ... Insulating substrate, 13, 42 ... 1st wiring metal plate, 14 ... Metal plate, 21, 22, 61, 62 ... 1st semiconductor element, 25, 50 ... 2nd wiring Metal plate, 26, 27, 63, 64 ... second semiconductor element, 32 ... output electrode, 36, 75 ... heat dissipation member, 41 ... first insulating substrate, 47 ... metal plate.

Claims (3)

第１の半導体素子と、
前記第１の半導体素子が接合された第１の配線層と、
前記第１の半導体素子の前記第１の配線層に接合された面と反対側の面に接合された第２の配線層と、
前記第２の配線層の前記第１の半導体素子が接合された面と反対側の面に接合された第２の半導体素子と、を備え、前記第２の半導体素子が発した熱を、前記第１の半導体素子を含む第１の伝熱経路を介して前記第１の配線層に伝導させる半導体モジュールであって、
前記第２の半導体素子が発した熱が伝導され、前記第２の半導体素子に対して前記第２の配線層が配置される側に配置される伝熱層を備え、
前記伝熱層と前記第２の配線層の間には、前記第１の配線層と絶縁されるとともに、前記第２の半導体素子が発した熱を前記伝熱層に伝導させる前記第１の伝熱経路とは異なる第２の伝熱経路が設けられ、
前記第１の配線層の前記第１の半導体素子が接合された面と反対側の面には、絶縁層が設けられるとともに、前記絶縁層の前記第１の配線層が設けられる面と同一面上には、前記第１の配線層と電気的に分離された前記伝熱層が設けられ、前記伝熱層と前記第２の配線層の間には、出力電極が設けられ、前記出力電極が前記第２の伝熱経路を兼ねることを特徴とする半導体モジュール。 A first semiconductor element;
A first wiring layer to which the first semiconductor element is bonded;
A second wiring layer bonded to a surface opposite to the surface bonded to the first wiring layer of the first semiconductor element;
A second semiconductor element bonded to a surface opposite to the surface where the first semiconductor element of the second wiring layer is bonded, and the heat generated by the second semiconductor element is A semiconductor module that conducts to the first wiring layer through a first heat transfer path including a first semiconductor element,
The heat generated by the second semiconductor element is conducted, and a heat transfer layer is provided on a side where the second wiring layer is arranged with respect to the second semiconductor element,
Between the heat transfer layer and the second wiring layer, the first wiring layer is insulated from the first wiring layer and conducts heat generated by the second semiconductor element to the heat transfer layer. A second heat transfer path different from the heat transfer path is provided ,
An insulating layer is provided on the surface of the first wiring layer opposite to the surface to which the first semiconductor element is bonded, and the same surface as the surface of the insulating layer on which the first wiring layer is provided. Above, the heat transfer layer electrically isolated from the first wiring layer is provided, and an output electrode is provided between the heat transfer layer and the second wiring layer, and the output electrode Also serves as the second heat transfer path . 前記第２の伝熱経路は、少なくとも一つの前記第２の半導体素子の複数方向に設けられることを特徴とする請求項１に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the second heat transfer path is provided in a plurality of directions of at least one of the second semiconductor elements. 前記伝熱層には、前記伝熱層に伝導した熱の放熱を行う放熱部材が接合されることを特徴とする請求項１又は請求項２に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein a heat radiating member that radiates heat conducted to the heat transfer layer is joined to the heat transfer layer.
JP2012197105A 2012-09-07 2012-09-07 Semiconductor module Expired - Fee Related JP5942713B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012197105A JP5942713B2 (en) 2012-09-07 2012-09-07 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012197105A JP5942713B2 (en) 2012-09-07 2012-09-07 Semiconductor module

Publications (2)

Publication Number Publication Date
JP2014053457A JP2014053457A (en) 2014-03-20
JP5942713B2 true JP5942713B2 (en) 2016-06-29

Family

ID=50611661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012197105A Expired - Fee Related JP5942713B2 (en) 2012-09-07 2012-09-07 Semiconductor module

Country Status (1)

Country Link
JP (1) JP5942713B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018150449A1 (en) * 2017-02-14 2018-08-23 日本精工株式会社 Semiconductor module and production method therefor, drive device equipped with semiconductor module, and electric power steering device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112009005394T8 (en) * 2009-11-25 2012-12-20 Toyota Jidosha Kabushiki Kaisha Cooling structure of a semiconductor device
JP2011114176A (en) * 2009-11-27 2011-06-09 Mitsubishi Electric Corp Power semiconductor device

Also Published As

Publication number Publication date
JP2014053457A (en) 2014-03-20

Similar Documents

Publication Publication Date Title
JP5627499B2 (en) Semiconductor device provided with semiconductor module
JP5924164B2 (en) Semiconductor device
JP5206102B2 (en) Semiconductor device
JP4478618B2 (en) Power semiconductor module
JP7284566B2 (en) semiconductor equipment
JP5696696B2 (en) Semiconductor device
WO2009150875A1 (en) Power module and control method therefore
JP4531087B2 (en) Power semiconductor device
JP2017195687A (en) Electric power conversion system
CN110506330B (en) Power electronic module and electric power converter comprising the same
JP3643525B2 (en) Inverter device
JP2013105882A (en) Semiconductor module
JP5845835B2 (en) Semiconductor module
JP2011211017A (en) Semiconductor module and semiconductor device including the same
JP5942713B2 (en) Semiconductor module
JP2009021445A (en) Inverter apparatus
JP2018037545A (en) Semiconductor module
JP2009117701A (en) Power module
JP7196761B2 (en) semiconductor equipment
JP5402778B2 (en) Semiconductor device provided with semiconductor module
JP2014096412A (en) Semiconductor module
JP2021082804A (en) Semiconductor module
WO2019102665A1 (en) Semiconductor device, power module, and power supply device
JP2015053775A (en) Semiconductor power conversion device
JP2016101071A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20141112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160127

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160202

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160330

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160426

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160509

R151 Written notification of patent or utility model registration

Ref document number: 5942713

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees