JP7114824B1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7114824B1 JP7114824B1 JP2022522573A JP2022522573A JP7114824B1 JP 7114824 B1 JP7114824 B1 JP 7114824B1 JP 2022522573 A JP2022522573 A JP 2022522573A JP 2022522573 A JP2022522573 A JP 2022522573A JP 7114824 B1 JP7114824 B1 JP 7114824B1
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Abstract
Description
[1.半導体装置の構造]
以下では、本開示における縦型電界効果トランジスタの直交型構造についてデュアル構成を例にとって説明する。デュアル構成であることは必須ではなく、シングル構成の縦型電界効果トランジスタであってもよく、トリプル以上の構成の縦型電界効果トランジスタであってもよい。
図3Aおよび図3Bは、それぞれ、半導体装置1のX方向およびY方向に繰り返し形成される、トランジスタ10(またはトランジスタ20)の略単位構成の、平面図および斜視図である。図3Aおよび図3Bでは、分かりやすくするために半導体基板32、第1のソース電極11(または第2のソース電極21)は図示していない。なおY方向とは、半導体層40の上面と平行し、第1のトレンチ17および第2のトレンチ27が延在する方向(第1の方向)である。またX方向とは、半導体層40の上面と平行し、Y方向に直交する方向(第2の方向)のことをいう。
トランジスタ10(またはトランジスタ20)には、構造上、寄生バイポーラトランジスタが備わっている。寄生バイポーラトランジスタは、駆動していた半導体装置をオフした時(ターンオフ時)にオンしやすく、オフする直前までの駆動電圧が大きいほどオンしやすい。半導体装置1をオフした時、寄生バイポーラトランジスタがオンしない駆動電圧のうち最大のものを、本願ではターンオフ時耐圧(Voff)とよぶ。例えば10V駆動時からのオフでは寄生バイポーラトランジスタがオンしない一方で、11V駆動時からのオフでは寄生バイポーラトランジスタがオンすることが分かった場合、その半導体装置のターンオフ時耐圧は10V以上11V未満である。なお、半導体装置1がデュアル構成のN導電型の縦型電界効果トランジスタである場合、駆動電圧とはソース-ソース間電圧(VSS)のことであり、シングル構成の縦型電界効果トランジスタである場合、駆動電圧とはドレイン-ソース間電圧(VDS)のことである。また半導体装置1がデュアル構成のP導電型の縦型電界効果トランジスタである場合、駆動電圧とはドレイン-ドレイン間電圧(VDD)のことである。駆動とは、ゲート導体に電圧を印加してソース-ソース間(もしくはドレイン-ソース間、あるいはドレイン-ドレイン間)に電流を導通している状態のことをいい、特にことわらない限り、線形領域の条件で導通させることをいうものとする。
本発明者らはトランジスタ10の駆動時に、第1の接続部18Aの直下にある第1のボディ領域18を効率的に導通に寄与させて、オン抵抗の低減とターンオフ時の耐量の向上を両立することを見出した。図4A~図4Fおよび図5A-1~図5B-3を用いて説明する。
上記効果を有効に活用すれば、ベース抵抗Rb1を抑制するために第1のソース領域14の長さLS1を短くしても、第1の接続部18Aの長さLB1を一定程度まで短くすれば駆動時の導通チャネルを実効的に拡大し、オン抵抗を低減することができる。したがってオン抵抗の低減とターンオフ時の耐量の向上を両立することができる。
実施形態1および図5において、第1の接続部18Aの長さLB1を制御することで、第1のトレンチ17に沿うY方向の全長を導通に寄与させることができることを説明した。同様の効果はX方向においても期待することができる。これはY方向においては第1の接続部18Aであった対象が、X方向では、第1のトレンチ17と、隣り合う別の第1のトレンチ17との間の距離Lxmに置き換わることに他ならない。
第1のソース領域14(または第2のソース領域24)の構造は、その機能に応じてZ方向(半導体装置の深さ方向)で適切に変更することができる。図11A、図11Bに示すように、第1のソース領域14を、半導体層40の上面側に位置する上部側部分141と、第1のボディ領域18との境界側に位置する底部側部分142として、Z方向で構造を作り分けてもよい。
10 トランジスタ(第1の縦型電界効果トランジスタ)
11 第1のソース電極
12、13 部分
14 第1のソース領域
15 第1のゲート導体
16 第1のゲート絶縁膜
17 第1のトレンチ
18 第1のボディ領域
18A 第1の接続部
19 第1のゲート電極
20 トランジスタ(第2の縦型電界効果トランジスタ)
21 第2のソース電極
22、23 部分
24 第2のソース領域
25 第2のゲート導体
26 第2のゲート絶縁膜
27 第2のトレンチ
28 第2のボディ領域
28A 第2の接続部
29 第2のゲート電極
30 金属層
32 半導体基板
33 低濃度不純物層またはドリフト層
34 層間絶縁層
35 パッシベーション層
40 半導体層
90C 境界
116 第1のソース電極パッド
119 第1のゲート電極パッド
126 第2のソース電極パッド
129 第2のゲート電極パッド
141 上部側部分
142 底部側部分
Claims (10)
- フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
シリコンからなり第1導電型の不純物を含む半導体基板と、
前記半導体基板上に接して形成され、前記半導体基板の前記第1導電型の不純物の濃度より低い濃度の前記第1導電型の不純物を含む低濃度不純物層と、
前記低濃度不純物層の表面に形成された前記第1導電型と異なる第2導電型のボディ領域と、
前記ボディ領域の表面に形成された前記第1導電型のソース領域と、
前記ソース領域と電気的に接続されたソース電極と、
前記半導体基板上面と平行な第1の方向に延在し、かつ前記第1の方向と直交する第2の方向において等間隔に、前記低濃度不純物層上面から前記ボディ領域を貫通して前記低濃度不純物層の一部までの深さに形成された複数のトレンチと、
前記複数のトレンチの表面の少なくとも一部を覆うように形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート導体と、
前記ボディ領域と前記ソース電極とを電気的に接続する接続部と、を有する縦型電界効果トランジスタを備え、
前記縦型電界効果トランジスタには、前記第1の方向において、前記ソース領域と前記接続部とが交互かつ周期的に設置されており、
前記第2の方向において隣り合う前記トレンチとトレンチとの間の距離をLxm[μm]、1の前記トレンチの内部幅をLxr[μm]としたとき、
Lxm≦Lxr≦0.20μmが成り立ち、
前記縦型電界効果トランジスタの仕様最大電圧をVss[V]とするとき、
前記第1の方向における1の前記ソース領域の長さLS[μm]と、前記第1の方向における1の前記接続部の長さLB[μm]が
LB<0.35μm
かつLS≦0.12×Vss×Lxm-0.76×Lxm-0.05×Vss+1.26[μm]の関係にある
半導体装置。 - LB<0.30μmである
請求項1に記載の半導体装置。 - 前記第2の方向において隣り合う前記トレンチとトレンチとの間の距離Lxm[μm]は、前記第1の方向における前記接続部の長さLB[μm]以下であり、
前記第1の方向における任意の位置において、前記トレンチから隣接する別の前記トレンチまでの間の領域を、前記第1の方向と前記第2の方向とに直交する第3の方向の任意の位置にて前記第2の方向に沿って見たとき、導電型の異なる複数の層が交互に備わることがない
請求項1に記載の半導体装置。 - 前記縦型電界効果トランジスタの前記接続部の前記第1の方向における長さは、前記ゲート導体へ仕様の値の電圧を印加して前記縦型電界効果トランジスタに仕様の値の電流を流すときの前記縦型電界効果トランジスタのオン抵抗が前記接続部の長さをさらに短くしても著しく低減することのない収束域にある
請求項3に記載の半導体装置。 - Lxm≦Lxr/2が成り立つ
請求項3に記載の半導体装置。 - 前記第1の方向と前記第2の方向とに直交する第3の方向において、
前記ソース領域は、前記低濃度不純物層の上面側に位置し、前記第1の方向における長さが一定である上部側部分と、前記ボディ領域との境界側に位置し、前記第1の方向における長さが変化する底部側部分とを有し、
前記第1の方向における前記上部側部分の長さを上部ソース長さとし、前記第1の方向における前記底部側部分の長さが最大となる長さを底部ソース長さとしたとき、
前記底部ソース長さは、前記ソース領域の前記第3の方向における中央よりも底部側における前記底部側部分の長さであり、
前記底部ソース長さは、前記上部ソース長さよりも長く、前記ソース領域の長さは、前記底部ソース長さと一致する
請求項1に記載の半導体装置。 - 1の前記ソース領域の前記上部側部分と前記底部側部分は、前記第1の方向において、中央の位置が同じである
請求項6に記載の半導体装置。 - 前記第1の方向における1の前記ソース領域の長さの1の前記接続部の長さに対する比は、前記上部側において1未満であり、前記底部側において1以上である
請求項6に記載の半導体装置。 - 前記上部側において、
前記第1の方向における1の前記ソース領域の長さと1の前記接続部の長さの差は、0.20μm以下である
請求項8に記載の半導体装置。 - 前記ソース領域の前記上部側部分の不純物濃度は、当該ソース領域の前記底部側部分の不純物濃度よりも高い
請求項6に記載の半導体装置。
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