JP7079328B2 - Ldmosデバイスの製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 241000473391 Archosargus rhomboidalis Species 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Description
前記トップ埋込層とフィールド酸化絶縁層構造まで伸びさせて前記トップ埋込層の一部を除去するように、前記第一導電タイプのドープ領域にトレンチを開口することと、
第二導電タイプのイオンを注入して、前記トレンチの下にウェル領域を形成することと、
前記ウェル領域内にソースドープ領域を形成することと、を含み、
前記第一導電タイプと第二導電タイプは互いに逆となるものであることを特徴とするLDMOSデバイスの製造方法。
前記基板上に設けられ、ドリフト領域として用いられる第一導電タイプのドープ領域と、
前記第一導電タイプのドープ領域に開口されたトレンチと、
第二導電タイプを有し、前記トレンチの下に設けられたウェル領域と、
前記ウェル領域内に設けられたソースドープ領域と、
第二導電タイプを有し、前記第一導電タイプのドープ領域内に設けられ、一端が前記トレンチまで伸びているトップ埋込層と、
前記トップ埋込層の上に設けられ、一端が前記トレンチまで伸びているフィールド酸化絶縁層構造と、を備え、
前記第一導電タイプと第二導電タイプは互いに逆となるものであることを特徴とするLDMOSデバイス。
Claims (7)
- 第一導電タイプのドープ領域が形成され、前記第一導電タイプのドープ領域内にトップ埋込層が形成され、前記トップ埋込層上にフィールド酸化絶縁層構造が形成されたウェハを取得することと、
前記トップ埋込層とフィールド酸化絶縁層構造まで伸びさせて前記トップ埋込層の一部を除去するように、前記第一導電タイプのドープ領域にトレンチを開口することと、
第二導電タイプのイオンを注入して、前記トレンチの下にウェル領域を形成することと、
前記ウェル領域内にソースドープ領域を形成することと、を含み、
前記第一導電タイプと第二導電タイプは互いに逆となるものであり、
前記した前記第一導電タイプのドープ領域にトレンチを開口することは、前記フィールド酸化絶縁層構造をハードマスクとしてエッチングを行うことであることを特徴とするLDMOSデバイスの製造方法。 - 前記した前記第一導電タイプのドープ領域にトレンチを開口することにより形成されたトレンチの底部は、前記トップ埋込層の底部よりも低いことを特徴とする、請求項1に記載の方法。
- 前記した第一導電タイプのドープ領域が形成され、前記第一導電タイプのドープ領域内にトップ埋込層が形成され、前記トップ埋込層上にフィールド酸化絶縁層構造が形成されたウェハを取得することは、
前記第一導電タイプのドープ領域内に前記トップ埋込層を形成することと、
前記トップ埋込層を部分的に覆うように前記トップ埋込層上に前記フィールド酸化絶縁層構造を形成することと、を含み、
前記トップ埋込層は、前記トレンチに近い箇所における一部が前記フィールド酸化絶縁層構造の下から露出していることを特徴とする、請求項1に記載の方法。 - 第一導電タイプのドープ領域にトレンチを開口した後に、前記トレンチの底部及び前記トレンチにおけるトップ埋込層に近い側壁において連続したゲート酸化構造を形成することを含むことを特徴とする、請求項1に記載の方法。
- 前記ゲート酸化構造は、さらに前記フィールド酸化絶縁層構造の表面の一部まで伸びていることを特徴とする、請求項4に記載の方法。
- 前記したウェル領域内にソースドープ領域を形成することは、前記ウェル領域内に第一導電タイプのソースドープ領域と第二導電タイプのソースドープ領域を形成することであり、第一導電タイプのソースドープ領域が位置する箇所は第二導電タイプのソースドープ領域よりも前記トップ埋込層に近いことを特徴とする、請求項1に記載の方法。
- 前記第一導電タイプのドープ領域内にドレインドープ領域を形成することをさらに含み、前記ドレインドープ領域と前記ソースドープ領域は前記フィールド酸化絶縁層構造により離間され、前記ドレインドープ領域は第一導電タイプを有することを特徴とする、請求項6に記載の方法。
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CN201711278066.7A CN109888015A (zh) | 2017-12-06 | 2017-12-06 | Ldmos器件及其制备方法 |
PCT/CN2018/119252 WO2019109924A1 (zh) | 2017-12-06 | 2018-12-05 | Ldmos器件及其制备方法 |
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CN115132822A (zh) * | 2022-05-19 | 2022-09-30 | 深圳基本半导体有限公司 | 一种ldmos器件及其制作方法和应用 |
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US20150194506A1 (en) | 2014-01-06 | 2015-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming integrated circuit having modified isolation structure |
JP2015204308A (ja) | 2014-04-10 | 2015-11-16 | 旭化成エレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2017073410A (ja) | 2015-10-05 | 2017-04-13 | 株式会社日立製作所 | 半導体装置および半導体装置の製造方法 |
US20170194491A1 (en) | 2015-12-31 | 2017-07-06 | Globalfoundries Singapore Pte. Ltd. | High voltage device with low rdson |
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JP2021506118A (ja) | 2021-02-18 |
WO2019109924A1 (zh) | 2019-06-13 |
CN109888015A (zh) | 2019-06-14 |
KR102333100B1 (ko) | 2021-12-02 |
KR20200079318A (ko) | 2020-07-02 |
US20210175347A1 (en) | 2021-06-10 |
US11309406B2 (en) | 2022-04-19 |
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