JP7005356B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7005356B2 JP7005356B2 JP2018007227A JP2018007227A JP7005356B2 JP 7005356 B2 JP7005356 B2 JP 7005356B2 JP 2018007227 A JP2018007227 A JP 2018007227A JP 2018007227 A JP2018007227 A JP 2018007227A JP 7005356 B2 JP7005356 B2 JP 7005356B2
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- 239000004065 semiconductor Substances 0.000 title claims description 144
- 238000004519 manufacturing process Methods 0.000 title claims description 48
- 239000002184 metal Substances 0.000 claims description 203
- 229910052751 metal Inorganic materials 0.000 claims description 203
- 238000000034 method Methods 0.000 claims description 62
- 239000000758 substrate Substances 0.000 claims description 37
- 230000001681 protective effect Effects 0.000 claims description 32
- 239000003963 antioxidant agent Substances 0.000 claims description 29
- 230000003078 antioxidant effect Effects 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000007772 electroless plating Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000007747 plating Methods 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 10
- 238000007740 vapor deposition Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008642 heat stress Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description
(半導体装置の構成)
図1は、実施の形態1における半導体装置の構成を示す断面図である。半導体装置は、半導体基板1、第1電極2、第3電極3、保護膜4、第1金属膜5、第2電極6、第2金属膜7および第3金属膜8で構成される。
実施の形態1における半導体装置の製造方法を説明する。図2は、実施の形態1における半導体装置の製造方法を示すフローチャートである。
実施の形態1における半導体装置の製造方法についての効果を説明する前に、前提技術を説明する。図3は、前提技術における半導体装置の構成を示す断面図である。前提技術における半導体装置は、第1金属膜5および第2金属膜7が設けられていない点で、図1に示される半導体装置と相違する。前提技術における半導体装置の表面1a側に形成された第3金属膜8と、裏面1b側に形成された第3金属膜8との体積差により、半導体装置は上に凸、つまり表面1a側に凸の形状を有する。
実施の形態1における半導体装置の製造方法においては、保護膜4の開口部の割合に応じて第1金属膜5の厚さt1と第2金属膜7の厚さt2との比率が調整される。第1金属膜5の厚さt1および第2金属膜7の厚さt2は、t1>t2の関係を有する。それにより、第1金属膜5および第2金属膜7の厚さの差によって発生する応力が制御可能となり、反りの方向および反り量が調整される。
実施の形態2における半導体装置および半導体装置の製造方法を説明する。なお、実施の形態1と同様の構成および動作については説明を省略する。
以上のように、実施の形態2における半導体装置の製造方法においては、第1電極2および第1金属膜5を形成した後、半導体基板1の一方の主面に、第1電極2および第1金属膜5がそれぞれ有するパターンの端部を覆う保護膜4を形成する。
実施の形態3における半導体装置および半導体装置の製造方法を説明する。なお、実施の形態1または2と同様の構成および動作については説明を省略する。
以上のように、実施の形態3における半導体装置の製造方法においては、第1電極2を形成する際に、半導体基板1の一方の主面に、第1導電膜をパターニングすることにより、第1電極2とは離間して設けられる第3電極3をさらに形成し、第1金属膜5を形成する際に、第1金属膜5は第3電極3上を除いて形成される。
実施の形態4における半導体装置および半導体装置の製造方法を説明する。なお、実施の形態1から3のいずれかと同様の構成および動作については説明を省略する。
以上のように、実施の形態4における半導体装置の製造方法においては、第1金属膜5を形成した後に続いて、第1金属膜5上に、第1金属膜5の表面の酸化を防止する第1酸化防止膜9を形成し、第2金属膜7を形成した後に続いて、第2金属膜7上に、第2金属膜7の表面の酸化を防止する第2酸化防止膜10を形成し、第3金属膜8を無電解めっきによって一括して形成する前に、第1酸化防止膜9と第2酸化防止膜10とを除去する。
Claims (6)
- 半導体基板の一方の主面に、第1導電膜を堆積してパターニングすることにより、第1電極を形成し、
前記第1電極上に、前記第1電極が有するパターンに対応する第1金属膜を形成し、
前記半導体基板の前記一方の主面に、前記第1電極の前記パターンの端部を覆い、かつ、前記第1電極の一部と前記第1金属膜の少なくとも一部とが露出する開口部を含む保護膜を形成し、
前記半導体基板の他方の主面に、第2導電膜を堆積することにより、第2電極を形成し、
前記第2電極上に、前記第1金属膜よりも薄い第2金属膜を形成し、
前記開口部内の前記第1金属膜上および前記第2金属膜上のそれぞれに第3金属膜を、無電解めっきによって一括に形成し、
前記第1金属膜と前記第2金属膜とは、前記第3金属膜の形成後における前記半導体基板の反りが低減するように、前記保護膜の前記開口部の割合に応じて規定されたそれぞれの厚さで形成される、半導体装置の製造方法。 - 前記保護膜は、前記第1電極および前記第1金属膜を形成した後、前記半導体基板の前記一方の主面に、前記第1電極の前記パターンの前記端部と前記第1金属膜が有するパターンの端部との両方を覆うように形成される、請求項1に記載の半導体装置の製造方法。
- 前記第1電極を形成する際に、前記半導体基板の前記一方の主面に、前記第1導電膜をパターニングすることにより、前記第1電極とは離間して設けられる第3電極をさらに形成し、
前記第1金属膜を形成する際に、前記第1金属膜は前記第3電極上を除いて形成され、
前記半導体基板は、前記第1電極と前記第2電極と前記第3電極とを含む半導体素子を含み、
前記第3電極は、前記半導体素子のスイッチング動作を制御するための電圧信号が印加される電極である、請求項1または請求項2に記載の半導体装置の製造方法。 - 半導体基板の一方の主面に、第1導電膜を堆積してパターニングすることにより、第1電極を形成し、
前記第1電極上に、前記第1電極が有するパターンに対応する第1金属膜を形成し、
前記半導体基板の他方の主面に、第2導電膜を堆積することにより、第2電極を形成し、
前記第2電極上に、前記第1金属膜よりも薄い第2金属膜を形成し、
前記第1金属膜上および前記第2金属膜上のそれぞれに第3金属膜を、無電解めっきによって一括に形成し、
前記第1金属膜を形成した後に、前記第1金属膜上に、前記第1金属膜の表面の酸化を防止する第1酸化防止膜を形成し、
前記第2金属膜を形成した後に、前記第2金属膜上に、前記第2金属膜の表面の酸化を防止する第2酸化防止膜を形成し、
前記第3金属膜を前記無電解めっきによって一括して形成する前に、前記第1酸化防止膜と前記第2酸化防止膜とを除去する、半導体装置の製造方法。 - 前記第1電極および前記第1金属膜を形成した後、前記半導体基板の前記一方の主面に、前記第1電極の前記パターンの端部と前記第1金属膜が有するパターンの端部とを覆う保護膜を形成する、請求項4に記載の半導体装置の製造方法。
- 前記第1電極を形成する際に、前記半導体基板の前記一方の主面に、前記第1導電膜をパターニングすることにより、前記第1電極とは離間して設けられる第3電極をさらに形成し、
前記第1金属膜を形成する際に、前記第1金属膜は前記第3電極上を除いて形成され、
前記半導体基板は、前記第1電極と前記第2電極と前記第3電極とを含む半導体素子を含み、
前記第3電極は、前記半導体素子のスイッチング動作を制御するための電圧信号が印加される電極である、請求項4または請求項5に記載の半導体装置の製造方法。
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