JP6899976B1 - パワー半導体モジュール及び電力変換装置 - Google Patents
パワー半導体モジュール及び電力変換装置 Download PDFInfo
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- JP6899976B1 JP6899976B1 JP2020564287A JP2020564287A JP6899976B1 JP 6899976 B1 JP6899976 B1 JP 6899976B1 JP 2020564287 A JP2020564287 A JP 2020564287A JP 2020564287 A JP2020564287 A JP 2020564287A JP 6899976 B1 JP6899976 B1 JP 6899976B1
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Abstract
Description
図1から図6を参照して、実施の形態1のパワー半導体モジュール1を説明する。パワー半導体モジュール1は、絶縁回路基板10と、複数の自己消弧型半導体素子20aと、プリント配線基板30と、複数の導電接合部材25aと、複数の導電ゲートワイヤ50aと、導電ブロック40と、電極端子42と、電極端子44と、第1ソース制御端子46と、導電ワイヤ47と、第1ゲート制御端子48と、導電ワイヤ49とを主に備える。パワー半導体モジュール1は、複数の第1還流ダイオード20hをさらに備えてもよい。
パワー半導体モジュール1では、複数の自己消弧型半導体素子20aのソース電極22aは、複数の導電接合部材25aによって、ソース導電パターン33に接合されている。これに対し、複数の自己消弧型半導体素子20aのゲート電極23aは、複数の導電ゲートワイヤ50aによって、ゲート導電パターン36に接続されている。複数の導電接合部材25aの各々の厚さは、複数の導電ゲートワイヤ50aの各々の長さよりも小さい。複数の導電接合部材25aの各々の断面積は、複数の導電ゲートワイヤ50aの各々の断面積よりも大きい。複数の導電接合部材25aの各々の断面積は、複数の導電接合部材25aの各々の厚さ方向(第3方向(z方向))に垂直な複数の導電接合部材25aの各々の断面の面積として定義される。複数の導電ゲートワイヤ50aの各々の断面積は、複数の導電ゲートワイヤ50aの各々の長手方向に垂直な複数の導電ゲートワイヤ50aの各々の断面の面積として定義される。
本実施の形態のパワー半導体モジュール1は、絶縁回路基板10と、複数の第1自己消弧型半導体素子(複数の自己消弧型半導体素子20a)と、プリント配線基板30と、複数の第1導電接合部材(複数の導電接合部材25a)と、複数の第1導電ゲートワイヤ(複数の導電ゲートワイヤ50a)とを備える。絶縁回路基板10は、第1主面12aを含む絶縁板12と、第1主面12a上に設けられている第1導電回路パターン13とを含む。プリント配線基板30は、絶縁板12の第1主面12aに対向して配置されている。プリント配線基板30は、絶縁基板31と、第1ソース導電パターン(ソース導電パターン33)と、第1ゲート導電パターン(ゲート導電パターン36)とを含む。絶縁基板31は、第1主面12aに対向する第2主面31aと、第2主面31aとは反対側の第3主面31bとを含む。絶縁基板31の第3主面31bの平面視において、絶縁基板31は、第1縁31cと、第1縁31cとは反対側の第2縁31dとを含む。複数の第1自己消弧型半導体素子は、それぞれ、第1ソース電極(ソース電極22a)と、第1ゲート電極(ゲート電極23a)と、第1ドレイン電極(ドレイン電極21a)とを含む。
図7及び図8を参照して、実施の形態2のパワー半導体モジュール1bを説明する。本実施の形態のパワー半導体モジュール1bは、実施の形態1のパワー半導体モジュール1と同様の構成を備えるが、以下の点で主に異なる。
図9から図15を参照して、実施の形態3のパワー半導体モジュール1cを説明する。本実施の形態のパワー半導体モジュール1cは、実施の形態1のパワー半導体モジュール1と同様の構成を備えるが、以下の点で主に異なる。
図16から図23を参照して、実施の形態4のパワー半導体モジュール1dを説明する。本実施の形態のパワー半導体モジュール1dは、実施の形態1のパワー半導体モジュール1と同様の構成を備えるが、以下の点で主に異なる。
図24から図31を参照して、実施の形態5のパワー半導体モジュール1eを説明する。本実施の形態のパワー半導体モジュール1eは、実施の形態3のパワー半導体モジュール1cと同様の構成を備えるが、以下の点で主に異なる。
本実施の形態は、上述した実施の形態1から実施の形態5のパワー半導体モジュール1,1b,1c,1d,1eを電力変換装置に適用したものである。本開示は特定の電力変換装置に限定されるものではないが、以下、実施の形態6として、三相のインバータに本開示のパワー半導体モジュール1,1b,1c,1d,1eを適用した場合について説明する。
Claims (19)
- 第1主面を含む絶縁板と、前記第1主面上に設けられている第1導電回路パターンとを含む絶縁回路基板と、
複数の第1自己消弧型半導体素子と、
前記第1主面に対向して配置されているプリント配線基板と、
複数の第1導電接合部材と、
複数の第1導電ゲートワイヤとを備え、
前記プリント配線基板は、絶縁基板と、第1ソース導電パターンと、第1ゲート導電パターンとを含み、
前記絶縁基板は、前記第1主面に対向する第2主面と、前記第2主面とは反対側の第3主面とを含み、
前記第3主面の平面視において、前記絶縁基板は、第1縁と、前記第1縁とは反対側の第2縁とを含み、
前記複数の第1自己消弧型半導体素子は、それぞれ、第1ソース電極と、第1ゲート電極と、第1ドレイン電極とを含み、
前記複数の第1自己消弧型半導体素子の前記第1ドレイン電極は、前記第1導電回路パターンに接合されており、
前記複数の第1自己消弧型半導体素子の前記第1ソース電極は、前記複数の第1導電接合部材によって、前記第1ソース導電パターンに接合されており、
前記複数の第1導電ゲートワイヤは、前記複数の第1自己消弧型半導体素子の前記第1ゲート電極と前記第1ゲート導電パターンとを互いに接続しており、
前記第3主面の前記平面視において、前記第1ゲート導電パターンの第1長手方向は、前記複数の第1自己消弧型半導体素子の第1配列方向であり、
前記第3主面の前記平面視において、前記第1ゲート導電パターンは、前記複数の第1自己消弧型半導体素子にわたって連続的に設けられている、パワー半導体モジュール。 - 前記複数の第1自己消弧型半導体素子は、前記第2主面に対向しており、
前記第1ゲート導電パターンは、前記第3主面上に設けられている、請求項1に記載のパワー半導体モジュール。 - 第1主面を含む絶縁板と、前記第1主面上に設けられている第1導電回路パターンとを含む絶縁回路基板と、
複数の第1自己消弧型半導体素子と、
前記第1主面に対向して配置されているプリント配線基板と、
複数の第1導電接合部材と、
複数の第1導電ゲートワイヤとを備え、
前記プリント配線基板は、絶縁基板と、第1ソース導電パターンと、第1ゲート導電パターンとを含み、
前記絶縁基板は、前記第1主面に対向する第2主面と、前記第2主面とは反対側の第3主面とを含み、
前記第3主面の平面視において、前記絶縁基板は、第1縁と、前記第1縁とは反対側の第2縁とを含み、
前記複数の第1自己消弧型半導体素子は、それぞれ、第1ソース電極と、第1ゲート電極と、第1ドレイン電極とを含み、
前記複数の第1自己消弧型半導体素子の前記第1ドレイン電極は、前記第1導電回路パターンに接合されており、
前記複数の第1自己消弧型半導体素子の前記第1ソース電極は、前記複数の第1導電接合部材によって、前記第2主面上に設けられている前記第1ソース導電パターンに接合されており、
前記複数の第1導電ゲートワイヤは、前記複数の第1自己消弧型半導体素子の前記第1ゲート電極と前記第3主面上に設けられている前記第1ゲート導電パターンとを互いに接
続しており、
前記第3主面の前記平面視において、前記第1ゲート導電パターンの第1長手方向は、前記複数の第1自己消弧型半導体素子の第1配列方向である、パワー半導体モジュール。 - 前記第1ゲート導電パターンの前記第1長手方向における前記第1ゲート導電パターンの第1長さは、前記複数の第1自己消弧型半導体素子の前記第1配列方向における前記複数の第1自己消弧型半導体素子の第2長さ以上である、請求項1から請求項3のいずれか一項に記載のパワー半導体モジュール。
- 前記第3主面の前記平面視において、前記第1ゲート導電パターンは、前記絶縁基板の前記第1縁に沿って配置されており、
前記複数の第1自己消弧型半導体素子は、前記絶縁基板の前記第1縁に沿って配置されている、請求項1から請求項4のいずれか一項に記載のパワー半導体モジュール。 - 前記第1ゲート導電パターンは、前記第3主面の前記平面視において、前記第1ソース導電パターンの縁に沿って配置されている、請求項1から請求項5のいずれか一項に記載のパワー半導体モジュール。
- 前記第1ゲート導電パターンのうち、前記第3主面の前記平面視において前記第1ゲート導電パターンの前記第1長手方向で前記複数の第1自己消弧型半導体素子に対応する第1ゲート導電パターン部分の第1幅は、前記第1ソース導電パターンのうち、前記第3主面の前記平面視において前記第1ゲート導電パターンの前記第1長手方向で前記複数の第1自己消弧型半導体素子に対応する第1ソース導電パターン部分の第2幅より小さく、
前記第1ゲート導電パターン部分の前記第1幅は、前記第1長手方向に垂直な前記第1ゲート導電パターンの第1短手方向における前記第1ゲート導電パターン部分の長さであり、
前記第1ソース導電パターン部分の前記第2幅は、前記第1ゲート導電パターンの前記第1短手方向における前記第1ソース導電パターン部分の長さである、請求項1から請求項6のいずれか一項に記載のパワー半導体モジュール。 - 前記第3主面の前記平面視において、前記複数の第1導電ゲートワイヤの少なくとも一つは、前記第1ゲート導電パターンの前記第1長手方向に対して斜めの方向に延在している、請求項1から請求項7のいずれか一項に記載のパワー半導体モジュール。
- 前記複数の第1導電ゲートワイヤの前記少なくとも一つは、前記複数の第1自己消弧型半導体素子の少なくとも一つの前記第1ゲート電極にボンディングされている第1端と、前記第1ゲート導電パターンにボンディングされている第2端とを有しており、
前記第1ゲート導電パターンの前記第1長手方向における前記第1端と前記第2端との間の間隔は、前記第1ゲート導電パターンの前記第1長手方向における前記複数の第1自己消弧型半導体素子の前記少なくとも一つの幅以下である、請求項8に記載のパワー半導体モジュール。 - 第1電極端子と、
第2電極端子とをさらに備え、
前記第1電極端子は、前記第1ソース電極と前記第1ドレイン電極との間を流れる第1主電流の第1経路の、前記パワー半導体モジュールにおける第1経路端であり、
前記第2電極端子は、前記第1主電流の前記第1経路の、前記パワー半導体モジュールにおける第2経路端であり、
前記第1電極端子は、導電ワイヤ無しに、前記第1ソース導電パターンを介して、前記第1ソース電極に電気的に接続されており、
前記第2電極端子は、導電ワイヤ無しに、前記第1導電回路パターンを介して、前記第1ドレイン電極に電気的に接続されている、請求項1から請求項9のいずれか一項に記載のパワー半導体モジュール。 - 複数の第2自己消弧型半導体素子と、
複数の第2導電接合部材と、
複数の第2導電ゲートワイヤとをさらに備え、
前記プリント配線基板は、前記第1ゲート導電パターンに電気的に接続されている第2ゲート導電パターンをさらに含み、
前記複数の第2自己消弧型半導体素子は、それぞれ、第2ソース電極と、第2ゲート電極と、第2ドレイン電極とを含み、
前記複数の第2自己消弧型半導体素子の前記第2ドレイン電極は、前記第1導電回路パターンに接合されており、
前記複数の第2自己消弧型半導体素子の前記第2ソース電極は、前記複数の第2導電接合部材によって、前記第1ソース導電パターンに接合されており、
前記複数の第2導電ゲートワイヤは、前記複数の第2自己消弧型半導体素子の前記第2ゲート電極と前記第2ゲート導電パターンとを互いに接続しており、
前記第3主面の前記平面視において、前記第2ゲート導電パターンの第2長手方向は、前記複数の第2自己消弧型半導体素子の第2配列方向である、請求項1から請求項10のいずれか一項に記載のパワー半導体モジュール。 - 前記第2ゲート導電パターンのうち、前記第3主面の前記平面視において前記第2ゲート導電パターンの前記第2長手方向で前記複数の第2自己消弧型半導体素子に対応する第2ゲート導電パターン部分の第3幅は、前記第1ソース導電パターンのうち、前記第3主面の前記平面視において前記第2ゲート導電パターンの前記第2長手方向で前記複数の第2自己消弧型半導体素子に対応する第2ソース導電パターン部分の第4幅より小さく、
前記第2ゲート導電パターン部分の前記第3幅は、前記第2長手方向に垂直な前記第2ゲート導電パターンの第2短手方向における前記第2ゲート導電パターン部分の長さであり、
前記第2ソース導電パターン部分の前記第4幅は、前記第2ゲート導電パターンの前記第2短手方向における前記第2ソース導電パターン部分の長さである、請求項11に記載のパワー半導体モジュール。 - 複数の第2自己消弧型半導体素子と、
複数の第2導電接合部材と、
複数の第2導電ゲートワイヤとをさらに備え、
前記絶縁回路基板は、前記第1主面上に設けられており、かつ、前記第1導電回路パターンから電気的に絶縁されている第2導電回路パターンをさらに含み、
前記プリント配線基板は、前記第1ソース導電パターンから電気的に絶縁されている第2ソース導電パターンと、前記第1ゲート導電パターンから電気的に絶縁されている第2ゲート導電パターンとをさらに含み、
前記複数の第2自己消弧型半導体素子は、それぞれ、第2ソース電極と、第2ゲート電極と、第2ドレイン電極とを含み、
前記複数の第2自己消弧型半導体素子の前記第2ドレイン電極は、前記第2導電回路パターンに接合されており、
前記複数の第2自己消弧型半導体素子の前記第2ソース電極は、前記複数の第2導電接合部材によって、前記第2ソース導電パターンに接合されており、
前記複数の第2導電ゲートワイヤは、前記複数の第2自己消弧型半導体素子の前記第2ゲート電極と前記第2ゲート導電パターンとを互いに接続しており、
前記第3主面の前記平面視において、前記第2ゲート導電パターンの第2長手方向は、前記複数の第2自己消弧型半導体素子の第2配列方向である、請求項1から請求項10のいずれか一項に記載のパワー半導体モジュール。 - 前記第3主面の前記平面視において、前記第2ゲート導電パターンの第2短手方向における、前記第2ゲート導電パターンのうち前記複数の第2自己消弧型半導体素子に対応する第2ゲート導電パターン部分の第3幅は、前記第2短手方向における、前記第2ソース導電パターンのうち前記複数の第2自己消弧型半導体素子に対応する第2ソース導電パターン部分の第4幅より小さく、
前記第2ゲート導電パターンの前記第2短手方向は、前記第2ゲート導電パターンの前記第2長手方向に垂直である、請求項13に記載のパワー半導体モジュール。 - 前記第2ゲート導電パターンの前記第2長手方向における前記第2ゲート導電パターンの第3長さは、前記複数の第2自己消弧型半導体素子の前記第2配列方向における前記複数の第2自己消弧型半導体素子の第4長さ以上である、請求項11から請求項14のいずれか一項に記載のパワー半導体モジュール。
- 前記第3主面の前記平面視において、前記第2ゲート導電パターンは、前記絶縁基板の前記第2縁に沿って配置されており、
前記複数の第2自己消弧型半導体素子は、前記絶縁基板の前記第2縁に沿って配置されている、請求項11から請求項15のいずれか一項に記載のパワー半導体モジュール。 - 前記第3主面の前記平面視において、前記第2ゲート導電パターンは、前記絶縁基板の前記第1縁に沿って配置されており、
前記複数の第2自己消弧型半導体素子は、前記絶縁基板の前記第1縁に沿って配置されている、請求項13または請求項14に記載のパワー半導体モジュール。 - 第3電極端子と、
第4電極端子とをさらに備え、
前記第3電極端子は、前記第2ソース電極と前記第2ドレイン電極との間を流れる第2主電流の第2経路の、前記パワー半導体モジュールにおける第3経路端であり、
前記第4電極端子は、前記第2主電流の前記第2経路の、前記パワー半導体モジュールにおける第4経路端であり、
前記第3電極端子は、導電ワイヤ無しに、前記第2ソース導電パターンを介して、前記第2ソース電極に電気的に接続されており、
前記第4電極端子は、導電ワイヤ無しに、前記第2導電回路パターンを介して、前記第2ドレイン電極に電気的に接続されている、請求項13または請求項14に記載のパワー半導体モジュール。 - 請求項1から請求項18のいずれか一項に記載の前記パワー半導体モジュールを有し、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備える、電力変換装置。
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