JP6837057B2 - 保護膜付き半導体チップの製造方法及び半導体装置の製造方法 - Google Patents

保護膜付き半導体チップの製造方法及び半導体装置の製造方法 Download PDF

Info

Publication number
JP6837057B2
JP6837057B2 JP2018514607A JP2018514607A JP6837057B2 JP 6837057 B2 JP6837057 B2 JP 6837057B2 JP 2018514607 A JP2018514607 A JP 2018514607A JP 2018514607 A JP2018514607 A JP 2018514607A JP 6837057 B2 JP6837057 B2 JP 6837057B2
Authority
JP
Japan
Prior art keywords
protective film
forming
film
meth
sensitive adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018514607A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2017188218A1 (ja
Inventor
洋一 稲男
洋一 稲男
明徳 佐藤
明徳 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lintec Corp
Original Assignee
Lintec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corp filed Critical Lintec Corp
Publication of JPWO2017188218A1 publication Critical patent/JPWO2017188218A1/ja
Application granted granted Critical
Publication of JP6837057B2 publication Critical patent/JP6837057B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)
JP2018514607A 2016-04-28 2017-04-25 保護膜付き半導体チップの製造方法及び半導体装置の製造方法 Active JP6837057B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016092010 2016-04-28
JP2016092010 2016-04-28
PCT/JP2017/016287 WO2017188218A1 (ja) 2016-04-28 2017-04-25 保護膜付き半導体チップの製造方法及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPWO2017188218A1 JPWO2017188218A1 (ja) 2019-03-07
JP6837057B2 true JP6837057B2 (ja) 2021-03-03

Family

ID=60161569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018514607A Active JP6837057B2 (ja) 2016-04-28 2017-04-25 保護膜付き半導体チップの製造方法及び半導体装置の製造方法

Country Status (5)

Country Link
JP (1) JP6837057B2 (ko)
KR (1) KR102410096B1 (ko)
CN (1) CN109075046B (ko)
TW (1) TWI722178B (ko)
WO (1) WO2017188218A1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018200656A1 (de) 2018-01-16 2019-07-18 Disco Corporation Verfahren zum Bearbeiten eines Wafers

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144433B1 (ko) 1970-02-02 1976-11-29
JP4364508B2 (ja) * 2002-12-27 2009-11-18 リンテック株式会社 チップ裏面用保護膜形成用シートおよび保護膜付きチップの製造方法
JP4851434B2 (ja) * 2007-12-18 2012-01-11 古河電気工業株式会社 チップ保護用フィルム
EP2265682A1 (en) * 2008-03-31 2010-12-29 Henkel Corporation Multilayer uv-curable adhesive film
JP2010031183A (ja) 2008-07-30 2010-02-12 Furukawa Electric Co Ltd:The エネルギー線硬化型チップ保護用フィルム
JP2011204806A (ja) * 2010-03-24 2011-10-13 Nitto Denko Corp ウエハの加工方法
US10190017B2 (en) * 2014-03-28 2019-01-29 Lintec Corporation Protective film-forming film and method of manufacturing semiconductor chip with protective film
EP3159914B1 (en) * 2014-06-18 2019-07-24 LINTEC Corporation Dicing-sheet base film and dicing sheet
KR102330885B1 (ko) * 2014-07-04 2021-11-24 린텍 가부시키가이샤 보호막 형성용 필름

Also Published As

Publication number Publication date
CN109075046B (zh) 2023-07-18
TW201812878A (zh) 2018-04-01
WO2017188218A1 (ja) 2017-11-02
KR20190003943A (ko) 2019-01-10
TWI722178B (zh) 2021-03-21
KR102410096B1 (ko) 2022-06-17
JPWO2017188218A1 (ja) 2019-03-07
CN109075046A (zh) 2018-12-21

Similar Documents

Publication Publication Date Title
JP6847929B2 (ja) 保護膜形成用フィルムおよび保護膜形成用複合シート
JP6854811B2 (ja) 保護膜形成用フィルム、保護膜形成用複合シート、及び半導体チップの製造方法
JP6902530B2 (ja) 保護膜形成用複合シート及び保護膜付き半導体チップの製造方法、並びに半導体装置の製造方法
JP7071916B2 (ja) 保護膜付き半導体チップの製造方法及び半導体装置の製造方法
JP6956074B2 (ja) 保護膜形成用フィルム及び保護膜形成用複合シート
JP6963024B2 (ja) 保護膜形成用フィルム、保護膜形成用複合シート、及び半導体チップの製造方法
JP6971977B2 (ja) 保護膜形成用フィルム及び保護膜形成用複合シート、並びに、保護膜付き半導体チップの製造方法及び保護膜付き半導体チップの梱包方法
JP7086986B2 (ja) 保護膜形成用フィルム、保護膜形成用複合シート、及び半導体チップの製造方法
JP6979081B2 (ja) 保護膜形成用フィルム、保護膜形成用複合シート、及び半導体チップの製造方法
JP2022089876A (ja) 保護膜形成用フィルム及び保護膜形成用複合シート
JP6837057B2 (ja) 保護膜付き半導体チップの製造方法及び半導体装置の製造方法
JP6929835B2 (ja) 保護膜形成用複合シート
JP7039460B2 (ja) 保護膜形成用複合シート
JP6438173B2 (ja) 保護膜形成用フィルム及び保護膜形成用複合シート
JP6938476B2 (ja) 保護膜形成用フィルム及び保護膜形成用複合シート
JP6938477B2 (ja) 保護膜形成用複合シート
JP2024008899A (ja) 保護膜形成フィルム、保護膜形成用複合シート、キット、及び、保護膜形成フィルムの使用
JP2024008898A (ja) 保護膜形成フィルム、保護膜形成用複合シート、キット、及び、保護膜形成フィルムの使用
JP2024008460A (ja) 保護膜形成フィルム、保護膜形成用複合シート、第一キット、第二キット、保護膜形成フィルムの使用、及び、第二キットの使用
JP2022152294A (ja) 保護膜形成フィルム、保護膜形成用複合シート、及び保護膜付きチップの製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200205

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200929

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201126

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210202

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210208

R150 Certificate of patent or registration of utility model

Ref document number: 6837057

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250