JP6720775B2 - Compound semiconductor device and method of manufacturing compound semiconductor device - Google Patents

Compound semiconductor device and method of manufacturing compound semiconductor device Download PDF

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JP6720775B2
JP6720775B2 JP2016164679A JP2016164679A JP6720775B2 JP 6720775 B2 JP6720775 B2 JP 6720775B2 JP 2016164679 A JP2016164679 A JP 2016164679A JP 2016164679 A JP2016164679 A JP 2016164679A JP 6720775 B2 JP6720775 B2 JP 6720775B2
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高橋　剛
剛 高橋
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Description

本発明は、化合物半導体装置、及び化合物半導体装置の製造方法に関する。 The present invention relates to a compound semiconductor device and a method for manufacturing a compound semiconductor device.

化合物半導体装置には様々なタイプのものがある。なかでも、HEMT(High Electron Mobility Transistor)は、雑音が小さく高速動作が可能であり、この特徴を活かしてマイクロ波やミリ波の増幅器に使用されている。 There are various types of compound semiconductor devices. Among them, HEMTs (High Electron Mobility Transistors) have low noise and can operate at high speed, and by utilizing this feature, they are used in microwave and millimeter wave amplifiers.

そのHEMTにおいてはチャネル層に不純物がドープされていないため、チャネル層において不純物散乱が発生せず、これによりチャネル層における二次元電子ガスの移動度が高められる。 In the HEMT, since the channel layer is not doped with impurities, impurity scattering does not occur in the channel layer, which increases the mobility of the two-dimensional electron gas in the channel layer.

そのチャネル層と化合物半導体基板の各々の材料の組み合わせには様々なものがある。 There are various combinations of materials for the channel layer and the compound semiconductor substrate.

例えば、GaAs基板の上にチャネル層としてi型のInxGa1-xAs (x=0.1〜0.2)層を形成したGaAs HEMTは、GaAs基板とチャネル層とが疑似格子整合した状態となるため、pseudomorphic型のHEMT(p-HEMT)と呼ばれる。p-HEMTにおいては、チャネル層のInxGa1-xAsに含まれるInによって二次元電子ガスの移動度を更に高めることができる。 For example, in a GaAs HEMT in which an i-type In x Ga 1-x As (x=0.1 to 0.2) layer is formed as a channel layer on a GaAs substrate, the GaAs substrate and the channel layer are in a pseudo lattice-matched state. , Called pseudomorphic HEMT (p-HEMT). In p-HEMT, the mobility of the two-dimensional electron gas can be further increased by In contained in In x Ga 1-x As of the channel layer.

また、化合物半導体基板としてInP基板を使用したInP HEMTもある。そのInP HEMTのチャネル層としては、例えば、InP基板と格子整合したi型のIn0.53Ga0.47As層がある。なお、電子の移動度を更に高めるために、In0.53Ga0.47As層よりもInの組成が高いi型のInxGa1-xAs (0.53<x)層をInP HEMTのチャネル層に使用することもある。 There is also InP HEMT that uses an InP substrate as a compound semiconductor substrate. As the channel layer of the InP HEMT, for example, there is an i-type In 0.53 Ga 0.47 As layer lattice-matched with the InP substrate. In order to further increase electron mobility, an i-type In x Ga 1-x As (0.53<x) layer having a higher In composition than the In 0.53 Ga 0.47 As layer is used as the channel layer of InP HEMT. Sometimes.

InGaAs層は、低温にすることで二次元電子ガスのフォノン散乱が減少し、二次元電子ガスの移動度が向上することが報告されている。例えば、In0.53Ga0.47As層における二次元電子ガスの移動度は、室温（３００K）では１０，０００cm2/Vsであるのに対し、４Kでの極低温では６０，０００cm2/Vsに向上することが報告されている。 It has been reported that the low temperature of the InGaAs layer reduces the phonon scattering of the two-dimensional electron gas and improves the mobility of the two-dimensional electron gas. For example, the mobility of the two-dimensional electron gas in the In 0.53 Ga 0.47 As layer is 10,000 cm 2 /Vs at room temperature (300 K), but is improved to 60,000 cm 2 /Vs at 4 K cryogenic temperature. It has been reported.

このように低温下でチャネル層の移動度が向上することで、低温下で雑音の少ない増幅器をHEMTで実現できると考えられる。 By improving the mobility of the channel layer at low temperatures in this way, it is possible to realize an HEMT with a low-noise amplifier at low temperatures.

特開２００８−９８６７４号公報JP, 2008-98674, A 特公平５−４８１２号公報Japanese Examined Patent Publication No. 5-4812 Matsuoka et al., "Temperature Dependence of Electron Mobility in InGaAs/InAlAs Heterostructures", Japanese Journal of Applied Physics. vol. 29, no. 10, pp2017-2025, 1990Matsuoka et al., "Temperature Dependence of Electron Mobility in InGaAs/InAlAs Heterostructures", Japanese Journal of Applied Physics. vol. 29, no. 10, pp2017-2025, 1990 Akazaki et al., "Kink Effect in an InAs-Inserted-Channel InAlAs/InGaAs Inverted HEMT at Low Temperature", IEEE Electron Device Letters., vol. 17, no. 7, pp. 378-380, 1996Akazaki et al., "Kink Effect in an InAs-Inserted-Channel InAlAs/InGaAs Inverted HEMT at Low Temperature", IEEE Electron Device Letters., vol. 17, no. 7, pp. 378-380, 1996 Oliver et al., "ELECTRICAL CHARACTERIZATION AND ALLOY SCATTERING MEASUREMENTS OF LPE GaxIn1-xAs/InP FOR HIGH FREQUENCY DEVICE APPLICATIONS", Journal of Crystal Growth 54, pp. 64-68, 1981Oliver et al., "ELECTRICAL CHARACTERIZATION AND ALLOY SCATTERING MEASUREMENTS OF LPE GaxIn1-xAs/InP FOR HIGH FREQUENCY DEVICE APPLICATIONS", Journal of Crystal Growth 54, pp. 64-68, 1981

しかしながら、上記のようにチャネル層の移動度が向上しても、チャネル層以外の部分で低抵抗化が図られないと、低温下でのHEMTの優れた増幅性能を引き出すことができない。 However, even if the mobility of the channel layer is improved as described above, unless the resistance of the portion other than the channel layer is reduced, the excellent amplification performance of HEMT at low temperature cannot be obtained.

開示の技術は、上記に鑑みてなされたものであって、低抵抗化を実現することが可能な化合物半導体装置、及び化合物半導体装置の製造方法を提供することを目的とする。 The disclosed technique has been made in view of the above, and an object thereof is to provide a compound semiconductor device capable of realizing a low resistance and a method for manufacturing the compound semiconductor device.

以下の開示の一観点によれば、基板と、前記基板の上方に形成されたチャネル層と、前記チャネル層の上に形成された電子供給層と、前記電子供給層の上に互いに間隔をおいて形成された第１のキャップ層及び第２のキャップ層と、前記第１のキャップ層の上に形成されたソース電極と、前記第２のキャップ層の上に形成されたドレイン電極と、前記第１のキャップ層と前記第２のキャップ層の間における前記電子供給層の上に形成されたゲート電極とを備え、前記第１のキャップ層と前記第２のキャップ層の各々が、i型の第１の化合物半導体層と、前記第１の化合物半導体層よりもバンドギャップが広いn型の第２の化合物半導体層とが交互に複数積層された積層膜である化合物半導体装置が提供される。 According to one aspect of the following disclosure, a substrate, a channel layer formed above the substrate, an electron supply layer formed on the channel layer, and an electron supply layer spaced apart from each other on the electron supply layer. A first cap layer and a second cap layer formed on the first cap layer, a source electrode formed on the first cap layer, a drain electrode formed on the second cap layer, and A gate electrode formed on the electron supply layer between the first cap layer and the second cap layer, wherein each of the first cap layer and the second cap layer is i-type There is provided a compound semiconductor device, which is a laminated film in which a plurality of the first compound semiconductor layers and an n-type second compound semiconductor layer having a wider band gap than the first compound semiconductor layer are alternately laminated. ..

以下の開示によれば、n型の第２の化合物半導体層によって第１の化合物半導体層に電子が誘起される。その電子は、不純物を含まないi型の第１の化合物半導体層を基板横方向に走行するため、不純物散乱によって第１のキャップ層や第２のキャップ層の抵抗が上昇せず、化合物半導体装置の抵抗を低い状態に維持できる。 According to the following disclosure, electrons are induced in the first compound semiconductor layer by the n-type second compound semiconductor layer. Since the electrons travel in the lateral direction of the substrate in the i-type first compound semiconductor layer containing no impurities, the resistance of the first cap layer and the second cap layer does not increase due to impurity scattering, and the compound semiconductor device The resistance of can be kept low.

図１は、検討に使用した化合物半導体装置の断面図である。FIG. 1 is a cross-sectional view of the compound semiconductor device used for the study. 図２は、図１の化合物半導体装置のエネルギバンド構造を示す図である。FIG. 2 is a diagram showing an energy band structure of the compound semiconductor device of FIG. 図３は、図１の化合物半導体装置に生じる抵抗を模式的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing the resistance generated in the compound semiconductor device of FIG. 図４は、InGaAsにおけるホールの移動度の温度依存性を示すグラフである。FIG. 4 is a graph showing the temperature dependence of hole mobility in InGaAs. 図５（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その１）である。5A and 5B are cross-sectional views (No. 1) of the compound semiconductor device according to the first embodiment which is being manufactured. 図６（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その２）である。6A and 6B are cross-sectional views (No. 2) during the manufacturing of the compound semiconductor device according to the first embodiment. 図７（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その３）である。7A and 7B are cross-sectional views (3) of the compound semiconductor device according to the first embodiment in the process of being manufactured. 図８（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その４）である。FIGS. 8A and 8B are cross-sectional views (No. 4) in the process of manufacturing the compound semiconductor device according to the first embodiment. 図９（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その５）である。9A and 9B are cross-sectional views (No. 5) in the process of manufacturing the compound semiconductor device according to the first embodiment. 図１０（ａ）、（ｂ）は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その６）である。10A and 10B are sectional views (No. 6) in the process of manufacturing the compound semiconductor device according to the first embodiment. 図１１は、第１実施形態に係る化合物半導体装置の製造途中の断面図（その７）である。FIG. 11 is a sectional view (No. 7) of the compound semiconductor device according to the first embodiment which is being manufactured. 図１２は、第１実施形態に係る第１のキャップ層のエネルギバンド構造を示す図である。FIG. 12 is a diagram showing an energy band structure of the first cap layer according to the first embodiment. 図１３は、図１１のII-II線に沿った第１実施形態に係る化合物半導体装置の全体のバンド構造を示す図である。FIG. 13 is a diagram showing the entire band structure of the compound semiconductor device according to the first embodiment taken along the line II-II of FIG. 図１４は、第１実施形態に係る第１のキャップ層の抵抗の試算結果を示す図である。FIG. 14 is a diagram showing a trial calculation result of the resistance of the first cap layer according to the first embodiment. 図１５（ａ）、（ｂ）は、第２実施形態に係る化合物半導体装置の製造途中の断面図（その１）である。15A and 15B are cross-sectional views (No. 1) in the process of manufacturing the compound semiconductor device according to the second embodiment. 図１６（ａ）、（ｂ）は、第２実施形態に係る化合物半導体装置の製造途中の断面図（その２）である。16A and 16B are cross-sectional views (No. 2) of the compound semiconductor device according to the second embodiment in the process of being manufactured. 図１７は、第２実施形態に係る化合物半導体装置の製造途中の断面図（その３）である。FIG. 17 is a cross-sectional view (3) of the compound semiconductor device according to the second embodiment which is being manufactured. 図１８（ａ）は、第１実施形態に係る第１のキャップ層のエネルギバンド構造を示す図であり、図１８（ｂ）は、第２実施形態に係る第１のキャップ層のエネルギバンド構造を示す図である。FIG. 18A is a diagram showing the energy band structure of the first cap layer according to the first embodiment, and FIG. 18B is the energy band structure of the first cap layer according to the second embodiment. FIG. 図１９（ａ）、（ｂ）は、第３実施形態に係る化合物半導体装置の製造途中の断面図（その１）である。FIGS. 19A and 19B are cross-sectional views (part 1) of the compound semiconductor device according to the third embodiment during manufacturing. 図２０は、第３実施形態に係る化合物半導体装置の製造途中の断面図（その２）である。FIG. 20 is a cross-sectional view (2) of the compound semiconductor device according to the third embodiment in the process of being manufactured. 図２１は、図２０のIII-III線に沿った第３実施形態に係る化合物半導体装置の全体のバンド構造を示す図である。21 is a diagram showing the entire band structure of the compound semiconductor device according to the third embodiment taken along the line III-III of FIG. 図２２は、化合物半導体装置としてInP HEMPを製造する場合における各層の材料の他の例について示す図である。FIG. 22 is a diagram showing another example of the material of each layer in the case of manufacturing InP HEMP as a compound semiconductor device. 図２３は、化合物半導体装置としてGaN HEMTを製造する場合の各層の材料の例について示す図である。FIG. 23 is a diagram showing an example of the material of each layer in the case of manufacturing a GaN HEMT as a compound semiconductor device. 図２４は、化合物半導体装置としてGaAs HEMTを製造する場合の各層の材料の例について示す図である。FIG. 24 is a diagram showing an example of the material of each layer when a GaAs HEMT is manufactured as a compound semiconductor device.

本実施形態の説明に先立ち、本願発明者が検討した事項について説明する。 Prior to the description of the present embodiment, matters examined by the inventor of the present application will be described.

図１は、その検討に使用した化合物半導体装置の断面図である。 FIG. 1 is a cross-sectional view of the compound semiconductor device used for the study.

この化合物半導体装置１は、前述のInP HEMTであって、InP基板２の上にバッファ層３、チャネル層４、及び電子供給層５がこの順に形成される。 The compound semiconductor device 1 is the above-described InP HEMT, and the buffer layer 3, the channel layer 4, and the electron supply layer 5 are formed in this order on the InP substrate 2.

このうち、バッファ層３は、InP基板２の欠陥がチャネル層４に伝わらないようにする役割を担い、この例ではi型のInAlAs層をバッファ層３として形成する。 Of these, the buffer layer 3 plays a role of preventing defects of the InP substrate 2 from being transmitted to the channel layer 4. In this example, an i-type InAlAs layer is formed as the buffer layer 3.

また、チャネル層４は電子が走行する層であり、例えばi型のInGaAs層をチャネル層４として形成する。そのチャネル層４には不純物がドープされないため、チャネル層４を走行する電子の移動度が不純物散乱によって低下するのを防止できる。 The channel layer 4 is a layer through which electrons travel, and an i-type InGaAs layer is formed as the channel layer 4, for example. Since the channel layer 4 is not doped with impurities, it is possible to prevent the mobility of electrons traveling in the channel layer 4 from decreasing due to impurity scattering.

そして、電子供給層５は、チャネル層４に電子を供給する化合物半導体層である。この例では、いずれもi型のInAlAsを材料とするスペーサ層５ａとバリア層５ｃとをこの順に積層すると共に、これらの界面にn型不純物であるシリコンのドープ層５ｂを形成することにより電子供給層５を形成する。 The electron supply layer 5 is a compound semiconductor layer that supplies electrons to the channel layer 4. In this example, a spacer layer 5a and a barrier layer 5c each made of i-type InAlAs are laminated in this order, and a doped layer 5b of silicon, which is an n-type impurity, is formed at the interface between them to supply electrons. Form layer 5.

この構造によれば、ドープ層５ｂにおけるn型不純物によってチャネル層４に二次元電子ガスを誘起することができる。 According to this structure, a two-dimensional electron gas can be induced in the channel layer 4 by the n-type impurity in the doped layer 5b.

更に、ドープ層５ｂのn型不純物がチャネル層４に拡散するのがスペーサ層５ａによって防止されるため、そのn型不純物に起因した不純物散乱がチャネル層４で発生することがなく、チャネル層４における電子の移動度を高い値に維持できる。 Further, the n-type impurities of the doped layer 5b are prevented from diffusing into the channel layer 4 by the spacer layer 5a, so that the impurity scattering due to the n-type impurities does not occur in the channel layer 4 and the channel layer 4 is prevented. The electron mobility at can be maintained at a high value.

しかも、バリア層５ｃによって後述のゲート電極との間でショットキー障壁が形成され、これによりトランジスタの増幅作用を実現できる。 In addition, the barrier layer 5c forms a Schottky barrier with the gate electrode described later, and thus the amplifying action of the transistor can be realized.

なお、上記の電子供給層５は、スペーサ層５ａの成長を停止した後にその表面をシリコン等のn型不純物を含むガスに曝してドープ層５ｂを形成し、その後にバリア層５ｃを成長させることで形成され得る。このようなドープ層５ｂの形成方法はプレーナドープとも呼ばれる。 In the electron supply layer 5, the growth of the spacer layer 5a is stopped, the surface thereof is exposed to a gas containing an n-type impurity such as silicon to form the doped layer 5b, and then the barrier layer 5c is grown. Can be formed of. Such a method of forming the doped layer 5b is also called planar doping.

その電子供給層５の上には第１のキャップ層６と第２のキャップ層７が間隔をおいて形成されており、更に各キャップ層６、７の上にはソース電極８とドレイン電極９が形成される。 A first cap layer 6 and a second cap layer 7 are formed on the electron supply layer 5 at intervals, and a source electrode 8 and a drain electrode 9 are further formed on the cap layers 6 and 7. Is formed.

第１のキャップ層６は、電子供給層５とソース電極８との間の抵抗を低減するためのn型の化合物半導体層である。第１のキャップ層６におけるn型不純物の濃度が高いほど電子供給層５とソース電極８との間の抵抗が低減でき、この例ではn型不純物としてシリコンを１×１０19cm-3程度の高濃度にドープしたInGaAs層をその第１のキャップ層６として形成する。 The first cap layer 6 is an n-type compound semiconductor layer for reducing the resistance between the electron supply layer 5 and the source electrode 8. The higher the concentration of the n-type impurity in the first cap layer 6, the lower the resistance between the electron supply layer 5 and the source electrode 8. In this example, silicon is used as the n-type impurity at about 1×10 19 cm −3 . A heavily doped InGaAs layer is formed as the first cap layer 6.

なお、第２のキャップ層７は、第１のキャップ層６と同じ工程で形成され、第１のキャップ層６と同様にシリコンが高濃度にドープされたInGaAs層である。 The second cap layer 7 is an InGaAs layer which is formed in the same step as the first cap layer 6 and is heavily doped with silicon like the first cap layer 6.

そして、各キャップ層６、７の間の電子供給層５の上にはゲート電極１０が形成される。 Then, the gate electrode 10 is formed on the electron supply layer 5 between the cap layers 6 and 7.

図２は、この化合物半導体装置１のエネルギバンド構造を示す図である。 FIG. 2 is a diagram showing an energy band structure of the compound semiconductor device 1.

図２に示されるように、第１のキャップ層６にn型不純物としてシリコンを高濃度にドープしたことで、第１のキャップ層６のキャリア濃度が高くなり、第１のキャップ層６に多量の電子eを発生させることができる。 As shown in FIG. 2, by doping the first cap layer 6 with silicon as an n-type impurity at a high concentration, the carrier concentration of the first cap layer 6 is increased, and a large amount of the first cap layer 6 is contained. Can generate electrons e.

また、ドープ層５ｂにおけるn型不純物により、チャネル層４には二次元電子ガス１１が誘起される。 Also, the two-dimensional electron gas 11 is induced in the channel layer 4 by the n-type impurities in the doped layer 5b.

このような化合物半導体装置１によれば、前述のようにチャネル層４に不純物がドープされていないため、不純物散乱によってチャネル層４における電子の移動度が低下せず、ドレイン電流の低雑音化が図られるはずである。 According to such a compound semiconductor device 1, since the channel layer 4 is not doped with impurities as described above, the mobility of electrons in the channel layer 4 does not decrease due to impurity scattering, and the noise of the drain current can be reduced. It should be possible.

しかし、前述のAkazaki et al.にはHEMTのソース抵抗が低温時に上昇することが報告されている。その報告によれば、温度が３００Kから７７Kに低下するとソース抵抗が１．０２Ωmmから０．６８Ωmmに低下するものの、温度が更に低下して７７Kから４．２Kになると、ソース抵抗が０．６８Ωmmから０．８２Ωmmに上昇する。 However, Akazaki et al. mentioned above reported that the source resistance of HEMT increased at low temperature. According to the report, when the temperature drops from 300K to 77K, the source resistance drops from 1.02Ωmm to 0.68Ωmm, but when the temperature drops further from 77K to 4.2K, the source resistance drops from 0.68Ωmm. It rises to 0.82Ωmm.

その理由は以下のように考えられる。 The reason is considered as follows.

図３は、化合物半導体装置１に生じる抵抗を模式的に示す断面図である。 FIG. 3 is a cross-sectional view schematically showing the resistance generated in the compound semiconductor device 1.

図３に示されるように、この化合物半導体装置１には第１のR1〜第４の抵抗R4があり、ソース抵抗はこれら第１〜第４の抵抗R1〜R4を直列に接続したものと近似できる。 As shown in FIG. 3, the compound semiconductor device 1 has first to fourth resistances R1 to R4, and the source resistance is similar to that of the first to fourth resistances R1 to R4 connected in series. it can.

第１の抵抗R1は、第１のキャップ層６とソース電極８との間のコンタクト抵抗である。また、第２の抵抗R2は、基板横方向に沿った第１のキャップ層６の抵抗である。 The first resistance R1 is a contact resistance between the first cap layer 6 and the source electrode 8. The second resistance R2 is the resistance of the first cap layer 6 along the lateral direction of the substrate.

そして、第３の抵抗R3は、電子供給層５により形成される障壁を電子が乗り越えるときの抵抗である。更に、第４の抵抗R4は、基板横方向に沿ったチャネル層４の抵抗である。 The third resistance R3 is a resistance when the electrons get over the barrier formed by the electron supply layer 5. Furthermore, the fourth resistance R4 is the resistance of the channel layer 4 along the lateral direction of the substrate.

本願発明者は、第１〜第４の抵抗R1〜R4のうち、第２の抵抗R2が極低温時に増加したことにより、極低温下でソース抵抗が増加したと考える。 The inventor of the present application considers that the source resistance increases at the extremely low temperature because the second resistance R2 among the first to fourth resistances R1 to R4 increases at the extremely low temperature.

図４は、その理由を説明するための図であって、InGaAsにおけるホールの移動度の温度依存性を示すグラフである。 FIG. 4 is a graph for explaining the reason, and is a graph showing the temperature dependence of the hole mobility in InGaAs.

図４に示すように、移動度を低下させる要因には、フォノン散乱、合金散乱、及び不純物散乱がある。このうち、フォノン散乱と合金散乱は温度の低下と共に減少していくのに対し、不純物散乱は極低温において顕著となる。 As shown in FIG. 4, factors that reduce the mobility include phonon scattering, alloy scattering, and impurity scattering. Of these, phonon scattering and alloy scattering decrease as the temperature decreases, whereas impurity scattering becomes significant at extremely low temperatures.

その結果、InGaAsの温度を低下させていくと、移動度の増加は７７K程度の温度で飽和し、これよりも低い極低温下では移動度が逆に低下している。 As a result, when the temperature of InGaAs is lowered, the increase in mobility saturates at a temperature of about 77 K, and the mobility decreases conversely at cryogenic temperatures lower than this.

これにより、極低温下における移動度の低下は、化合物半導体に含まれる不純物が原因であると推測できる。前述の第１〜第４の抵抗R1〜R4のうち、不純物がドープされた化合物半導体層に発生するのは、n型不純物がドープされた第１のキャップ層６に発生する第２の抵抗R2である。 From this, it can be inferred that the decrease in mobility at extremely low temperatures is caused by the impurities contained in the compound semiconductor. Of the above-described first to fourth resistors R1 to R4, what occurs in the compound semiconductor layer doped with impurities is the second resistor R2 generated in the first cap layer 6 doped with n-type impurities. Is.

よって、Akazaki et al.で報告された低温下におけるソース抵抗の増加は、この第２の抵抗R2が低温下で増加したためと考えられる。 Therefore, it is considered that the increase of the source resistance at low temperature reported by Akazaki et al. is due to the increase of the second resistance R2 at low temperature.

特に、第１のキャップ層６は、前述のように低抵抗化のためにn型不純物が１×１０19cm-3程度の高濃度にドープされているため、極低温化における不純物散乱が顕著に発生し、低温下で第２の抵抗R2が大きくなると考えられる。 In particular, since the first cap layer 6 is doped with n-type impurities at a high concentration of about 1×10 19 cm −3 for reducing the resistance as described above, the impurity scattering at extremely low temperatures is remarkable. It is considered that the second resistance R2 increases at low temperature.

このような知見に鑑み、本実施形態では以下のようにしてキャップ層の抵抗を低減して、低温下におけるHEMTのソース抵抗を低い状態に維持する。 In view of such knowledge, in the present embodiment, the resistance of the cap layer is reduced as described below to maintain the source resistance of the HEMT at a low temperature at a low state.

（第１実施形態）
本実施形態に係る化合物半導体装置について、その製造工程を追いながら説明する。 (First embodiment)
The compound semiconductor device according to this embodiment will be described by following the manufacturing process thereof.

図５〜図１１は、本実施形態に係る化合物半導体装置の製造途中の断面図である。 5 to 11 are cross-sectional views of the compound semiconductor device according to the present embodiment in the process of being manufactured.

本実施形態では以下のようにして化合物半導体装置としてInP HEMTを製造する。 In this embodiment, the InP HEMT is manufactured as a compound semiconductor device as follows.

まず、図５（ａ）に示すように、基板２０としてInP基板等の化合物半導体基板を用意する。 First, as shown in FIG. 5A, a compound semiconductor substrate such as an InP substrate is prepared as the substrate 20.

そして、不図示のチャンバ内に基板２０を入れ、その基板２０の上にMOCVD(Metal Organic Chemical Vapor Deposition)法でバッファ層２１としてi型のInAlAs層を３００nm程度の厚さに形成する。 Then, the substrate 20 is placed in a chamber (not shown), and an i-type InAlAs layer is formed as the buffer layer 21 on the substrate 20 by MOCVD (Metal Organic Chemical Vapor Deposition) to a thickness of about 300 nm.

そのInAlAs層を形成するための成長ガスは特に限定されない。例えば、Inの原料ガスとしてはトリメチルインジウム((CH3)3In)やトリエチルインジウム((C2H5)3In)があり、Alの原料ガスとしてはトリメチルアルミニウム((CH3)3Al)やトリエチルアルミニウム((C2H5)3Al)がある。そして、Asの原料ガスとしては例えばアルシン(AsH3)がある。 The growth gas for forming the InAlAs layer is not particularly limited. For example, there are trimethylindium ((CH 3 ) 3 In) and triethylindium ((C 2 H 5 ) 3 In) as the source gas of In, and trimethylaluminum ((CH 3 ) 3 Al) as the source gas of Al. And triethyl aluminum ((C 2 H 5 ) 3 Al). The source gas of As includes, for example, arsine (AsH 3 ).

更に、InAlAs層の組成比も特に限定されないが、本実施形態では基板２０として使用するInP基板と格子整合するIn0.52Al0.48As層をバッファ層２１として形成する。 Further, the composition ratio of the InAlAs layer is not particularly limited, but in the present embodiment, an In 0.52 Al 0.48 As layer lattice-matched with the InP substrate used as the substrate 20 is formed as the buffer layer 21.

上記したInAlAs層の組成比や原料ガスについては、後の工程で形成する各InAlAs層においても同様である。 The composition ratio of the InAlAs layer and the source gas described above are the same for each InAlAs layer formed in a later step.

更に、上記のチャンバから化合物半導体装置２０を取り出さずに、そのチャンバ内においてバッファ層２１の上にMOCVD法でi型のInGaAs層を１５nm程度の厚さに形成し、そのInGaAs層をチャネル層２２とする。 Further, without taking out the compound semiconductor device 20 from the above chamber, an i-type InGaAs layer having a thickness of about 15 nm is formed on the buffer layer 21 by MOCVD in the chamber, and the InGaAs layer is formed into the channel layer 22. And

InGaAs層の成長ガスも特に限定されず、Inの原料ガスとしてはトリメチルインジウムやトリエチルインジウムを使用し、Gaの原料ガスとしてはトリメチルガリウム((CH3)3Ga)やトリエチルガリウム((C2H5)3Ga)を使用し得る。そして、Asの原料ガスとしてはアルシンを使用し得る。 The growth gas for the InGaAs layer is not particularly limited, and trimethylindium or triethylindium is used as the source gas for In, and trimethylgallium ((CH 3 ) 3 Ga) or triethylgallium ((C 2 H 5 ) 3 Ga) can be used. And, arsine can be used as a source gas of As.

また、InGaAs層の組成比は、基板２０の材料であるInPと格子整合するIn0.53Ga0.48Asとする。 The composition ratio of the InGaAs layer is In 0.53 Ga 0.48 As which is lattice-matched with InP which is the material of the substrate 20.

そのようなInGaAs層の組成比や原料ガスについては、後の工程で形成する各InGaAs層においても同様である。 The composition ratios and source gases of such InGaAs layers are the same for each InGaAs layer formed in a later step.

次に、図５（ｂ）に示す工程について説明する。 Next, the process shown in FIG. 5B will be described.

まず、上記のチャンバを引き続き使用し、バッファ層２１を形成したのと同じ成長ガスをそのチャンバに供給しながらMOCVD法でチャネル層２２の上にi型のInAlAs層を３nm程度の厚さに形成し、そのInAlAs層をスペーサ層２３ａとする。 First, while continuing to use the above chamber, the i-type InAlAs layer having a thickness of about 3 nm is formed on the channel layer 22 by MOCVD while supplying the same growth gas as that used for forming the buffer layer 21 to the chamber. The InAlAs layer is used as the spacer layer 23a.

そして、成長ガスの供給を一旦停止し、チャンバ内にシリコンの原料ガスであるシラン(SiH4)又はジシラン(Si2H6)を供給する。これにより、スペーサ層２３ａの表層にn型不純物であるシリコンが５×１０12cm-2程度の濃度でドープされたn型のドープ層２３ｂがプレーナドープにより形成されることになる。 Then, the supply of the growth gas is temporarily stopped, and silane (SiH 4 ) or disilane (Si 2 H 6 ) which is a raw material gas of silicon is supplied into the chamber. As a result, an n-type doped layer 23b in which silicon, which is an n-type impurity, is doped at a concentration of about 5×10 12 cm -2 on the surface layer of the spacer layer 23a is formed by planar doping.

その後、InAlAs層用の成長ガスを再び上記のチャンバに供給することにより、ドープ層２３ｂの上にバリア層２３ｃとしてi型のInAlAs層を１０nm程度の厚さにMOCVD法で形成する。 Then, the growth gas for the InAlAs layer is supplied again to the above chamber to form the i-type InAlAs layer as the barrier layer 23c on the doped layer 23b to a thickness of about 10 nm by the MOCVD method.

以上により、スペーサ層２３ａ、n型のドープ層２３ｂ、及びバリア層２３ｃがこの順に積層された電子供給層２３が形成される。 As described above, the electron supply layer 23 in which the spacer layer 23a, the n-type doped layer 23b, and the barrier layer 23c are stacked in this order is formed.

このような層構造の電子供給層２３によれば、図１の例と同様に、ドープ層２３ｂのn型不純物がチャネル層２２に拡散するのをスペーサ層２３ａで防止でき、かつ後述のゲート電極とバリア層２３ｃとの間にショットキー障壁を形成できる。 According to the electron supply layer 23 having such a layer structure, the spacer layer 23a can prevent the n-type impurities of the doped layer 23b from diffusing into the channel layer 22 as in the example of FIG. A Schottky barrier can be formed between the barrier layer 23c and the barrier layer 23c.

但し、これらの利点が不要な場合には、電子供給層２３としてn型の単層のInAlAs層を形成してもよい。 However, when these advantages are unnecessary, an n-type single-layer InAlAs layer may be formed as the electron supply layer 23.

続いて、図６（ａ）に示すように、上記のチャンバ内においてMOCVD法により電子供給層２３の上にi型の第１の化合物半導体層２４とn型の第２の化合物半導体層２５とをこの順に積層し、各化合物半導体層２４、２５の積層膜２６を形成する。 Subsequently, as shown in FIG. 6A, an i-type first compound semiconductor layer 24 and an n-type second compound semiconductor layer 25 are formed on the electron supply layer 23 by MOCVD in the above chamber. Are laminated in this order to form a laminated film 26 of the compound semiconductor layers 24 and 25.

ここで、本実施形態では、第１の化合物半導体層２４よりも第２の化合物半導体層２５の方がバンドギャップが広くなるように各化合物半導体層２４、２５の材料を選択する。 Here, in the present embodiment, the material of each of the compound semiconductor layers 24 and 25 is selected so that the band gap of the second compound semiconductor layer 25 is wider than that of the first compound semiconductor layer 24.

このような材料の組み合わせはいくつかあるが、以下では第１の化合物半導体層２４としてInGaAs層を形成する。また、第２の化合物半導体層２５は、n型不純物としてシリコンが１×１０19cm-2程度の濃度で均一にドープされたInAlAs層である。 Although there are several combinations of such materials, an InGaAs layer is formed as the first compound semiconductor layer 24 below. The second compound semiconductor layer 25 is an InAlAs layer uniformly doped with silicon as an n-type impurity at a concentration of about 1×10 19 cm -2 .

なお、InAlAs層にシリコンをドープするには前述のInAlAs用の成長ガスにシランやジシラン等のシラン系のガスを添加すればよく、更にそのシラン系のガスの流量を調節することでInAlAs層におけるシリコンのドープ量を制御し得る。 In order to dope the InAlAs layer with silicon, a silane-based gas such as silane or disilane may be added to the above-described growth gas for InAlAs, and by further adjusting the flow rate of the silane-based gas in the InAlAs layer. The doping amount of silicon can be controlled.

各化合物半導体層２４、２５のバンドギャップはそれらの組成比に依存する。例えば、第１の化合物半導体層２４としてi型のIn0.53Ga0.48As層を形成する場合は、そのIn0.53Ga0.48As層のバンドギャップは０．７４eVである。また、第２の化合物半導体層２５としてn型のIn0.52Al0.48As層を形成する場合は、そのIn0.52Al0.48As層のバンドギャップは１．４６eVである。 The band gap of each compound semiconductor layer 24, 25 depends on their composition ratio. For example, when an i-type In 0.53 Ga 0.48 As layer is formed as the first compound semiconductor layer 24, the band gap of the In 0.53 Ga 0.48 As layer is 0.74 eV. When an n-type In 0.52 Al 0.48 As layer is formed as the second compound semiconductor layer 25, the band gap of the In 0.52 Al 0.48 As layer is 1.46 eV.

更に、各化合物半導体層２４、２５の膜厚も特に限定されないが、本実施形態ではこれらの化合物半導体層２４、２５の膜厚を５nm程度とする。このように５nm程度の薄い化合物半導体層２４、２５が積層された構造は超格子構造とも呼ばれる。 Further, the film thickness of each compound semiconductor layer 24, 25 is not particularly limited, but in the present embodiment, the film thickness of these compound semiconductor layers 24, 25 is about 5 nm. The structure in which the compound semiconductor layers 24 and 25 having a thin thickness of about 5 nm are stacked is also called a superlattice structure.

また、各化合物半導体層２４、２５の積層数も特に限定されない。この例では、第１の化合物半導体層２４の層数は６層とし、第２の化合物半導体層２５の層数は５層とする。そして、積層膜２６の最上層と最下層には第１の化合物半導体層２４を設ける。 Further, the number of stacked compound semiconductor layers 24 and 25 is not particularly limited. In this example, the number of first compound semiconductor layers 24 is six, and the number of second compound semiconductor layers 25 is five. Then, the first compound semiconductor layer 24 is provided on the uppermost layer and the lowermost layer of the laminated film 26.

なお、第１の化合物半導体層２４のIn0.53Ga0.48As層と第２の化合物半導体層２５のIn0.52Al0.48As層とは格子整合が図られているが、バンドギャップに差があれば格子整合が図られていなくてもよい。 The In 0.53 Ga 0.48 As layer of the first compound semiconductor layer 24 and the In 0.52 Al 0.48 As layer of the second compound semiconductor layer 25 are lattice-matched with each other. It does not have to be matched.

次に、図６（ｂ）に示すように、積層膜２６の上にフォトレジストを塗布し、それを露光、現像することにより第１のレジスト層３０を形成する。 Next, as shown in FIG. 6B, a photoresist is applied on the laminated film 26, and the photoresist is exposed and developed to form a first resist layer 30.

そして、図７（ａ）に示すように、第１のレジスト層３０をマスクにしながら、チャネル層２２、電子供給層２３、及び積層膜２６をウェットエッチングすることにより、これらの各層に素子分離溝２９を形成する。 Then, as shown in FIG. 7A, the channel layer 22, the electron supply layer 23, and the laminated film 26 are wet-etched by using the first resist layer 30 as a mask to form device isolation trenches in each of these layers. 29 is formed.

このウェットエッチングで使用するエッチング液は特に限定されないが、例えばリン酸と過酸化水素水との混合溶液をエッチング液として使用し得る。 The etching solution used in this wet etching is not particularly limited, but for example, a mixed solution of phosphoric acid and hydrogen peroxide solution can be used as the etching solution.

この後に、第１のレジスト層３０は除去される。 After this, the first resist layer 30 is removed.

続いて、図７（ｂ）に示すように、基板２０の上側全面にフォトレジストを塗布し、それを露光、現像することにより、第１の開口３１ａと第２の開口３１ｂとを備えた第２のレジスト層３１を形成する。 Subsequently, as shown in FIG. 7B, a photoresist is applied to the entire upper surface of the substrate 20, and the photoresist is exposed and developed to provide a first opening 31a and a second opening 31b. A second resist layer 31 is formed.

次に、図８（ａ）に示すように、第２のレジスト層３１の上と各開口３１ａ、３１ｂ内に蒸着法で金属積層膜３３を形成する。その金属積層膜３３は、例えば、下から順に厚さが約１０nmのチタン層、厚さが約３０nmのプラチナ層、及び厚さが約３００nmの金層を積層した積層膜である。 Next, as shown in FIG. 8A, a metal laminated film 33 is formed on the second resist layer 31 and in each of the openings 31a and 31b by a vapor deposition method. The metal laminated film 33 is, for example, a laminated film in which a titanium layer having a thickness of about 10 nm, a platinum layer having a thickness of about 30 nm, and a gold layer having a thickness of about 300 nm are laminated in this order from the bottom.

次いで、図８（ｂ）に示すように、有機溶剤で第２のレジスト層３１を除去することにより、第１の開口３１ａと第２の開口３１ｂの各々に形成されていた金属積層膜３３をそれぞれソース電極３３ａ及びドレイン電極３３ｂとして積層膜２６の上に残す。このような金属積層膜３３のパターニング方法はリフトオフ法とも呼ばれる。 Then, as shown in FIG. 8B, the second resist layer 31 is removed with an organic solvent to remove the metal laminated film 33 formed in each of the first opening 31a and the second opening 31b. The source electrode 33a and the drain electrode 33b are left on the laminated film 26, respectively. Such a patterning method of the metal laminated film 33 is also called a lift-off method.

続いて、図９（ａ）に示すように、基板２０の上側全面に電子線レジストを塗布し、それを電子線で露光した後に現像することにより、ソース電極３３ａとドレイン電極３３ｂとの間に第３の開口３５ａを備えた第３のレジスト層３５を形成する。 Subsequently, as shown in FIG. 9A, an electron beam resist is applied to the entire upper surface of the substrate 20, exposed by an electron beam, and then developed, so that a space between the source electrode 33a and the drain electrode 33b is formed. A third resist layer 35 having a third opening 35a is formed.

そして、図９（ｂ）に示すように、第３の開口３５ａを通じて積層膜２６をウェットエッチングすることにより積層膜２６をパターニングし、第３の開口３５ａの下の積層膜２６に溝２６ｘを形成する。 Then, as shown in FIG. 9B, the laminated film 26 is patterned by wet-etching the laminated film 26 through the third opening 35a, and a groove 26x is formed in the laminated film 26 below the third opening 35a. To do.

このパターニングにより、ソース電極３３ａの下の積層膜２６が第１のキャップ層２６ａとして残されると共に、ドレイン電極３３ｂの下の積層膜２６が第２のキャップ層２６ｂとして残され、各キャップ層２６ａ、２６ｂが溝２６ｘで分離される。 By this patterning, the laminated film 26 under the source electrode 33a is left as the first cap layer 26a, and the laminated film 26 under the drain electrode 33b is left as the second cap layer 26b. 26b are separated by a groove 26x.

その後に、第３のレジスト層３５は除去される。 After that, the third resist layer 35 is removed.

次に、図１０（ａ）に示す工程について説明する。 Next, the step shown in FIG. 10A will be described.

まず、基板２０の上側全面に電子線用の第４〜第６のレジスト層４１〜４３をこの順に形成する。 First, the fourth to sixth resist layers 41 to 43 for electron beams are formed in this order on the entire upper surface of the substrate 20.

そして、第６のレジスト層４３を電子線で露光した後にそれを現像することにより、第６のレジスト層４３に第４の開口４３ａを形成する。更に、その第４の開口４３ａを通じて第５のレジスト層４２をウェットエッチングして、第４の開口４３ａよりも側面が後退した第５の開口４２ａを第５のレジスト層４２に形成する。 Then, by exposing the sixth resist layer 43 with an electron beam and then developing it, a fourth opening 43a is formed in the sixth resist layer 43. Further, the fifth resist layer 42 is wet-etched through the fourth opening 43a to form a fifth opening 42a in which the side surface is recessed from the fourth opening 43a in the fifth resist layer 42.

その後に、第５の開口４２ａから露出した第４のレジスト層４１を電子線で露光した後にそれを現像し、溝２６ｘ内の第４のレジスト層４１にホール４１ａを形成する。 After that, the fourth resist layer 41 exposed from the fifth opening 42a is exposed with an electron beam and then developed to form a hole 41a in the fourth resist layer 41 in the groove 26x.

次いで、図１０（ｂ）に示すように、第６のレジスト層４３の上に蒸着法により金属積層膜４５を形成する。その金属積層膜４５は、下から順に厚さが１０nmのチタン層、厚さが３０nmのプラチナ層、及び厚さが３００nmの金層を積層した積層膜である。 Next, as shown in FIG. 10B, a metal laminated film 45 is formed on the sixth resist layer 43 by a vapor deposition method. The metal laminated film 45 is a laminated film in which a titanium layer having a thickness of 10 nm, a platinum layer having a thickness of 30 nm, and a gold layer having a thickness of 300 nm are laminated in this order from the bottom.

その金属積層膜４５はホール４１ａと各開口４２ａ、４３ａ内にも形成され、これにより電子供給層２３の上にT字型のゲート電極４５ａが形成される。 The metal laminated film 45 is also formed in the hole 41a and the openings 42a and 43a, whereby a T-shaped gate electrode 45a is formed on the electron supply layer 23.

その後に、図１１に示すように、有機溶剤で各レジスト層４１〜４３を溶解して除去する。 Then, as shown in FIG. 11, the resist layers 41 to 43 are dissolved and removed with an organic solvent.

以上により、本実施形態に係る化合物半導体装置５０の基本構造が完成する。 As described above, the basic structure of the compound semiconductor device 50 according to this embodiment is completed.

上記した化合物半導体装置５０によれば、互いにバンドギャップが異なる第１の化合物半導体層２４と第２の化合物半導体層２５とを積層することで超格子構造の第１のキャップ層２６ａを形成する。 According to the compound semiconductor device 50 described above, the first compound semiconductor layer 24 and the second compound semiconductor layer 25 having different band gaps are stacked to form the first cap layer 26a having a superlattice structure.

図１２は、その第１のキャップ層２６ａのエネルギバンド構造を示す図である。 FIG. 12 is a diagram showing an energy band structure of the first cap layer 26a.

図１２に示すように、第２の化合物半導体層２５にはn型不純物２５ｘとしてシリコンが均一にドープされており、そのn型不純物２５ｘにより第１の化合物半導体層２４に電子eが誘起される。 As shown in FIG. 12, the second compound semiconductor layer 25 is uniformly doped with silicon as an n-type impurity 25x, and an electron e is induced in the first compound semiconductor layer 24 by the n-type impurity 25x. ..

また、各化合物半導体層２４、２５のバンドギャップの大きさが異なるため、第１のキャップ層２６ａには量子井戸が形成される。 Further, since the compound semiconductor layers 24 and 25 have different bandgap sizes, a quantum well is formed in the first cap layer 26a.

第１のキャップ層２６ａにおける大部分の電子eは、その量子井戸に閉じ込められると共に、量子井戸の内部において離散的なエネルギEを取り、そのエネルギEに応じた運動量で第１の化合物半導体層２４を基板横方向に自由に走行する。 Most of the electrons e in the first cap layer 26a are confined in the quantum well and take discrete energy E inside the quantum well, and the first compound semiconductor layer 24 has a momentum corresponding to the energy E. The board freely travels in the lateral direction.

その結果、図１の例とは異なり、第１のキャップ層２６ａを基板横方向に走行する電子の大部分がn型不純物２５ｘによって散乱されず、不純物散乱に起因して第１のキャップ層２６ａの抵抗が低温下で上昇するのを防止することが可能となる。 As a result, unlike the example of FIG. 1, most of the electrons traveling in the lateral direction of the substrate through the first cap layer 26a are not scattered by the n-type impurities 25x, and the first cap layer 26a is caused by the impurity scattering. It is possible to prevent the resistance of the device from rising at a low temperature.

しかも、このようにn型の第２の化合物半導体層２５を複数設けることにより、第２の化合物半導体層２５が一層のみの場合と比較して多くの電子eを第１の化合物半導体層２４に誘起することができ、第１のキャップ層２６ａのシート抵抗を低減できる。 Moreover, by providing a plurality of n-type second compound semiconductor layers 25 in this manner, a larger number of electrons e are supplied to the first compound semiconductor layer 24 as compared with the case where the second compound semiconductor layer 25 has only one layer. It can be induced, and the sheet resistance of the first cap layer 26a can be reduced.

また、第２の化合物半導体層２５の膜厚が薄く、電子eが容易に第２の化合物半導体層２５をトンネリングすることができるため、第１のキャップ層２６ａの膜厚方向にも電子eが容易に流れることができる。そして、トンネル電流はn型不純物２５ｘによって散乱されないため、第１のキャップ層２６ａの膜厚方向の抵抗も低い状態に維持することができる。 Further, since the second compound semiconductor layer 25 has a small film thickness and the electrons e can easily tunnel the second compound semiconductor layer 25, the electrons e are also generated in the film thickness direction of the first cap layer 26a. Can flow easily. Since the tunnel current is not scattered by the n-type impurity 25x, the resistance in the film thickness direction of the first cap layer 26a can be kept low.

このように電子eが第２の化合物半導体層２５を容易にトンネリングできるようにするために、第２の化合物半導体層２５の膜厚を５nm〜１０nm程度に薄くするのが好ましい。 As described above, in order that the electrons e can easily tunnel the second compound semiconductor layer 25, the film thickness of the second compound semiconductor layer 25 is preferably thinned to about 5 nm to 10 nm.

また、上記のように量子井戸において電子eが離散的なエネルギEを取ることができるようにするためには、第１の化合物半導体層２４の膜厚を５nm〜１０nm程度に薄くするのが好ましい。 Further, in order to allow the electrons e to take discrete energy E in the quantum well as described above, it is preferable to make the thickness of the first compound semiconductor layer 24 thin to about 5 nm to 10 nm. ..

更に、このように第１のキャップ層２６ａの低抵抗化が図られるのと同じ理由によって、その第１のキャップ層２６ａと同じ構造を有する第２のキャップ層２６ｂの低抵抗化も実現できる。 Further, for the same reason that the resistance of the first cap layer 26a is reduced, the resistance of the second cap layer 26b having the same structure as that of the first cap layer 26a can be reduced.

図１３は、図１１のII-II線に沿った化合物半導体装置５０の全体のバンド構造を示す図である。 FIG. 13 is a diagram showing the entire band structure of the compound semiconductor device 50 taken along the line II-II in FIG.

図１３に示すように、この化合物半導体装置５０においては、電子供給層２３から発生した電子eがチャネル層２２に至ることで、チャネル層２２に二次元電子ガス５１が発生する。 As shown in FIG. 13, in the compound semiconductor device 50, the two-dimensional electron gas 51 is generated in the channel layer 22 by the electrons e generated from the electron supply layer 23 reaching the channel layer 22.

そして、前述のように低温下において第１のキャップ層２６ａが低抵抗化されるため、ソース電極３３ａとチャネル層２２との間に生じるソース抵抗も低温化において低抵抗化することが可能となる。 Then, as described above, the resistance of the first cap layer 26a is lowered at a low temperature, so that the source resistance generated between the source electrode 33a and the channel layer 22 can also be lowered at a low temperature. ..

特に、本実施形態では、第２の化合物半導体層２５よりもバンドギャップが狭い第１の化合物半導体層２４を第１のキャップ層２６ａの最上層に設けたため、第１のキャップ層２６ａとソース電極３３ａとの間の障壁ΔE1を低くできる。その結果、ソース電極３３ａから第１のキャップ層２６ａにスムーズに電子を供給でき、化合物半導体装置５０のソース抵抗を更に低くすることができる。 In particular, in the present embodiment, the first compound semiconductor layer 24 having a bandgap narrower than that of the second compound semiconductor layer 25 is provided as the uppermost layer of the first cap layer 26a, so that the first cap layer 26a and the source electrode are formed. The barrier ΔE 1 with respect to 33a can be lowered. As a result, electrons can be smoothly supplied from the source electrode 33a to the first cap layer 26a, and the source resistance of the compound semiconductor device 50 can be further reduced.

更に、バンドギャップの狭い第１の化合物半導体層２４を第１のキャップ層２６ａの最下層に設けることで、第１のキャップ層２６ａから電子供給層２３に電子を注入するのがバンドギャップの広い第２の化合物半導体層２５により阻害されない。これにより、第１のキャップ層２６ａから電子供給層２３に電子がスムーズに供給されるようになり、化合物半導体装置５０のソース抵抗を一層低減することが可能となる。 Further, by providing the first compound semiconductor layer 24 having a narrow bandgap as the lowermost layer of the first cap layer 26a, injecting electrons from the first cap layer 26a into the electron supply layer 23 has a wide bandgap. It is not blocked by the second compound semiconductor layer 25. As a result, electrons can be smoothly supplied from the first cap layer 26a to the electron supply layer 23, and the source resistance of the compound semiconductor device 50 can be further reduced.

本願発明者は、本実施形態における第１のキャップ層２６ａの抵抗を試算した。 The inventor of the present application calculated the resistance of the first cap layer 26a in the present embodiment.

その計算結果を図１４に示す。 The calculation result is shown in FIG.

なお、その試算においては、比較例として図１の第１のキャップ層６を採用し、その第１のキャップ層６の抵抗も計算した。図１を参照して説明したように、この第１のキャップ層６は単層のn型のInGaAs層である。 In the trial calculation, the first cap layer 6 of FIG. 1 was adopted as a comparative example, and the resistance of the first cap layer 6 was also calculated. As described with reference to FIG. 1, the first cap layer 6 is a single-layer n-type InGaAs layer.

また、本実施形態における移動度の試算に際しては第２の化合物半導体層２５の積層数を１層とし、シート抵抗の試算に際しては第２の化合物半導体層２５の積層数を５層とした。 In addition, the number of layers of the second compound semiconductor layer 25 was set to one layer in the trial calculation of the mobility in this embodiment, and the number of layers of the second compound semiconductor layer 25 was set to five layers in the trial calculation of the sheet resistance.

図１４に示すように、室温（３００K）での電子の移動度は、比較例では２，０００cm2/Vsであるのに対し、本実施形態では１０，０００cm2/Vsであり、室温においても本実施形態の方が移動度が高くなることが判明した。 As shown in FIG. 14, the electron mobility at room temperature (300K), compared to the comparative example is 2,000 cm 2 / Vs, in this exemplary embodiment is 10,000 cm 2 / Vs, even at room temperature It has been found that the mobility is higher in this embodiment.

また、極低温（４K）での電子の移動度については、比較例では２，５００cm2/Vsであって、室温（３００K）での移動度（２，０００cm2/Vs）よりも高い値となる。 The electron mobility at cryogenic temperature (4K) is 2,500 cm 2 /Vs in the comparative example, which is higher than the mobility (2,000 cm 2 /Vs) at room temperature (300K). Become.

一方、本実施形態では、極低温（４K）での電子の移動度が６０，０００cm2/Vsとなり、室温での移動度（１０，０００cm2/Vs）からの上昇率が比較例よりも大幅に増加することが明らかとなった。 On the other hand, in this embodiment, the mobility of electrons at cryogenic temperature (4K) is 60,000 cm 2 /Vs, and the rate of increase from the mobility at room temperature (10,000 cm 2 /Vs) is larger than that of the comparative example. It became clear that it will increase.

また、室温（３００K）でのシート抵抗は本実施形態も比較例も同程度である。 The sheet resistance at room temperature (300K) is the same in this embodiment and the comparative example.

しかし、極低温（４K）でのシート抵抗は、本実施形態では１０．４Ω／□となり、比較例の値（４９．９Ω／□）よりも低い値となった。 However, the sheet resistance at an extremely low temperature (4K) was 10.4Ω/□ in this embodiment, which was lower than the value of the comparative example (49.9Ω/□).

そして、室温（３００K）と極低温（４K）の各々におけるシート抵抗の比の百分率は、比較例では８０％程度であるのに対し、本実施形態ではこれよりも大幅に低い１７％となった。 The percentage of the sheet resistance ratio at room temperature (300K) and cryogenic temperature (4K) is about 80% in the comparative example, while it is 17%, which is much lower than that in the present embodiment. ..

以上の結果から、本実施形態のように第１のキャップ層２６ａを超格子構造とすることが、４K程度の極低温下における第１のキャップ層２６ａの抵抗を低減するのに有効であることが確かめられた。 From the above results, it is effective to reduce the resistance of the first cap layer 26a at an extremely low temperature of about 4K by making the first cap layer 26a a superlattice structure as in the present embodiment. Was confirmed.

このように極低温において低抵抗化が図られるため、本実施形態に係る化合物半導体装置５０は極低温下において低雑音化を実現できる。そのため、例えば電波望遠鏡用の増幅器に化合物半導体装置５０を使用し、その化合物半導体装置５０を極低温にまで冷却することで、雑音が極めて少ない観測結果を得ることが可能となる。 Since the resistance is reduced at an extremely low temperature in this manner, the compound semiconductor device 50 according to the present embodiment can realize a low noise at an extremely low temperature. Therefore, for example, by using the compound semiconductor device 50 for an amplifier for a radio telescope and cooling the compound semiconductor device 50 to an extremely low temperature, it is possible to obtain an observation result with very little noise.

（第２実施形態）
本実施形態では、以下のようにして第１のキャップ層２６ａを更に低抵抗化する。 (Second embodiment)
In this embodiment, the resistance of the first cap layer 26a is further reduced as follows.

図１５〜図１７は、本実施形態に係る化合物半導体装置の製造途中の断面図である。なお、図１５〜図１７において、第１実施形態と同じ要素には第１実施形態におけるのと同じ符号を付し、以下ではその説明を省略する。 15 to 17 are cross-sectional views of the compound semiconductor device according to this embodiment in the process of being manufactured. 15 to 17, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

まず、第１実施形態の図５（ａ）、（ｂ）の工程を行うことにより、図１５（ａ）に示すように、基板２０の上にバッファ層２１、チャネル層２２、及び電子供給層２３がこの順に積層された構造を得る。 First, by performing the steps of FIGS. 5A and 5B of the first embodiment, as shown in FIG. 15A, the buffer layer 21, the channel layer 22, and the electron supply layer are formed on the substrate 20. A structure in which 23 is stacked in this order is obtained.

続いて、図１５（ｂ）に示すように、電子供給層２３の上にi型の第１の化合物半導体層２４を５nm程度の厚さに形成する。 Subsequently, as shown in FIG. 15B, the i-type first compound semiconductor layer 24 is formed on the electron supply layer 23 to a thickness of about 5 nm.

その第１の化合物半導体層２４は、第１実施形態と同様に、MOCVD法で形成されたi型のInGaAs層である。 The first compound semiconductor layer 24 is an i-type InGaAs layer formed by the MOCVD method as in the first embodiment.

次に、図１６（ａ）に示す工程について説明する。 Next, the process shown in FIG. 16A will be described.

まず、第１の化合物半導体層２４を形成するのに使用した不図示のチャンバにInAlAs層用の成長ガスを供給し、第１の化合物半導体層２４の上に第２の化合物半導体層２５の下側層２５ａとしてi型のInAlAs層をMOCVD法で２．５nm程度の厚さに形成する。 First, the growth gas for the InAlAs layer is supplied to the chamber (not shown) used to form the first compound semiconductor layer 24, and the growth gas for the InAlAs layer is provided above the first compound semiconductor layer 24 and below the second compound semiconductor layer 25. An i-type InAlAs layer is formed as the side layer 25a by MOCVD to a thickness of about 2.5 nm.

第１実施形態で説明したように、そのInAlAs層の成長ガスのうち、Inの原料ガスとしてはトリメチルインジウムやトリエチルインジウムがあり、Alの原料ガスとしてはトリメチルアルミニウムやトリエチルアルミニウムがある。そして、Asの原料ガスとしては例えばアルシンがある。 As described in the first embodiment, among the growth gases of the InAlAs layer, the source gas of In is trimethylindium or triethylindium, and the source gas of Al is trimethylaluminum or triethylaluminum. The source gas of As includes, for example, arsine.

そして、チャンバへの成長ガスの供給を一旦停止し、チャンバ内にシリコンの原料ガスであるシラン又はジシランを供給することにより、その原料ガスに下側層２５ａの表面を曝す。これにより、下側層２５ａの表層にn型不純物であるシリコンが５×１０12cm-2程度の濃度でドープされたn型のドープ層２５ｂがプレーナドープにより形成される。 Then, the supply of the growth gas to the chamber is once stopped, and silane or disilane, which is the raw material gas of silicon, is supplied into the chamber to expose the surface of the lower layer 25a to the raw material gas. As a result, an n-type doped layer 25b doped with silicon, which is an n-type impurity, at a concentration of about 5×10 12 cm -2 is formed by planar doping on the surface layer of the lower layer 25a.

その後、InAlAs層用の成長ガスを再び上記のチャンバに供給することにより、ドープ層２５ｂの上に上側層２５ｃとしてi型のInAlAs層を２．５nm程度の厚さにMOCVD法で形成する。 Then, the growth gas for the InAlAs layer is supplied to the above chamber again to form the i-type InAlAs layer as the upper layer 25c on the doped layer 25b by the MOCVD method to a thickness of about 2.5 nm.

以上により、下側層２５ａと上側層２５ｃとの界面におけるドープ層２５ｂにn型不純物が局在した第２の化合物半導体層２５が得られる。 As described above, the second compound semiconductor layer 25 in which the n-type impurities are localized in the doped layer 25b at the interface between the lower layer 25a and the upper layer 25c is obtained.

次に、図１６（ｂ）に示すように、上記した第１の化合物半導体層２４と第２の化合物半導体層２５とを交互に複数積層することにより積層膜２６を形成する。 Next, as shown in FIG. 16B, a laminated film 26 is formed by alternately laminating a plurality of the first compound semiconductor layers 24 and the second compound semiconductor layers 25 described above.

この後は、第１実施形態で説明した図６（ｂ）〜図１１の工程を行うことにより、図１７に示すように、本実施形態に係る化合物半導体装置６０の基本構造を完成させる。 After that, the basic structure of the compound semiconductor device 60 according to the present embodiment is completed as shown in FIG. 17 by performing the steps of FIGS. 6B to 11 described in the first embodiment.

以上説明した本実施形態によれば、図１６（ａ）に示したように、第２の化合物半導体層２５をいずれもi型の下側層２５ａと上側層２５ｃとの積層構造とし、これらの界面のドープ層２５ｂにn型不純物を局在させる。 According to the present embodiment described above, as shown in FIG. 16A, each of the second compound semiconductor layers 25 has a laminated structure of the i-type lower layer 25a and the upper layer 25c, and The n-type impurities are localized in the doped layer 25b at the interface.

図１８（ａ）は、第１実施形態に係る第１のキャップ層２６ａのエネルギバンド構造を示す図であり、図１８（ｂ）は、本実施形態に係る第１のキャップ層２６ａのエネルギバンド構造を示す図である。 18A is a diagram showing the energy band structure of the first cap layer 26a according to the first embodiment, and FIG. 18B is the energy band structure of the first cap layer 26a according to the present embodiment. It is a figure which shows a structure.

図１８（ａ）に示すように、各化合物半導体層２４、２５のバンドギャップの差ΔEgが有限であるため、電子eの波動関数φの裾野部分は第２の化合物半導体層２５に重なる。よって、第２の化合物半導体層２５内にもある程度の確率で電子eが存在することになるが、第１実施形態では第２の化合物半導体層２５内に均一にn型不純物２５ｘが分散しているため、第２の化合物半導体層２５内の電子eがn型不純物２５ｘによって散乱される。 As shown in FIG. 18A, since the difference ΔE g between the band gaps of the compound semiconductor layers 24 and 25 is finite, the foot portion of the wave function φ of the electron e overlaps the second compound semiconductor layer 25. Therefore, the electrons e also exist in the second compound semiconductor layer 25 with a certain probability, but in the first embodiment, the n-type impurities 25x are uniformly dispersed in the second compound semiconductor layer 25. Therefore, the electrons e in the second compound semiconductor layer 25 are scattered by the n-type impurity 25x.

一方、図１８（ａ）に示すように、本実施形態においても上記と同じ理由で電子eの波動関数φの裾野部分が第２の化合物半導体層２５に重なるため、第２の化合物半導体層２５内にもある程度の確率で電子eが存在する。 On the other hand, as shown in FIG. 18A, in the present embodiment as well, the skirt portion of the wave function φ of the electron e overlaps the second compound semiconductor layer 25 for the same reason as described above, and thus the second compound semiconductor layer 25 is formed. There is also a probability that electron e exists inside.

但し、本実施形態では下側層２５ａと上側層２５ｃの界面にn型不純物２５ｘが局在しているため、波動関数φの裾野部分とn型不純物２５ｘとが重なり難くなる。 However, in this embodiment, since the n-type impurity 25x is localized at the interface between the lower layer 25a and the upper layer 25c, it is difficult for the skirt portion of the wave function φ and the n-type impurity 25x to overlap.

よって、第２の化合物半導体層２５内に存在する電子eがn型不純物２５ｘによって散乱され難くなり、第１のキャップ層２６ａにおける電子の移動度を第１実施形態よりも高くすることが可能となる。 Therefore, the electrons e existing in the second compound semiconductor layer 25 are less likely to be scattered by the n-type impurity 25x, and the electron mobility in the first cap layer 26a can be made higher than that in the first embodiment. Become.

特に、下側層２５ａと上側層２５ｃのそれぞれの膜厚を同一にすることで、第２の化合物半導体層２５の両側の各波動関数φからn型不純物２５ｘを均等に離すことができる。その結果、第２の化合物半導体層２５の表面と裏面の両方に存在する電子eがn型不純物２５ｘによって散乱され難くなるため、電子の移動度を更に高めることができる。 In particular, by making the thicknesses of the lower layer 25a and the upper layer 25c the same, the n-type impurities 25x can be evenly separated from the wave functions φ on both sides of the second compound semiconductor layer 25. As a result, the electrons e existing on both the front surface and the back surface of the second compound semiconductor layer 25 are less likely to be scattered by the n-type impurities 25x, so that the electron mobility can be further increased.

（第３実施形態）
本実施形態では、以下のようにして更にソース抵抗を低減する。 (Third Embodiment)
In this embodiment, the source resistance is further reduced as follows.

図１９〜図２０は、本実施形態に係る化合物半導体装置の製造途中の断面図である。なお、図１９〜図２０において、第１実施形態と同じ要素には第１実施形態におけるのと同じ符号を付し、以下ではその説明を省略する。 19 to 20 are cross-sectional views of the compound semiconductor device according to the present embodiment during manufacturing. 19 to 20, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

まず、第１実施形態の図５（ａ）、（ｂ）の工程を行うことにより、図１９（ａ）に示すように、基板２０の上にバッファ層２１、チャネル層２２、及び電子供給層２３がこの順に積層された構造を得る。 First, by performing the steps of FIGS. 5A and 5B of the first embodiment, as shown in FIG. 19A, the buffer layer 21, the channel layer 22, and the electron supply layer are formed on the substrate 20. A structure in which 23 is stacked in this order is obtained.

次に、図１９（ｂ）に示すように、電子供給層２３を形成したのと同じチャンバ内において成長ガスを交互に切り替えることにより、MOCVD法でi型の第１の化合物半導体層２４とn型の第２の化合物半導体層２５とを交互に複数積層し、積層膜２６を形成する。 Next, as shown in FIG. 19B, the growth gas is alternately switched in the same chamber in which the electron supply layer 23 is formed, so that the i-type first compound semiconductor layer 24 and the n-type compound semiconductor layer 24 are formed by the MOCVD method. A plurality of second type compound semiconductor layers 25 are alternately laminated to form a laminated film 26.

これらの化合物半導体層のうち、i型の第１の化合物半導体層２４は厚さが５nｍのInGaAs層である。 Among these compound semiconductor layers, the i-type first compound semiconductor layer 24 is an InGaAs layer having a thickness of 5 nm.

また、n型の第２の化合物半導体層２５は、第１実施形態と同様にn型不純物としてシリコンが１×１０19cm-2程度の濃度で均一にドープされた厚さが５nmのInAlAs層である。 The n-type second compound semiconductor layer 25 is an InAlAs layer having a thickness of 5 nm that is uniformly doped with silicon as an n-type impurity at a concentration of about 1×10 19 cm −2 as in the first embodiment. Is.

但し、本実施形態では、積層膜２６の最上層に近づくにつれそのInAlAs層におけるAlの組成比を低くすることにより、最上層に近づくにつれて第２の化合物半導体層２５のバンドギャップを狭くする。このようにAlの組成比を低くするには、第２の化合物半導体層２５の成長ガスに含まれるトリメチルアルミニウムやトリエチルアルミニウム等のAlの原料ガスの流量比を低くすればよい。 However, in the present embodiment, the band gap of the second compound semiconductor layer 25 is narrowed toward the uppermost layer by lowering the Al composition ratio in the InAlAs layer as the uppermost layer of the laminated film 26 is approached. As described above, in order to reduce the Al composition ratio, the flow rate ratio of the Al source gas such as trimethylaluminum or triethylaluminum contained in the growth gas of the second compound semiconductor layer 25 may be decreased.

この例では第２の化合物半導体層２５の層数を５層とし、最上層から数えて１〜２層目までの第２の化合物半導体層２５の材料を上から順にIn0.65Al0.35As、In0.60Al0.40As、In0.55Al0.45Asとする。そして、これよりも下の３層の第２の化合物半導体層２５の材料はいずれもIn0.52Al0.48Asとする。 In this example, the number of layers of the second compound semiconductor layer 25 is set to 5, and the materials of the second compound semiconductor layer 25 from the uppermost layer to the first to second layers are In 0.65 Al 0.35 As, In 0.60 Al 0.40 As and In 0.55 Al 0.45 As. Then, the materials of the three second compound semiconductor layers 25 below this are all In 0.52 Al 0.48 As.

この後は、第１実施形態で説明した図６（ｂ）〜図１１の工程を行うことにより、図２０に示すように、本実施形態に係る化合物半導体装置７０の基本構造を完成させる。 After that, the basic structure of the compound semiconductor device 70 according to the present embodiment is completed as shown in FIG. 20 by performing the steps of FIGS. 6B to 11 described in the first embodiment.

以上説明した本実施形態によれば、第１のキャップ層２６ａにおける複数の第２の化合物半導体層２５の各々のバンドギャップを、第１のキャップ層２６ａの最上層に近づくにつれて狭くする。 According to the present embodiment described above, the band gap of each of the plurality of second compound semiconductor layers 25 in the first cap layer 26a is narrowed toward the uppermost layer of the first cap layer 26a.

図２１は、図２０のIII-III線に沿った化合物半導体装置７０の全体のバンド構造を示す図である。 21 is a diagram showing the entire band structure of the compound semiconductor device 70 along the line III-III in FIG.

図２１に示すように、前述のように第１のキャップ層２６ａの最上層に近づくにつれて第２の化合物半導体層２５の各々のバンドギャップを狭くした結果、ソース電極３３ａと最上層の第２の化合物半導体層２５との間の障壁の高さΔE2を低くできる。 As shown in FIG. 21, as described above, as the band gap of each of the second compound semiconductor layers 25 is narrowed toward the uppermost layer of the first cap layer 26a, as a result, the source electrode 33a and the second uppermost layer are formed. The height ΔE 2 of the barrier with the compound semiconductor layer 25 can be reduced.

その結果、ソース電極３３ａと第１のキャップ層２６ａとの間に生じるオーミックコンタクト抵抗が低減し、ソース抵抗を更に低くすることが可能となる。 As a result, the ohmic contact resistance generated between the source electrode 33a and the first cap layer 26a is reduced, and the source resistance can be further reduced.

なお、上記ではn型の第２の化合物半導体層２５に均一にn型不純物をドープしたが、第２実施形態のようにプレーナドープにより第２の化合物半導体層２５にn型不純物をドープしてもよい。 Although the n-type second compound semiconductor layer 25 is uniformly doped with the n-type impurity in the above description, the second compound semiconductor layer 25 is doped with the n-type impurity by planar doping as in the second embodiment. Good.

（その他の実施形態）
上記した第１〜第３実施形態では化合物半導体装置としてInP HEMTを製造したが、そのInP HEMTにおける各層の材料は上記に限定されない。更に、化合物半導体装置もInP HEMTに限定されない。 (Other embodiments)
InP HEMTs are manufactured as compound semiconductor devices in the above-described first to third embodiments, but the material of each layer in the InP HEMTs is not limited to the above. Furthermore, the compound semiconductor device is not limited to InP HEMT.

本実施形態では、化合物半導体装置や各層のバリエーションについて説明する。 In this embodiment, a compound semiconductor device and variations of each layer will be described.

＜InP HEMT＞
図２２は、第１〜第３実施形態と同様に化合物半導体装置としてInP HEMTを製造する場合における各層の材料の他の例について示す図である。 <InP HEMT>
FIG. 22 is a diagram showing another example of the material of each layer in the case of manufacturing an InP HEMT as a compound semiconductor device similarly to the first to third embodiments.

図２２に示すように、第１の化合物半導体層２４の材料としては、第１実施形態で説明したi型のInGaAsの他に、i型のInAsを採用し得る。この場合、第２の化合物半導体層２５の材料としてはn型のInAlAsやn型のInGaAsを採用し得る。 As shown in FIG. 22, as the material of the first compound semiconductor layer 24, i-type InAs can be adopted in addition to the i-type InGaAs described in the first embodiment. In this case, as the material of the second compound semiconductor layer 25, n-type InAlAs or n-type InGaAs can be adopted.

＜GaN HEMT＞
図２３は、化合物半導体装置としてGaN HEMTを製造する場合の各層の材料の例について示す図である。 <GaN HEMT>
FIG. 23 is a diagram showing an example of the material of each layer in the case of manufacturing a GaN HEMT as a compound semiconductor device.

GaN HEMTは、チャネル層２２がGaN層のHEMTである。この場合は、基板２０としてGaN基板を採用し、電子供給層２３の材料としてn型のAlGaNを採用し得る。また、第１の化合物半導体層２４の材料は例えばi型のInGaNであり、第２の化合物半導体層２５の材料はいずれもn型のGaN又はAlGaNである。 The GaN HEMT is a HEMT in which the channel layer 22 is a GaN layer. In this case, a GaN substrate may be used as the substrate 20, and n-type AlGaN may be used as the material of the electron supply layer 23. The material of the first compound semiconductor layer 24 is, for example, i-type InGaN, and the material of the second compound semiconductor layer 25 is n-type GaN or AlGaN.

＜GaAs HEMT＞
図２４は、化合物半導体装置としてGaAs HEMTを製造する場合の各層の材料の例について示す図である。 <GaAs HEMT>
FIG. 24 is a diagram showing an example of the material of each layer when a GaAs HEMT is manufactured as a compound semiconductor device.

GaAs HEMTは、チャネル層２２がGaAs層のHEMTである。この場合は、基板２０としてGaAs基板を採用し、電子供給層２３の材料としてn型のAlGaAsを採用し得る。また、第１の化合物半導体層２４の材料は例えばいずれもi型のGaAs又はInGaAsであり、第２の化合物半導体層２５の材料はn型のAlGaAsである。 The GaAs HEMT is a HEMT in which the channel layer 22 is a GaAs layer. In this case, a GaAs substrate may be used as the substrate 20, and n-type AlGaAs may be used as the material of the electron supply layer 23. The material of the first compound semiconductor layer 24 is, for example, i-type GaAs or InGaAs, and the material of the second compound semiconductor layer 25 is n-type AlGaAs.

以上説明した各実施形態に関し、更に以下の付記を開示する。 The following supplementary notes will be disclosed with respect to the respective embodiments described above.

（付記１） 基板と、
前記基板の上方に形成されたチャネル層と、
前記チャネル層の上に形成された電子供給層と、
前記電子供給層の上に互いに間隔をおいて形成された第１のキャップ層及び第２のキャップ層と、
前記第１のキャップ層の上に形成されたソース電極と、
前記第２のキャップ層の上に形成されたドレイン電極と、
前記第１のキャップ層と前記第２のキャップ層の間における前記電子供給層の上に形成されたゲート電極とを備え、
前記第１のキャップ層と前記第２のキャップ層の各々が、i型の第１の化合物半導体層と、前記第１の化合物半導体層よりもバンドギャップが広いn型の第２の化合物半導体層とが交互に複数積層された積層膜であることを特徴とする化合物半導体装置。 (Appendix 1) a substrate,
A channel layer formed above the substrate,
An electron supply layer formed on the channel layer,
A first cap layer and a second cap layer formed on the electron supply layer with a space therebetween,
A source electrode formed on the first cap layer,
A drain electrode formed on the second cap layer,
A gate electrode formed on the electron supply layer between the first cap layer and the second cap layer,
Each of the first cap layer and the second cap layer is an i-type first compound semiconductor layer and an n-type second compound semiconductor layer having a wider bandgap than the first compound semiconductor layer. 2. A compound semiconductor device, comprising: a laminated film in which a plurality of and are alternately laminated.

（付記２） 前記第２の化合物半導体層は、
i型の化合物半導体を材料とする下側層と、
前記下側層の上に形成され、前記i型の化合物半導体を材料とする上側層とを有し、
前記下側層と前記上側層との界面にn型不純物が局在していることを特徴とする付記１に記載の化合物半導体装置。 (Supplementary Note 2) The second compound semiconductor layer comprises:
a lower layer made of an i-type compound semiconductor,
Formed on the lower layer, having an upper layer made of the i-type compound semiconductor as a material,
2. The compound semiconductor device according to Appendix 1, wherein n-type impurities are localized at the interface between the lower layer and the upper layer.

（付記３） 前記下側層と前記上側層の各々の膜厚が等しいことを特徴とする付記２に記載の化合物半導体装置。 (Supplementary Note 3) The compound semiconductor device according to Supplementary Note 2, wherein the film thicknesses of the lower layer and the upper layer are equal.

（付記４） 複数の前記第２の化合物半導体層の各々のバンドギャップは、前記積層膜の最上層に近づくにつれて狭くなることを特徴とする付記１に記載の化合物半導体装置。 (Supplementary Note 4) The compound semiconductor device according to Supplementary Note 1, wherein the band gap of each of the plurality of second compound semiconductor layers becomes narrower toward the uppermost layer of the laminated film.

（付記５） 前記積層膜の最上層は、前記第１の化合物半導体層であることを特徴とする付記１に記載の化合物半導体装置。 (Supplementary Note 5) The compound semiconductor device according to Supplementary Note 1, wherein the uppermost layer of the laminated film is the first compound semiconductor layer.

（付記６） 前記積層膜の最下層は、前記第１の化合物半導体層であることを特徴とする付記１に記載の化合物半導体装置。 (Supplementary Note 6) The compound semiconductor device according to Supplementary Note 1, wherein the lowermost layer of the laminated film is the first compound semiconductor layer.

（付記７） 基板の上方にチャネル層を形成する工程と、
前記チャネル層の上に電子供給層を形成する工程と、
前記電子供給層の上に、i型の第１の化合物半導体層と、前記第１の化合物半導体層よりもバンドギャップが広いn型の第２の化合物半導体層とを交互に複数形成することにより、前記第１の化合物半導体層と前記第２の化合物半導体層の積層膜を形成する工程と、
前記積層膜をパターニングすることにより、互いに間隔がおかれた第１のキャップ層と第２のキャップ層とを形成する工程と、
前記第１のキャップ層の上にソース電極を形成する工程と、
前記第２のキャップ層の上にドレイン電極を形成する工程と、
前記第１のキャップ層と前記第２のキャップ層の間における前記電子供給層の上にゲート電極を形成する工程と、
を有することを特徴とする化合物半導体装置の製造方法。 (Supplementary Note 7) A step of forming a channel layer above a substrate,
Forming an electron supply layer on the channel layer,
By alternately forming a plurality of i-type first compound semiconductor layers and n-type second compound semiconductor layers having a wider bandgap than the first compound semiconductor layers on the electron supply layer. Forming a laminated film of the first compound semiconductor layer and the second compound semiconductor layer,
Patterning the laminated film to form a first cap layer and a second cap layer spaced apart from each other;
Forming a source electrode on the first cap layer;
Forming a drain electrode on the second cap layer;
Forming a gate electrode on the electron supply layer between the first cap layer and the second cap layer;
A method of manufacturing a compound semiconductor device, comprising:

（付記８） 前記第２の化合物半導体層を形成する工程は、
i型の化合物半導体を材料とする下側層を形成する工程と、
n型不純物を含むガスに前記下側層の表面を曝す工程と、
前記ガスに前記下側層の前記表面を曝した後、前記表面の上に、前記i型の化合物半導体を材料とする上側層を形成し、前記下側層と前記上側層とを前記第２の化合物半導体層にする工程とを有することを特徴とする付記７に記載の化合物半導体装置の製造方法。 (Supplementary Note 8) In the step of forming the second compound semiconductor layer,
a step of forming a lower layer made of an i-type compound semiconductor,
exposing the surface of the lower layer to a gas containing n-type impurities;
After exposing the surface of the lower layer to the gas, an upper layer made of the i-type compound semiconductor is formed on the surface, and the lower layer and the upper layer are formed into the second layer. 8. The method of manufacturing a compound semiconductor device according to appendix 7, further comprising: a step of forming the compound semiconductor layer.

（付記９） 前記下側層と前記上側層の各々の膜厚が等しいことを特徴とする付記７に記載の化合物半導体装置の製造方法。 (Supplementary Note 9) The method for producing a compound semiconductor device according to Supplementary Note 7, wherein the film thicknesses of the lower layer and the upper layer are equal.

１、５０、６０、７０…化合物半導体装置、２…InP基板、３…バッファ層、４…チャネル層、５…電子供給層、５ａ…スペーサ層、５ｂ…ドープ層、５ｃ…バリア層、６…第１のキャップ層、７…第２のキャップ層、８…ソース電極、９…ドレイン電極、１０…ゲート電極、１１…二次元電子ガス、２０…化合物半導体基板、２１…バッファ層、２２…チャネル層、２３…電子供給層、２３ａ…スペーサ層、２３…ドープ層、２３ｃ…バリア層、２４…第１の化合物半導体層、２５…第２の化合物半導体層、２５ａ…下側層、２５ｂ…ドープ層、２５ｃ…上側層、２６…積層膜、２６ｘ…溝、２９…素子分離溝、３０…第１のレジスト層、３１…第２のレジスト層、３１ａ…第１の開口、３１ｂ…第２の開口、３３…金属積層膜、３３ａ…ソース電極、３３ｂ…ドレイン電極、３５…第３のレジスト層、３５ａ…第３の開口、４１…第４のレジスト層、４１ａ…ホール、４２…第５のレジスト層、４２ａ…第５の開口、４３…第６のレジスト層、４３ａ…第４の開口、４５…金属積層膜、４５ａ…ゲート電極。 1, 50, 60, 70... Compound semiconductor device, 2... InP substrate, 3... Buffer layer, 4... Channel layer, 5... Electron supply layer, 5a... Spacer layer, 5b... Doped layer, 5c... Barrier layer, 6... 1st cap layer, 7... 2nd cap layer, 8... Source electrode, 9... Drain electrode, 10... Gate electrode, 11... Two-dimensional electron gas, 20... Compound semiconductor substrate, 21... Buffer layer, 22... Channel Layer, 23... Electron supply layer, 23a... Spacer layer, 23... Doped layer, 23c... Barrier layer, 24... First compound semiconductor layer, 25... Second compound semiconductor layer, 25a... Lower layer, 25b... Doped Layer, 25c... Upper layer, 26... Laminated film, 26x... Trench, 29... Element isolation trench, 30... First resist layer, 31... Second resist layer, 31a... First opening, 31b... Second Opening, 33... Metal laminated film, 33a... Source electrode, 33b... Drain electrode, 35... Third resist layer, 35a... Third opening, 41... Fourth resist layer, 41a... Hole, 42... Fifth Resist layer, 42a... Fifth opening, 43... Sixth resist layer, 43a... Fourth opening, 45... Metal laminated film, 45a... Gate electrode.

Claims (5)

基板と、
前記基板の上方に形成されたチャネル層と、
前記チャネル層の上に形成された電子供給層と、
前記電子供給層の上に互いに間隔をおいて形成された第１のキャップ層及び第２のキャップ層と、
前記第１のキャップ層の上に形成されたソース電極と、
前記第２のキャップ層の上に形成されたドレイン電極と、
前記第１のキャップ層と前記第２のキャップ層の間における前記電子供給層の上に形成されたゲート電極とを備え、
前記第１のキャップ層と前記第２のキャップ層の各々が、ｉ型の第１の化合物半導体層と、前記第１の化合物半導体層よりもバンドギャップが広いｎ型の第２の化合物半導体層とが交互に複数積層された積層膜であり、
前記積層膜の最上層は、前記ｉ型の前記第１の化合物半導体層であることを特徴とする化合物半導体装置。 Board,
A channel layer formed above the substrate,
An electron supply layer formed on the channel layer,
A first cap layer and a second cap layer formed on the electron supply layer with a space therebetween,
A source electrode formed on the first cap layer,
A drain electrode formed on the second cap layer,
A gate electrode formed on the electron supply layer between the first cap layer and the second cap layer,
Each of the first cap layer and the second cap layer is an i-type first compound semiconductor layer and an n-type second compound semiconductor layer having a wider bandgap than the first compound semiconductor layer. Ri laminated film der which bets are alternately stacked,
A compound semiconductor device , wherein an uppermost layer of the laminated film is the i-type first compound semiconductor layer . 前記第２の化合物半導体層は、
ｉ型の化合物半導体を材料とする下側層と、
前記下側層の上に形成され、前記i型の化合物半導体を材料とする上側層とを有し、
前記下側層と前記上側層との界面にn型不純物が局在していることを特徴とする請求項１に記載の化合物半導体装置。 The second compound semiconductor layer is
a lower layer made of an i-type compound semiconductor,
Formed on the lower layer, having an upper layer made of the i-type compound semiconductor as a material,
The compound semiconductor device according to claim 1, wherein an n-type impurity is localized at an interface between the lower layer and the upper layer. 複数の前記第２の化合物半導体層の各々のバンドギャップは、前記積層膜の最上層に近づくにつれて狭くなることを特徴とする請求項１に記載の化合物半導体装置。 The compound semiconductor device according to claim 1, wherein a band gap of each of the plurality of second compound semiconductor layers becomes narrower toward an uppermost layer of the laminated film. 前記積層膜の最下層は、前記ｉ型の前記第１の化合物半導体層であることを特徴とする請求項１に記載の化合物半導体装置。 The compound semiconductor device according to claim 1, wherein a lowermost layer of the laminated film is the first compound semiconductor layer of the i-type . 基板の上方にチャネル層を形成する工程と、
前記チャネル層の上に電子供給層を形成する工程と、
前記電子供給層の上に、ｉ型の第１の化合物半導体層と、前記第１の化合物半導体層よりもバンドギャップが広いn型の第２の化合物半導体層とを交互に複数形成することにより、前記ｉ型の前記第１の化合物半導体層と前記ｎ型の前記第２の化合物半導体層の積層膜を形成し、前記積層膜の最上層を前記ｉ型の前記第１の化合物半導体層とする工程と、
前記積層膜をパターニングすることにより、互いに間隔がおかれた第１のキャップ層と第２のキャップ層とを形成する工程と、
前記第１のキャップ層の上にソース電極を形成する工程と、
前記第２のキャップ層の上にドレイン電極を形成する工程と、
前記第１のキャップ層と前記第２のキャップ層の間における前記電子供給層の上にゲート電極を形成する工程と、
を有することを特徴とする化合物半導体装置の製造方法。 Forming a channel layer above the substrate,
Forming an electron supply layer on the channel layer,
By alternately forming a plurality of i-type first compound semiconductor layers and n-type second compound semiconductor layers having a wider band gap than the first compound semiconductor layers on the electron supply layer. A laminated film of the i-type first compound semiconductor layer and the n-type second compound semiconductor layer is formed, and the uppermost layer of the laminated film is the i-type first compound semiconductor layer. The process of
Patterning the laminated film to form a first cap layer and a second cap layer spaced apart from each other;
Forming a source electrode on the first cap layer;
Forming a drain electrode on the second cap layer;
Forming a gate electrode on the electron supply layer between the first cap layer and the second cap layer;
A method of manufacturing a compound semiconductor device, comprising:
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