JP6658429B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6658429B2 JP6658429B2 JP2016188202A JP2016188202A JP6658429B2 JP 6658429 B2 JP6658429 B2 JP 6658429B2 JP 2016188202 A JP2016188202 A JP 2016188202A JP 2016188202 A JP2016188202 A JP 2016188202A JP 6658429 B2 JP6658429 B2 JP 6658429B2
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- 238000013461 design Methods 0.000 description 3
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- 238000000034 method Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001151 other effect Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19032—Structure including wave guides being a microstrip line type
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19101—Disposition of discrete passive components
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Description
図1は、本発明の実施の形態1に係る半導体装置を示す平面図である。図2は、図1のI−IIに沿った断面図である。パッケージの金属部分であるベース1上に、プリマッチ回路を有する回路基板P1と、GaNなどの電界効果トランジスタを有する半導体基板T1とが設けられている。ベース1上において、回路基板P1と半導体基板T1はパッケージの側壁2で囲われている。側壁2の互いに対向する辺に入力端子INと出力端子OUTが設けられている。ワイヤW11〜W14が入力端子INと回路基板P1を接続する。ワイヤW21〜W24が回路基板P1と半導体基板T1を接続する。ワイヤW31〜W34が半導体基板T1と出力端子OUTを接続する。側壁2の内側はふた3で覆われている。
図11は、本発明の実施の形態2に係る半導体装置を示す平面図である。回路基板P1は、複数の回路パターン11〜14の入力と複数の第1入力パッドPD11〜PD14をそれぞれ接続する複数の第2マイクロストリップ線路L21〜L24を有する。一列に並んだ複数の回路パターン11〜14のうち両端に配置された回路パターン11,14に接続された第2マイクロストリップ線路L21,L24は他の第2マイクロストリップ線路L22,L23よりも長い。これにより、ワイヤW11,W14の小さい相互インダクタンスを補うことができるため、実施の形態1よりも更に負荷インピーダンスの均一性を高めることができる。その他の効果は実施の形態1と同様である。なお、複数の第2マイクロストリップ線路L21〜L24の長さを複数の回路パターン11〜14の両端に近づくに従って長くなるように設定してもよい。
図12は、本発明の実施の形態3に係る半導体装置を示す平面図である。実施の形態2の構成に加えて、半導体基板T1は、複数のトランジスタセルTr1〜Tr4の出力と複数の第2出力パッドPD41〜PD44をそれぞれ接続する複数の第3マイクロストリップ線路L31〜L34を有する。一列に並んだ複数のトランジスタセルTr1〜Tr4のうち両端に配置されたトランジスタセルTr1,Tr4に接続された第3マイクロストリップ線路L31,L34は他の第3マイクロストリップ線路L32,L33よりも長い。これにより、ワイヤW31,W34の小さい相互インダクタンスを補うことができるため、出力負荷インピーダンスの均一性を高めることができる。その他の効果は実施の形態1,2と同様である。なお、複数の第3マイクロストリップ線路L31〜L34の長さを複数のトランジスタセルTr1〜Tr4の両端に近づくに従って長くなるように設定してもよい。
図13は、本発明の実施の形態4に係る半導体装置を示す平面図である。本実施の形態では、入力整合回路を構成する2つ回路基板P1,P2が並んで配置されている。回路基板P1,P2のレイアウトは互いに同じである。回路基板P1,P2のそれぞれの両端に配置された回路パターン11,14には、第4マイクロストリップ線路L11a,L14aを介してそれぞれ第1パッドPD21a、PD24aが接続され、第4マイクロストリップ線路L11a,L14aよりも長い第5マイクロストリップ線路L11b,L14bを介して第2パッドPD21b、PD24bが接続されている。第4マイクロストリップ線路L11a,L14aは第1マイクロストリップ線路L12,L13と同様に設計されている。第5マイクロストリップ線路L11b,L14bは実施の形態1の第1マイクロストリップ線路L11,L14と同様に設計されている。
図14は、本発明の実施の形態5に係る半導体装置を示す平面図である。図15は、本発明の実施の形態5に係る半導体装置を示す回路図である。本実施の形態では、実施の形態1とは異なり、直列容量C11〜C14が並列容量C21〜C24と第1出力パッドPD21〜PD24の間に接続されている。また、相互インダクタンス補正のためのマイクロストリップ線路は無く、その代わりに直列容量C11〜C14の容量値を調整している。前述したように直列インダクタンスはスミスチャートの等レジスタンス円上で軌跡を描く。同様に直列容量も等レジスタンス円上で軌跡を描く。そのため、直列容量の容量値を調整することで、特定の周波数帯では負荷インピーダンスを均一化できる。
Claims (7)
- 入力端子と、
並列容量を含む複数の回路パターンと、前記複数の回路パターンの入力にそれぞれ接続された複数の第1入力パッドと、複数の第1出力パッドと、前記複数の回路パターンの出力と前記複数の第1出力パッドをそれぞれ接続する複数の第1マイクロストリップ線路とを有する回路基板と、
複数のトランジスタセルと、前記複数のトランジスタセルの入力に接続された複数の第2入力パッドと、前記複数のトランジスタセルの出力に接続された複数の第2出力パッドとを有する半導体基板と、
出力端子と、
前記入力端子と前記複数の第1入力パッドをそれぞれ接続する複数の第1ワイヤと、
前記複数の第1出力パッドと前記複数の第2入力パッドをそれぞれ接続する複数の第2ワイヤと、
前記複数の第2出力パッドと前記出力端子をそれぞれ接続する複数の第3ワイヤとを備え、
各トランジスタセルは、複数のフィンガーが並列に接続されたものであり、ビアホールを介して裏面電極に接続されたソース電極を有し、
前記複数のトランジスタセルのフィンガー数は互いに同じであり、
一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンに接続された第1マイクロストリップ線路は他の第1マイクロストリップ線路よりも長く、
前記回路基板は、前記複数の回路パターンの入力と前記複数の第1入力パッドをそれぞれ接続する複数の第2マイクロストリップ線路を有し、
一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンに接続された第2マイクロストリップ線路は他の第2マイクロストリップ線路よりも長いことを特徴とする半導体装置。 - 入力端子と、
並列容量を含む複数の回路パターンと、前記複数の回路パターンの入力にそれぞれ接続された複数の第1入力パッドと、複数の第1出力パッドと、前記複数の回路パターンの出力と前記複数の第1出力パッドをそれぞれ接続する複数の第1マイクロストリップ線路とを有する回路基板と、
複数のトランジスタセルと、前記複数のトランジスタセルの入力に接続された複数の第2入力パッドと、前記複数のトランジスタセルの出力に接続された複数の第2出力パッドとを有する半導体基板と、
出力端子と、
前記入力端子と前記複数の第1入力パッドをそれぞれ接続する複数の第1ワイヤと、
前記複数の第1出力パッドと前記複数の第2入力パッドをそれぞれ接続する複数の第2ワイヤと、
前記複数の第2出力パッドと前記出力端子をそれぞれ接続する複数の第3ワイヤとを備え、
各トランジスタセルは、複数のフィンガーが並列に接続されたものであり、ビアホールを介して裏面電極に接続されたソース電極を有し、
前記複数のトランジスタセルのフィンガー数は互いに同じであり、
一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンに接続された第1マイクロストリップ線路は他の第1マイクロストリップ線路よりも長く、
前記半導体基板は、前記複数のトランジスタセルの出力と前記複数の第2出力パッドをそれぞれ接続する複数の第3マイクロストリップ線路を有し、
一列に並んだ前記複数のトランジスタセルのうち両端に配置されたトランジスタセルに接続された第3マイクロストリップ線路は他の第3マイクロストリップ線路よりも長いことを特徴とする半導体装置。 - 入力端子と、
並列容量を含む複数の回路パターンと、前記複数の回路パターンの入力にそれぞれ接続された複数の第1入力パッドと、複数の第1出力パッドと、前記複数の回路パターンの出力と前記複数の第1出力パッドをそれぞれ接続する複数の第1マイクロストリップ線路とを有する回路基板と、
複数のトランジスタセルと、前記複数のトランジスタセルの入力に接続された複数の第2入力パッドと、前記複数のトランジスタセルの出力に接続された複数の第2出力パッドとを有する半導体基板と、
出力端子と、
前記入力端子と前記複数の第1入力パッドをそれぞれ接続する複数の第1ワイヤと、
前記複数の第1出力パッドと前記複数の第2入力パッドをそれぞれ接続する複数の第2ワイヤと、
前記複数の第2出力パッドと前記出力端子をそれぞれ接続する複数の第3ワイヤとを備え、
各トランジスタセルは、複数のフィンガーが並列に接続されたものであり、ビアホールを介して裏面電極に接続されたソース電極を有し、
前記複数のトランジスタセルのフィンガー数は互いに同じであり、
一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンに接続された第1マイクロストリップ線路は他の第1マイクロストリップ線路よりも長く、
前記回路基板は、並んで配置された第1及び第2の基板を有し、
前記第1及び第2の基板のそれぞれの両端に配置された回路パターンには、第4マイクロストリップ線路を介して第1パッドが接続され、前記第4マイクロストリップ線路よりも長い第5マイクロストリップ線路を介して第2パッドが接続され、
前記第1及び第2の基板の互いに隣接する内端に配置された回路パターンでは前記第1パッドに前記第2ワイヤが接続され、
前記第1及び第2の基板の外端に配置された回路パターンでは前記第2パッドに前記第2ワイヤが接続されることを特徴とする半導体装置。 - 前記複数の第1マイクロストリップ線路の長さは、前記複数の回路パターンの両端に近づくに従って長くなることを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンに接続された第1マイクロストリップ線路の特性インピーダンスは50Ω〜200Ωであることを特徴とする請求項1〜4の何れか1項に記載の半導体装置。
- 入力端子と、
複数の回路パターンと、前記複数の回路パターンの入力にそれぞれ接続された複数の第1入力パッドと、前記複数の回路パターンの出力にそれぞれ接続された複数の第1出力パッドとを有する回路基板と、
複数のトランジスタセルと、前記複数のトランジスタセルの入力に接続された複数の第2入力パッドと、前記複数のトランジスタセルの出力に接続された複数の第2出力パッドとを有する半導体基板と、
出力端子と、
前記入力端子と前記複数の第1入力パッドをそれぞれ接続する複数の第1ワイヤと、
前記複数の第1出力パッドと前記複数の第2入力パッドをそれぞれ接続する複数の第2ワイヤと、
前記複数の第2出力パッドと前記出力端子をそれぞれ接続する複数の第3ワイヤとを備え、
各トランジスタセルは、複数のフィンガーが並列に接続されたものであり、ビアホールを介して裏面電極に接続されたソース電極を有し、
前記複数のトランジスタセルのフィンガー数は互いに同じであり、
各回路パターンは、並列容量と、前記並列容量と前記第1出力パッドの間に接続された直列容量と、前記直列容量に並列に接続された抵抗とを有し、
一列に並んだ前記複数の回路パターンのうち両端に配置された回路パターンの直列容量の容量値は他の直列容量の容量値よりも大きいことを特徴とする半導体装置。 - 前記複数の回路パターンの直列容量の容量値は、前記複数の回路パターンの両端に近づくに従って大きくなることを特徴とする請求項6に記載の半導体装置。
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