JP6623056B2 - 配線基板、半導体装置 - Google Patents
配線基板、半導体装置 Download PDFInfo
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- JP6623056B2 JP6623056B2 JP2015244936A JP2015244936A JP6623056B2 JP 6623056 B2 JP6623056 B2 JP 6623056B2 JP 2015244936 A JP2015244936 A JP 2015244936A JP 2015244936 A JP2015244936 A JP 2015244936A JP 6623056 B2 JP6623056 B2 JP 6623056B2
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- insulating layer
- layer
- wiring layer
- wiring
- treatment film
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Description
[第1の実施の形態に係る半導体装置の構造]
まず、第1の実施の形態に係る半導体装置の構造について説明する。図1は、第1の実施の形態に係る半導体装置を例示する図であり、図1(a)は断面図、図1(b)は図1(a)の絶縁層11と配線層12のみを示した部分拡大平面図である。なお、図1(a)は図1(b)のA−A線に沿う断面を示している。又、図1(b)では、便宜上、配線層12を梨地模様で示している。
次に、第1の実施の形態に係る半導体装置の製造方法について説明する。図2〜図6は、第1の実施の形態に係る半導体装置の製造工程を例示する図である。
第1の実施の形態の変形例1では、配線層12の上面に選択的に表面処理膜を設け、はんだ40と配線層12との間に表面処理膜を介在させる例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
10、10A 配線基板
11 絶縁層
11x、340x 開口部
12 配線層
13、15 表面処理膜
20 半導体チップ
30 バンプ
40 はんだ
50 アンダーフィル樹脂
60 モールド樹脂
90 はんだバンプ
300 支持体
310 プリプレグ
320 金属箔
321 薄箔
322 厚箔
340 レジスト層
400 接着層
410 第2支持体
Claims (9)
- 単層の絶縁層と、
前記絶縁層に埋め込まれた銅からなる単層の配線層と、を有し、
前記配線層の一方の面の全面をなす銅の表面が、前記絶縁層の一方の面から窪んだ位置に露出しており、
前記配線層の他方の面は、前記絶縁層の他方の面から窪んだ位置に部分的に露出しており、
前記銅の表面の一部が、半導体チップと接続するための接続パッドとして機能する配線基板。 - 単層の絶縁層と、
前記絶縁層に埋め込まれた単層の配線層と、を有し、
前記配線層の一方の面の全面は、前記絶縁層の一方の面から窪んだ位置に露出しており、
前記配線層の他方の面は、前記絶縁層の他方の面から窪んだ位置に部分的に露出しており、
前記配線層の一方の面は、表面処理膜が形成されている部分と、表面処理膜が形成されていない部分と、を有しており、
前記表面処理膜が、前記配線層の一方の面の前記表面処理膜が形成されていない部分に対して前記絶縁層の一方の面側に突起しており、
前記表面処理膜の全体が前記絶縁層の一方の面から窪んだ位置にある配線基板。 - 前記配線層の一方の面側が電子部品搭載面であり、他方の面側が外部接続端子形成面である請求項1又は2に記載の配線基板。
- 前記絶縁層の他方の面側には支持体が形成されており、
前記支持体は、前記絶縁層の他方の面、及び前記絶縁層の他方の面から窪んだ前記配線層の他方の面を覆うように配置されている請求項1乃至3の何れか一項に記載の配線基板。 - 単層の絶縁層と、前記絶縁層に埋め込まれた銅からなる単層の配線層と、を有し、前記配線層の一方の面の全面をなす銅の表面が、前記絶縁層の一方の面から窪んだ位置に露出しており、前記配線層の他方の面は、前記絶縁層の他方の面から窪んだ位置に部分的に露出しており、前記銅の表面の一部が、半導体チップと接続するための接続パッドとして機能する配線基板と、
前記絶縁層の一方の面側に実装された半導体チップと、を有し、
前記半導体チップは、はんだを介して、前記配線層の一方の面と接続されている半導体装置。 - 単層の絶縁層と、前記絶縁層に埋め込まれた単層の配線層と、を有し、前記配線層の一方の面の全面は、前記絶縁層の一方の面から窪んだ位置に露出しており、前記配線層の他方の面は、前記絶縁層の他方の面から窪んだ位置に部分的に露出しており、前記配線層の一方の面は、表面処理膜が形成されている第1部分と、表面処理膜が形成されていない第2部分と、を有しており、前記表面処理膜が、前記配線層の一方の面の前記表面処理膜が形成されていない部分に対して前記絶縁層の一方の面側に突起しており、前記表面処理膜の全体が前記絶縁層の一方の面から窪んだ位置にある配線基板と、
前記絶縁層の一方の面側に実装された半導体チップと、を有し、
前記半導体チップは、はんだを介して、前記配線層の一方の面と接続されている半導体装置。 - 前記はんだは、前記第1部分と前記第2部分の両方に連続して設けられており、
前記はんだと前記配線層との間に表面処理膜が介在する請求項6に記載の半導体装置。 - 前記配線基板の一方の面側及び前記半導体チップを被覆する封止樹脂を有している請求項5乃至7の何れか一項に記載の半導体装置。
- 前記配線基板の一方の面側と前記半導体チップとの間を充填するアンダーフィル樹脂を有している請求項5乃至8の何れか一項に記載の半導体装置。
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JP2015244936A JP6623056B2 (ja) | 2015-12-16 | 2015-12-16 | 配線基板、半導体装置 |
US15/367,264 US10109580B2 (en) | 2015-12-16 | 2016-12-02 | Wiring board and semiconductor device |
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