JP6577166B2 - 不揮発性メモリのチャネル制御用システム及びその制御方法 - Google Patents
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Description
Claims (6)
- システムであって、
コマンドインターフェースを介して、コマンドを受け取り、及びレスポンスを送出するように構成された高レベル制御プロセッサと、
前記システムと1以上の不揮発性メモリデバイスとを接続するように構成された不揮発性メモリデバイスインターフェースと、
(i)前記高レベル制御プロセッサと(ii)前記不揮発性メモリデバイスインターフェースとに接続され、コントロールストアを有する低レベルマイクロシーケンサ
を備え、
前記不揮発性メモリデバイスインターフェースは、複数のデータ入出力ピンと複数の制御入出力ピンとを備え、
前記コントロールストアは、前記低レベルマイクロシーケンサによって読み取り可能であり、及び、前記高レベル制御プロセッサによって書き込み可能であり、
前記コマンドのうちの特定のコマンドを受け取ると、
前記高レベル制御プロセッサは、前記特定のコマンドに従って、前記コントロールストア内の位置で前記低レベルマイクロシーケンサに実行を開始させることができ、
前記低レベルマイクロシーケンサは、前記制御入出力ピン及び前記データ入出力ピンの状態を変更して、前記不揮発性メモリデバイスインターフェースに接続された前記1以上の不揮発性メモリデバイスのプロトコルに従って、前記特定のコマンドを実行することができ、
前記コントロールストアは、前記1以上の不揮発性メモリデバイスに関連付けられている1以上のプロトコルを実行するように前記高レベル制御プロセッサによってプログラムされることからなり、
前記高レベル制御プロセッサは、さらに、
まず、前記コントロールストアが複数のタイプの不揮発性メモリデバイスと互換性のある低速プロトコルを実行するように、前記高レベル制御プロセッサが前記コントロールストアをプログラムすることができるように構成され、及び、
その後、前記コントロールストアが前記1以上の不揮発性メモリデバイスと互換性のあるより高速なプロトコルを実行するように、前記高レベル制御プロセッサが前記コントロールストアをプログラムすることができるように構成されることからなる、システム。 - 前記低レベルマイクロシーケンサを介して前記不揮発性メモリデバイスインターフェースに接続された出力データインターフェースであって、出力データバッファを有する出力データインターフェースと、
前記低レベルマイクロシーケンサを介して前記不揮発性メモリデバイスインターフェースに接続された入力データインターフェースであって、入力データバッファを有する入力データインターフェース
をさらに備え、
前記出力データバッファは、前記不揮発性メモリデバイスインターフェースに送られるデータを受け取ることができ、
前記入力データバッファは、前記不揮発性メモリデバイスインターフェースから受け取ったデータを受け取ることができることからなる、請求項1に記載のシステム。 - 前記低レベルマイクロシーケンサは、さらに、(i)前記入力データバッファの全体状態を検出し、及び、(ii)前記全体状態の検出に応じて、前記コントロールストア内の所定の位置にジャンプすることができる、請求項2に記載のシステム。
- 前記システムは、ソリッドステートドライブ(SSD)装置の一部である、請求項1〜3のいずれかに記載のシステム。
- 前記システムは、1以上の集積回路として実施される、請求項1〜3のいずれかに記載のシステム。
- 不揮発性メモリチャネルを制御する方法であって、
高レベル制御プロセッサに接続されたコマンドインターフェースを介して、コマンドを受け取り、及びレスポンスを送出するステップと、
前記高レベル制御プロセッサに接続された低レベルマイクロシーケンサを用いて、コントロールストア内の位置で命令の実行を開始するステップ
を含み、
前記位置は、受け取った前記コマンドのうちの特定のコマンドにしたがって、前記高レベル制御プロセッサにより決定され、
前記低レベルマイクロシーケンサは、不揮発性メモリデバイスインターフェースの制御入出力ピン及びデータ入出力ピンの状態を変更して、前記不揮発性メモリデバイスインターフェースによって前記低レベルマイクロシーケンサに接続された1以上の不揮発性メモリデバイスのプロトコルに従って、前記特定のコマンドを実行し、
前記方法はさらに、前記高レベル制御プロセッサを用いて、前記不揮発性メモリデバイスインターフェースに取付けられた前記1以上の不揮発性メモリデバイスに関連付けられている1以上のプロトコルを実行するように前記コントロールストアをプログラムするステップを含むことからなり、
まず、前記コントロールストアが複数のタイプの不揮発性メモリデバイスと互換性のある低速プロトコルを実行するように、前記高レベル制御プロセッサが前記コントロールストアをプログラムできるようにするステップと、
その後、前記コントロールストアが前記1以上の不揮発性メモリデバイスと互換性のあるより高速なプロトコルを実行するように、前記高レベル制御プロセッサが前記コントロールストアをプログラムできるようにするステップ
をさらに含む、方法。
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US13/768,215 US9081666B2 (en) | 2013-02-15 | 2013-02-15 | Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer |
US13/768,215 | 2013-02-15 |
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JP2014157603A JP2014157603A (ja) | 2014-08-28 |
JP2014157603A5 JP2014157603A5 (ja) | 2017-03-16 |
JP6577166B2 true JP6577166B2 (ja) | 2019-09-18 |
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US (2) | US9081666B2 (ja) |
EP (1) | EP2767899A3 (ja) |
JP (1) | JP6577166B2 (ja) |
KR (1) | KR102170644B1 (ja) |
CN (2) | CN103995686B (ja) |
TW (1) | TWI633433B (ja) |
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2014
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TW201502775A (zh) | 2015-01-16 |
JP2014157603A (ja) | 2014-08-28 |
CN103995686B (zh) | 2019-06-28 |
KR102170644B1 (ko) | 2020-10-27 |
US20140237162A1 (en) | 2014-08-21 |
EP2767899A2 (en) | 2014-08-20 |
TWI633433B (zh) | 2018-08-21 |
US20150268870A1 (en) | 2015-09-24 |
US9081666B2 (en) | 2015-07-14 |
CN110134442A (zh) | 2019-08-16 |
EP2767899A3 (en) | 2016-08-17 |
KR20140103048A (ko) | 2014-08-25 |
CN103995686A (zh) | 2014-08-20 |
US9262084B2 (en) | 2016-02-16 |
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