JP6563390B2 - F−ramの製造方法 - Google Patents
F−ramの製造方法 Download PDFInfo
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- JP6563390B2 JP6563390B2 JP2016523760A JP2016523760A JP6563390B2 JP 6563390 B2 JP6563390 B2 JP 6563390B2 JP 2016523760 A JP2016523760 A JP 2016523760A JP 2016523760 A JP2016523760 A JP 2016523760A JP 6563390 B2 JP6563390 B2 JP 6563390B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本出願は、35U.S.C119(e)に基づいて2013年6月27日に出願された米国仮特許出願第61/839,997号、2013年6月27日に出願された米国仮特許出願第61/840,128号、及び2013年6月28日に出願された米国仮特許出願第61/841,104号の優先権の利益を主張しており、その両出願とも引用することにより本明細書に組み込まれるものとする。
Claims (11)
- 基板の表面上にゲートレベルを形成するステップであって、前記ゲートレベルは、金属酸化膜半導体(MOS)トランジスタのゲートスタック、前記MOSトランジスタの上に位置する第1の誘電体層、及び前記第1の誘電体層を経て該第1の誘電体層の上面から前記基板中の前記MOSトランジスタの拡散領域まで延在している第1のコンタクトを含む、ステップと、
前記第1の誘電体層の上面上及び前記第1のコンタクト上にO 2 障壁を形成するように選択される材料を含むローカルインターコネクト(LI)層を堆積するステップと、
前記LI層上にフェロスタックを堆積するステップであって、前記フェロスタックは、前記LI層に電気的に結合される底部電極、頂部電極、及び前記底部電極と前記頂部電極との間にある強誘電体層を含む、ステップと、
前記LI層上にLIマスクを形成し、前記LI層をエッチングすることにより、前記底部電極下の前記O 2 障壁および前記第1の誘電体層上のLIを同時に形成するステップと、
前記フェロスタックをパターニングして強誘電体キャパシタを形成するステップであって、前記底部電極は前記O2障壁を経て前記MOSトランジスタの前記拡散領域に電気的に結合される、ステップと
を含む、方法。 - 前記強誘電体キャパシタと前記LIを封入層で封入するステップをさらに含む、請求項1に記載の方法。
- 前記封入層は、前記強誘電体キャパシタ及び前記LI上に堆積された酸化アルミニウム(Al2O3)からなる水素(H2)障壁を含む多数の層を含む、請求項2に記載の方法。
- 前記封入層は、前記H2障壁上の窒化ケイ素からなる窒化物層をさらに含む、請求項3に記載の方法。
- 基板の表面上にゲートレベルを形成するステップであって、前記ゲートレベルは金属酸化膜半導体(MOS)トランジスタのゲートスタック、及び前記MOSトランジスタ上に位置する第1の誘電体層を含む、ステップと、
前記ゲートレベルの表面上に、ドープされていないキャップ酸化(NCAPOX)層を堆積する、ステップと、
デュアルダマシンプロセスを用いて、前記NCAPOX層および前記第1の誘電体層をマスクし、エッチングすることにより、ローカルインターコネクト(LI)用のトレンチ及びLIコンタクト用の開口を形成して充填するステップであって、前記LIコンタクトは前記第1の誘電体層を経て前記基板中の前記MOSトランジスタの拡散領域まで延在し、前記LIコンタクトの上層部分は、前記LIと物理的にも電気的にも結合しておらず、前記LIの一部として機能しないとする、ステップと、
頂部電極と底部電極との間に強誘電体層を含む強誘電体キャパシタを形成するステップであって、前記底部電極は、前記LIコンタクト上に位置し、前記LIコンタクトを経て前記MOSトランジスタの前記拡散領域に電気的に結合される、ステップと
を含む、方法。 - 前記強誘電体キャパシタ及び前記LIを封入層で封入するステップをさらに含む、請求項5に記載の方法。
- 前記封入層は、前記強誘電体キャパシタ及び前記LI上に堆積された酸化アルミニウム(Al2O3)からなる水素(H2)障壁を含む多数の層を含む、請求項6に記載の方法。
- 前記封入層は、前記H2障壁上の窒化ケイ素からなる窒化物層をさらに含む、請求項7に記載の方法。
- 前記強誘電体キャパシタを形成する前に前記LI上に酸素(O2)障壁を形成するステップをさらに含む、請求項5に記載の方法。
- 前記LI用の前記トレンチを形成して充填するステップ及び前記LIの頂部に酸素(O2)障壁を形成するために選択された材料の層を堆積するステップを含む、請求項5に記載の方法。
- 前記LI用の前記トレンチ及び前記LIコンタクト用の前記開口を形成して充填するステップは、前記LI用の前記トレンチ及び前記LIコンタクト用の前記開口をタングステン(W)で充填するステップを含む、請求項5に記載の方法。
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361839997P | 2013-06-27 | 2013-06-27 | |
US201361840128P | 2013-06-27 | 2013-06-27 | |
US61/840,128 | 2013-06-27 | ||
US61/839,997 | 2013-06-27 | ||
US201361841104P | 2013-06-28 | 2013-06-28 | |
US61/841,104 | 2013-06-28 | ||
US14/109,045 US9548348B2 (en) | 2013-06-27 | 2013-12-17 | Methods of fabricating an F-RAM |
US14/109,045 | 2013-12-17 | ||
PCT/US2014/040886 WO2014209559A1 (en) | 2013-06-27 | 2014-06-04 | Methods of fabricating an f-ram |
Publications (2)
Publication Number | Publication Date |
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JP2016526798A JP2016526798A (ja) | 2016-09-05 |
JP6563390B2 true JP6563390B2 (ja) | 2019-08-21 |
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JP2016523760A Active JP6563390B2 (ja) | 2013-06-27 | 2014-06-04 | F−ramの製造方法 |
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US (1) | US9548348B2 (ja) |
JP (1) | JP6563390B2 (ja) |
CN (2) | CN105308737A (ja) |
TW (1) | TWI635578B (ja) |
WO (1) | WO2014209559A1 (ja) |
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US11004867B2 (en) * | 2018-06-28 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded ferroelectric memory in high-k first technology |
US20210305356A1 (en) * | 2020-03-26 | 2021-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for metal insulator metal capacitors |
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CN113421882A (zh) * | 2021-06-21 | 2021-09-21 | 无锡拍字节科技有限公司 | 一种铁电存储器及其制造方法 |
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-
2013
- 2013-12-17 US US14/109,045 patent/US9548348B2/en active Active
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2014
- 2014-06-04 CN CN201480034108.0A patent/CN105308737A/zh active Pending
- 2014-06-04 JP JP2016523760A patent/JP6563390B2/ja active Active
- 2014-06-04 CN CN202010439894.XA patent/CN111785722A/zh active Pending
- 2014-06-04 WO PCT/US2014/040886 patent/WO2014209559A1/en active Application Filing
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CN105308737A (zh) | 2016-02-03 |
TWI635578B (zh) | 2018-09-11 |
US9548348B2 (en) | 2017-01-17 |
JP2016526798A (ja) | 2016-09-05 |
CN111785722A (zh) | 2020-10-16 |
US20150004718A1 (en) | 2015-01-01 |
TW201523795A (zh) | 2015-06-16 |
WO2014209559A1 (en) | 2014-12-31 |
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