JP6504962B2 - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
- Publication number
- JP6504962B2 JP6504962B2 JP2015154098A JP2015154098A JP6504962B2 JP 6504962 B2 JP6504962 B2 JP 6504962B2 JP 2015154098 A JP2015154098 A JP 2015154098A JP 2015154098 A JP2015154098 A JP 2015154098A JP 6504962 B2 JP6504962 B2 JP 6504962B2
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor device
- intermediate plate
- fixing surface
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 79
- 239000000758 substrate Substances 0.000 claims description 59
- 239000000463 material Substances 0.000 claims description 46
- 229910000679 solder Inorganic materials 0.000 claims description 44
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 26
- 239000004020 conductor Substances 0.000 description 26
- 230000000694 effects Effects 0.000 description 22
- 229920005989 resin Polymers 0.000 description 20
- 239000011347 resin Substances 0.000 description 20
- 239000011800 void material Substances 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 238000007789 sealing Methods 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 12
- 238000004382 potting Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229920000106 Liquid crystal polymer Polymers 0.000 description 4
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000011858 nanopowder Substances 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 239000013585 weight reducing agent Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- -1 Kovar or 42 alloy Chemical class 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000002105 nanoparticle Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000009849 vacuum degassing Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
本発明は、発電・送電から効率的なエネルギーの利用・再生まであらゆる場面で利用される電力用半導体装置に関する。 The present invention relates to a power semiconductor device used in all situations from power generation / transmission to efficient energy utilization / regeneration.
産業機器から家電・情報端末まであらゆる製品にパワーモジュール（電力用半導体装置）が普及しつつあり、自動車や電鉄など輸送機器に搭載されるモジュールについては、高い信頼性が求められ、小型化を実現するために高い放熱性が求められる。また、動作温度が高く、効率に優れている点で、今後の主流となる可能性の高いＳｉＣ半導体などワイドバンドギャップ半導体に適用できるパッケージ形態であることも同時に求められている。 Power modules (power semiconductor devices) are spreading to all products from industrial equipment to home appliances and information terminals, and high reliability is required for modules mounted on transportation equipment such as automobiles and railways, achieving miniaturization In order to do so, high heat dissipation is required. At the same time, it is also required to be a package form that can be applied to wide band gap semiconductors such as SiC semiconductors that are likely to become mainstream in the future, in terms of high operating temperature and excellent efficiency.
電力用半導体装置は、高電圧・大電流を扱うために発熱が大きく、効率的に排熱する目的で熱伝導率に優れたセラミック基板を絶縁基板として用いる場合が多い。セラミック基板はアルミナやＡｌＮ等の基材に、導体層を両面に張り付ける構造となっており、自動車など輸送機器に用いるパワーモジュールとしては、軽量化のためにアルミ導体層を用いることが多い。しかし、アルミは200℃前後で再結晶を生じるため、高温動作を行うことでアルミ結晶の粗大化や粒界の割れなどが生じやすいという問題がある。このアルミの熱変形によってダイボンド部のはんだにボイドを生じさせたり、電力用半導体素子自体の変形や割れを起こす可能性があった。 A power semiconductor device generates a large amount of heat to handle a high voltage and a large current, and often uses a ceramic substrate excellent in thermal conductivity as an insulating substrate for the purpose of efficiently discharging heat. The ceramic substrate has a structure in which a conductor layer is attached to both sides of a base material such as alumina or AlN, and an aluminum conductor layer is often used for weight reduction as a power module used for transportation equipment such as automobiles. However, since aluminum causes recrystallization at around 200 ° C., there is a problem that coarsening of the aluminum crystal and cracking of grain boundaries are likely to occur by high temperature operation. The thermal deformation of the aluminum may cause voids in the solder of the die bonding portion, or may cause deformation or cracking of the power semiconductor element itself.
特許文献１には、突起を有する中間板を電力用半導体素子のダイボンド部のはんだに埋め込み、ダイボンド部のはんだの厚さを確保し、熱応力に伴う電力用半導体素子への影響を抑制しようとする手法が提案されている。 In Patent Document 1, an intermediate plate having a protrusion is embedded in the solder of the die bonding portion of the power semiconductor device to secure the thickness of the solder of the die bonding portion to suppress the influence on the power semiconductor device due to the thermal stress. Methods have been proposed.
特許文献１に記載された方法によると、突起を有する中間板を挟み込むことで、アルミ導体層の熱変形の影響を抑制することが可能であるが、はんだ付けの際に生じる気泡が抜けにくくなってボイドとして残存し、熱抵抗となって熱暴走する可能性があった。 According to the method described in Patent Document 1, it is possible to suppress the influence of thermal deformation of the aluminum conductor layer by sandwiching the intermediate plate having the projections, but it becomes difficult for air bubbles generated during soldering to come off As a result, it remains as a void, which may cause thermal runaway due to thermal resistance.
この発明は、上記のような問題点を解決するためになされたものであり、はんだなど接合材中に残存するボイドが抑制された電力用半導体装置を得ることを目的としている。 The present invention has been made to solve the above-described problems, and it is an object of the present invention to obtain a power semiconductor device in which voids remaining in a bonding material such as solder are suppressed.
本発明は、半導体素子の一面である素子固着面が基板の一面である基板固着面に接合材により固着された電力用半導体装置において、接合材中に、基板固着面に対向する面が基板固着面に対して傾斜し、素子固着面に対向する面が素子固着面に対して傾斜した中間板が挿入されているようにした。 The present invention relates to a power semiconductor device in which an element fixing surface which is one surface of a semiconductor element is fixed to a substrate fixing surface which is one surface of a substrate by a bonding material. The intermediate plate is inserted such that the intermediate plate is inclined with respect to the surface and the surface facing the element fixing surface is inclined with respect to the element fixing surface.
この発明によれば、傾斜した中間板を挿入することで、中間板の上下の接合材層の厚さが外周に向かって徐々に厚くなるようになり、接合材中に発生した気泡が排出されやすくなり、ボイドの発生を抑制できる。 According to the present invention, by inserting the inclined intermediate plate, the thickness of the upper and lower bonding material layers of the intermediate plate becomes gradually thicker toward the outer periphery, and the air bubbles generated in the bonding material are discharged. It becomes easy and can suppress generation | occurrence | production of a void.
実施の形態１．
図１は本発明の実施の形態１による電力用半導体装置の構成を示す側面断面図、図２は後述のダイレクトポッティング封止樹脂を取り去って示す上面図である。表面に回路導体層１３、裏面に裏面導体層１２（いずれもアルミニウム、パターン厚さ０．４ｍｍ）が形成された基板１１（ＡｌＮ製、40mm×25mm×厚さ0.635mm、以降セラミック基板１１とも称する。）の回路導体層１３に、電力用半導体素子としてダイオード２１（15mm×15mm×厚さ0.3mm）とＩＧＢＴ（Insulated Gate Bipolar Transistor）２２がダイボンド部３１によって接合されている。回路導体層１３の、電力用半導体素子が固着される面を基板固着面と称する。また、電力用半導体素子の、回路導体層１３と接合される面を素子固着面と称する。ダイボンド部３１は接合材であるはんだに中間板９０が挿入された構成となっている。セラミック基板１１にはケース５１（ＰＰＳ樹脂製、48mm×28mm×高さ12mm）が接着剤８（シリコーン製）を用いて固定されており、ケース５１内部はダイレクトポッティング封止樹脂７により全体が封止されている。
Embodiment 1
FIG. 1 is a side sectional view showing a configuration of a power semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a top view showing a direct potting sealing resin to be described later. Substrate 11 (made of AlN, 40 mm x 25 mm x thickness 0.635 mm, hereinafter also referred to as ceramic substrate 11) on which circuit conductor layer 13 is formed on the front surface and back surface conductor layer 12 (both aluminum and pattern thickness 0.4 mm) is formed on the rear surface. A diode 21 (15 mm × 15 mm × 0.3 mm thickness) and an IGBT (Insulated Gate Bipolar Transistor) 22 are bonded to the circuit conductor layer 13 of the circuit conductor layer 13 by a die bonding portion 31. The surface of the circuit conductor layer 13 to which the power semiconductor element is fixed is referred to as a substrate fixing surface. Further, the surface of the power semiconductor element to be bonded to the circuit conductor layer 13 is referred to as an element fixing surface. The die bonding portion 31 has a configuration in which an intermediate plate 90 is inserted into solder which is a bonding material. A case 51 (made of PPS resin, 48 mm × 28 mm × 12 mm high) is fixed to the ceramic substrate 11 using an adhesive 8 (made of silicone), and the inside of the case 51 is entirely sealed with a direct potting sealing resin 7 It has been stopped.
ケース５１には、外部への接続のための主端子（ケース上部のネジ止め端子部分の幅は１０ｍｍ）が２個配置され、一方の主端子６１の先端はケース中でセラミック基板１１から２ｍｍ程度浮いており、ダイオードの主回路電極２１１およびＩＧＢＴの主回路電極２２１（ソース電極）とはんだ３２で接続される。他方の主端子であるネジ止め端子６１２はセラミック基板１１の回路導体層１３に直接はんだ付けされ、ＩＧＢＴ２２のドレイン電極と接続される。ケース５１に設けられた信号端子６２（幅1.5mm）は、ＩＧＢＴ２２の制御電極２２２（ゲート電極、温度センサー電極など）と、ワイヤ４で接続される。 In the case 51, two main terminals for connection to the outside (the width of the screw terminal portion at the top of the case is 10 mm) are arranged, and the tip of one main terminal 61 is about 2 mm from the ceramic substrate 11 in the case. It floats and is connected to the main circuit electrode 211 of the diode and the main circuit electrode 221 (source electrode) of the IGBT by the solder 32. The screw terminal 612, which is the other main terminal, is directly soldered to the circuit conductor layer 13 of the ceramic substrate 11 and connected to the drain electrode of the IGBT 22. The signal terminal 62 (width 1.5 mm) provided in the case 51 is connected to the control electrode 222 (gate electrode, temperature sensor electrode, etc.) of the IGBT 22 by the wire 4.
図３および図４は本発明の実施の形態１による中間板９０の概念図である。図３は断面図であり、図４は上面図である。図３および図４に示すように、中間板９０は銅製の板材（無酸素銅C1020、15mm×15mm×0.2mm）であり、プレス加工によって突起９１および９２が形成されている。上面突起９１は高さが0.2mmの９１Ｈと、高さが0.1mmの９１Ｌとからなり、右側に９１Ｈが並び、左側に９１Ｌが並んでいる。逆に下面突起９２は、左側に高さが0.2mmの９２Ｈが並び、右側に高さ0.1mmの９２Ｌが並んでいる。このように片面に高さが異なる複数の突起が形成され、他面にも高さが異なる複数の突起が形成された中間板９０が、電力用半導体素子であるダイオード２１やＩＧＢＴ２２の主回路電極とセラミック基板１１とを接合する接合材中に挿入されることにより、中間板９０は、セラミック基板１１の基板固着面や電力用半導体素子の素子固着面に対して傾斜して設置されることになる。 3 and 4 are conceptual views of the intermediate plate 90 according to Embodiment 1 of the present invention. FIG. 3 is a cross-sectional view, and FIG. 4 is a top view. As shown in FIGS. 3 and 4, the intermediate plate 90 is a copper plate material (oxygen-free copper C1020, 15 mm × 15 mm × 0.2 mm), and the protrusions 91 and 92 are formed by pressing. The upper surface projection 91 is composed of 91H having a height of 0.2 mm and 91 L having a height of 0.1 mm, 91H being arranged on the right side and 91L being arranged on the left side. On the other hand, in the lower surface protrusion 92, 92H having a height of 0.2 mm is arranged on the left side, and 92L having a height of 0.1 mm is arranged on the right side. As described above, the intermediate plate 90 having a plurality of projections of different heights formed on one side and a plurality of projections of different heights formed on the other side is the main circuit electrode of the diode 21 or IGBT 22 which is a power semiconductor element. The intermediate plate 90 is installed obliquely to the substrate fixing surface of the ceramic substrate 11 and the element fixing surface of the power semiconductor element by being inserted into the bonding material for bonding the electrode and the ceramic substrate 11. Become.
図５〜９は実施の形態１によるパワーモジュールのプロセスを説明する図である。図５に示すように、セラミック基板１１（ＡｌＮ製、40mm×25mm×厚さ0.635m、裏面導体層１２および回路導体層１３のパターン厚さ0.4mm）上に、ダイオード２１（15mm×15mm×厚さ0.3mm）と、ＩＧＢＴ（Insulated Gate Bipolar Transistor）２２がはんだによって搭載される。その際、厚さ0.15ｍｍのはんだ３０を２枚用い、中間板９０を挟むようにして搭載し、リフロー炉を用いてはんだ付けすることで図６に示すように、はんだダイボンド部３１を形成する。このようにして、はんだダイボンド部３１は、接合材であるはんだ中に中間板９０が、基板固着面に対向する面が基板固着面に対して傾斜し、素子固着面に対向する面が素子固着面に対して傾斜して挿入された構成となる。 5-9 is a figure explaining the process of the power module by Embodiment 1. FIG. As shown in FIG. 5, a diode 21 (15 mm × 15 mm × thickness) is formed on a ceramic substrate 11 (made of AlN, 40 mm × 25 mm × 0.635 m thickness, 0.4 mm thick for the back surface conductor layer 12 and the circuit conductor layer 13). And an IGBT (Insulated Gate Bipolar Transistor) 22 is mounted by soldering. At this time, two pieces of solder 30 having a thickness of 0.15 mm are mounted on both sides of the intermediate plate 90 and soldered using a reflow furnace to form a solder die bonding portion 31 as shown in FIG. In this manner, in the solder die bond portion 31, in the solder which is the bonding material, the surface facing the substrate fixing surface of the intermediate plate 90 is inclined to the substrate fixing surface, and the surface facing the element fixing surface is device fixing The structure is inserted at an angle to the surface.
次に図７に示すように、ケース５１（ＰＰＳ樹脂製、48mm×28mm×高さ12mm）を接着剤８（シリコーン製）を用いてセラミック基板１１に固定し、隙間を埋めることでダイレクトポッティング封止樹脂７の漏れを防止している。図８に示すように、ケース５１にはネジ止め端子６１１がケース外周部に形成された主端子６１がインサートモールドされており、ダイオード２１やＩＧＢＴ２２など電力用半導体素子のソース電極およびドレイン電極といった大電流が流れる電極とはんだ３２で接続される。また、ケースに形成された信号端子６２には、ＩＧＢＴ２２のゲート電極や温度センサー電極などと、ワイヤ（アルミ製φ0.15ｍｍ）４でそれぞれ電気的に接続される。最後に図９に示すように、ダイレクトポッティング封止樹脂７を６０℃に加熱した状態で流し込み、真空脱泡して加熱（１００℃、１．５時間→１４０℃、１．５時間）して硬化させて封止を完了し、パワーモジュールが完成する。 Next, as shown in FIG. 7, the case 51 (made of PPS resin, 48 mm × 28 mm × 12 mm in height) is fixed to the ceramic substrate 11 using the adhesive 8 (made of silicone), and the gap is filled to seal the direct potting seal. Leakage of the stop resin 7 is prevented. As shown in FIG. 8, a main terminal 61 having a screw terminal 611 formed on the outer periphery of the case is insert molded in the case 51, and is used as a source electrode and a drain electrode of a power semiconductor device such as a diode 21 or IGBT 22. It is connected by a solder 32 to an electrode through which current flows. Further, the signal electrode 62 formed in the case is electrically connected to the gate electrode of the IGBT 22, temperature sensor electrode, etc. by a wire (φ 0.15 mm made of aluminum) 4 respectively. Finally, as shown in FIG. 9, direct potting sealing resin 7 is poured in a heated state at 60 ° C., vacuum degassing and heating (100 ° C., 1.5 hours → 140 ° C., 1.5 hours) It is cured to complete the sealing, and the power module is completed.
図６に示すように、中間板９０は、高さの異なる突起の効果によって傾斜をもってはんだダイボンド部３１中に存在している。電力用半導体素子と中間板の間のはんだは、図６においては、左の方が薄く、右の方が厚い。一方、中間板とセラミック基板の間のはんだについては、左の方が厚く、右の方が薄い。このように、はんだの厚さが連続的に変化していて、かつ厚い方が外部に接している状態においては、はんだ中に発生した気泡が外部に排出されやすいと考えられる。 As shown in FIG. 6, the intermediate plate 90 is present in the solder die bond portion 31 with a slope due to the effect of the protrusions having different heights. In FIG. 6, the solder between the power semiconductor element and the middle plate is thinner on the left and thicker on the right. On the other hand, the solder between the middle plate and the ceramic substrate is thicker on the left and thinner on the right. As described above, it is considered that when the thickness of the solder is continuously changing and the thicker one is in contact with the outside, air bubbles generated in the solder are easily discharged to the outside.
排出機構、すなわち、はんだ中のボイドの移動原理について説明する。文献”水平の狭い矩形流路内の気泡挙動に関する実験”（日本機械学会論文集(Ｂ編)、 ｖｏｌ．６１, Ｎｏ．５８１、１９９５、ｐｐ．２０１-２０７）によれば、平板間に挟まれた液体中の気体は、表面張力の働きにより液体の断面積の大きな方へ移動するとある。図１０は、厚さが変化するはんだ中のボイドの挙動を示す図であり、中間板９０とセラミック基板１１の回路導体層１３との間のはんだ３０を示す。はんだ３０は、厚さが右から左に漸増的に大きくなっており、はんだや電力用半導体素子のメタライズ層から気化成分が出てボイドが発生して複数のボイドがつながって大きくなると、中間板９０と回路導体層１３に挟まれてボイド３９０は扁平した形状となる。やがてボイド３９０は、表面積の小さな球に近い形状を取ることができるように、はんだ厚さの大きい方へ移動して、球形に近いボイド３９１となる。ボイド３９１は複数個集まるとやがて扁平した形状となり、やがて移動する。それを繰り返してボイドが外部に排出されることによって、ボイドの低減が可能となる。この際、減圧リフロー炉を用いることで、復圧時にボイドが小さくなることはもちろん、減圧時にボイドが大きくなることで上記の移動が容易となる。電力用半導体素子と中間板９０の間では左右が逆転するものの同じことが起こり、ボイドは右側へ排出されることとなる。 The discharge mechanism, that is, the movement principle of the void in the solder will be described. According to the literature “Experiment on bubble behavior in a horizontal narrow rectangular flow path” (The Proceedings of the Japan Society of Mechanical Engineers, Volume B, vol. 61, No. 581, 1995, pp. 201-207) The gas in the liquid may move to the larger cross section of the liquid by the action of surface tension. FIG. 10 is a diagram showing the behavior of voids in the solder of varying thickness, showing the solder 30 between the intermediate plate 90 and the circuit conductor layer 13 of the ceramic substrate 11. The solder 30 has a thickness gradually increasing from the right to the left, and when the vaporization component is released from the solder or the metallized layer of the power semiconductor element, a void is generated and a plurality of voids are connected to increase the intermediate plate The void 390 has a flat shape by being sandwiched between 90 and the circuit conductor layer 13. Eventually, the void 390 moves to a larger solder thickness to become a near spherical void 391 so that it can be shaped close to a small surface area sphere. When a plurality of voids 391 gather, they become flat in the end and eventually move. It is possible to reduce the void by repeatedly discharging the void to the outside. At this time, by using the reduced pressure reflow furnace, not only the void becomes smaller at the time of pressure recovery but also the above movement becomes easy because the void becomes larger at the time of pressure reduction. The same thing happens between the power semiconductor element and the intermediate plate 90, although the right and left are reversed, and the void is discharged to the right.
ここでは中間板９０として銅を用いたが、基板固着面である回路導体層１３の材料がアルミニウムの場合、アルミニウムより融点が高く、硬度が高く、はんだぬれ性が確保できれば、ニッケルや鉄などの金属、あるいはコバールや４２アロイなどの合金、またはニッケル金めっきを施したチタンやセラミック板でも同様の効果が得られる。回路導体層１３の材料が銅の場合は、中間板９０の材料として、より融点が高く、硬度が高い材料を用いることでさらなる耐熱性の改善が可能であるが、回路導体層１３と同じ銅であってもボイドを低減する効果は得られる。また、基板固着面と半導体素子との間で生じる熱応力が小さくなるよう、中間板９０の線膨張係数は、基板固着面の材料よりも小さい線膨張係数を有する材料が好ましい。 Here, copper is used as the intermediate plate 90, but when the material of the circuit conductor layer 13 which is the substrate fixing surface is aluminum, the melting point is higher than that of aluminum, the hardness is high, and solderability can be ensured. The same effect can be obtained with metals, alloys such as Kovar or 42 alloy, or titanium and ceramic plates plated with nickel and gold. When the material of the circuit conductor layer 13 is copper, the heat resistance can be further improved by using a material having a higher melting point and a higher hardness as the material of the intermediate plate 90, but the same copper as the circuit conductor layer 13 Even in the case, the effect of reducing the void can be obtained. Further, in order to reduce the thermal stress generated between the substrate fixing surface and the semiconductor element, the linear expansion coefficient of the intermediate plate 90 is preferably a material having a smaller linear expansion coefficient than the material of the substrate fixing surface.
突起９１、突起９２の形成方法は、プレス加工に限らず、ワイヤボンドによって突起を形成したり、中間板の一部を折り曲げるなどして突起を形成しても同様の効果が得られる。 The method of forming the projections 91 and the projections 92 is not limited to the press processing, and the same effect can be obtained even if the projections are formed by forming the projections by wire bonding or bending a part of the intermediate plate.
セラミック基板の材料は、ＡｌＮに限らず、アルミナやＳｉＮなどのセラミック材料であっても同様の効果が得られる。さらに放熱性の必要があまりない場合には、ガラスエポキシ基板などを用いることも可能である。また、基板として、ベース板とセラミック基板の機能を併せ持つ金属基板を用いることで部品点数の削減が可能となり、軽量化や小型化が可能となる。ケースの材料はＰＰＳに限らず、ＬＣＰ（液晶ポリマー）などを用いることができる。また、ダイオードとＩＧＢＴが１対の１ｉｎ１でのモジュール構成のものを示したが、２対の２ｉｎ１や６対の６ｉｎ１であっても、主端子となる金属板上に信号端子を配置することで同様の効果が得られる。また、銅板の主端子６１を用いて電力用半導体素子との間をはんだを用いて接続するものを示したが、ワイヤボンドによってネジ止め端子６１１と電力用半導体素子間を接続しても同様の効果が得られる。また、ここではアルミ製のワイヤボンドを用いたが、銅製ワイヤやアルミ被覆銅ワイヤ、または金ワイヤを用いても同様の効果が得られる。また、リボンボンドを用いたり、金属板を超音波接合するバスバーなどを用いても同様の効果が得られる。また、ダイレクトポッティング封止樹脂については、流し込んで常温硬化させる種類のものでも同様の効果が得られる。例えば、シリコンゲルやエポキシ樹脂等を用いることができる。 The material of the ceramic substrate is not limited to AlN, and the same effect can be obtained with ceramic materials such as alumina and SiN. Furthermore, when heat dissipation is not required to a large extent, it is also possible to use a glass epoxy substrate or the like. In addition, by using a metal substrate having both functions of a base plate and a ceramic substrate as the substrate, the number of parts can be reduced, and weight reduction and miniaturization can be achieved. The material of the case is not limited to PPS, and LCP (liquid crystal polymer) or the like can be used. In addition, although the diode and IGBT have been shown to have a module configuration with one pair of 1 in 1, even if there are two pairs of 2 in 1 and 6 pairs of 6 in 1, by arranging the signal terminal on the metal plate to be the main terminal The same effect is obtained. In addition, although the main terminal 61 of the copper plate is used to connect to the power semiconductor element using solder, the same is true even if the screw terminal 611 and the power semiconductor element are connected by wire bonding. An effect is obtained. Further, although a wire bond made of aluminum is used here, the same effect can be obtained by using a copper wire, an aluminum-coated copper wire, or a gold wire. The same effect can be obtained by using a ribbon bond or by using a bus bar or the like for ultrasonically bonding a metal plate. Further, as to the direct potting sealing resin, the same effect can be obtained even if it is of a type in which it is poured and cured at room temperature. For example, silicone gel or epoxy resin can be used.
以上では、電力用半導体素子とセラミック基板の接続を行う接合材としてはんだを用いたものを説明したが、Ａｇフィラーをエポキシ樹脂に分散させた導電性接着剤や、ナノ粒子を低温焼成させるＡｇナノパウダやＣｕナノパウダなどを用いた場合でも、ボイドが生じた場合にはんだと同様の効果が期待できる。 In the above, although the thing using solder as a joining material which connects a semiconductor element for electric power and a ceramic substrate was explained, the conductive adhesive which made Ag filler disperse in an epoxy resin, and Ag nano powder which carries out low temperature baking of nanoparticles. Even in the case of using Cu nanopowder or the like, the same effect as that of the solder can be expected when a void occurs.
実施の形態２．
図１１〜図１４は実施の形態２による電力用半導体装置の中間板の構成を示す概念図である。図１１は斜視図であり、図１２は上面図である。図１１、図１２に示すように、中間板９５は銅製の板材（無酸素銅C1020、15mm×15mm×0.2mm）であり、プレス加工によって山折（対角線）と谷折（各辺の中心を結ぶ）が４５度毎に交互に形成されている。山折と谷折は交互に形成する必要があるが、必ずしも４５度毎に形成する必要は無く、例えば３０度毎にするなど、山折と谷折の数を４つよりも多く形成しても良い。
Second Embodiment
11 to 14 are conceptual diagrams showing the configuration of the intermediate plate of the power semiconductor device according to the second embodiment. FIG. 11 is a perspective view, and FIG. 12 is a top view. As shown in FIGS. 11 and 12, the intermediate plate 95 is a copper plate material (oxygen-free copper C1020, 15 mm × 15 mm × 0.2 mm), and is pressed to connect the center of the mountain fold (diagonal) and valley fold (each side) ) Are alternately formed every 45 degrees. Mountain folds and valley folds need to be formed alternately, but they need not necessarily be formed every 45 degrees; for example, they may be formed more than four, such as every 30 degrees .
図１３、図１４は実施の形態２によるパワーモジュールのはんだダイボンド部の拡大図である。図１３は、図１２のＣ−Ｃ断面を示し、図１４はＤ−Ｄ断面を示す。図１１〜図１４に示すように、本実施の形態２による中間板９５は、板材の中央部から周辺部に向かって放射状に山折と谷折が交互に形成されて、基板固着面に対して傾斜した複数の平面を有する形状となっている。また、図１３、図１４に示すように、本実施の形態２の中間板９５も、実施の形態１の中間板９０と同様、基板固着面に対向する面が基板固着面に対して傾斜し、素子固着面に対向する面が素子固着面に対して傾斜するよう接合材中に挿入されることになる。 13 and 14 are enlarged views of a solder die bonding portion of the power module according to the second embodiment. 13 shows a C-C cross section of FIG. 12, and FIG. 14 shows a D-D cross section. As shown in FIGS. 11 to 14, in the intermediate plate 95 according to the second embodiment, mountain folds and valley folds are alternately formed radially from the central portion to the peripheral portion of the plate material, and It has a shape having a plurality of inclined planes. Further, as shown in FIGS. 13 and 14, in the intermediate plate 95 of the second embodiment, as in the intermediate plate 90 of the first embodiment, the surface facing the substrate fixing surface is inclined relative to the substrate fixing surface. The element is inserted into the bonding material so that the surface facing the element fixing surface is inclined with respect to the element fixing surface.
図１３の断面において、電力用半導体素子２１と中間板９５の間に発生した気泡は、はんだ厚さの大きな外周部に移動して排出される。一方、中間板９５とセラミック基板１１の間に発生した気泡は一旦中央に集まってくるが、図１４の断面に示すように４５度回転した断面では中間板９５とセラミック基板１１の間は外周部の方がはんだ厚さが大きいため、中央に集まった気泡はほどなく外部に排出される。つまり、中間板の上下のはんだ層において発生した気泡は、いずれかの経路で外部に排出されることとなる。わずかに小さな気泡が、中間板の下部の中心に残る可能性はあるが、発熱元である電力用半導体素子２１表面からは離れているため、熱抵抗としてはほとんど無視できると考えられる。 In the cross section of FIG. 13, the air bubbles generated between the power semiconductor element 21 and the intermediate plate 95 move to the outer peripheral portion with a large solder thickness and are discharged. On the other hand, air bubbles generated between the intermediate plate 95 and the ceramic substrate 11 once gather at the center, but in the cross section rotated 45 degrees as shown in the cross section of FIG. Because the thickness of the solder is larger, the bubbles collected in the center are discharged to the outside soon. That is, air bubbles generated in the upper and lower solder layers of the intermediate plate are discharged to the outside through one of the paths. Slightly small air bubbles may remain in the center of the lower part of the intermediate plate, but they are considered to be almost negligible as thermal resistance because they are far from the surface of the power semiconductor element 21 from which heat is generated.
ここでは中間板９５として銅を用いたが、基板固着面である回路導体層１３の材料がアルミニウムの場合、アルミニウムより融点が高く、硬度が高く、はんだぬれ性が確保できれば、ニッケルや鉄などの金属、あるいはコバールや４２アロイなどの合金、またはニッケル金めっきを施したチタンやセラミック板でも同様の効果が得られる。回路導体層１３の材料が銅の場合は、中間板９０の材料として、より融点が高く、硬度が高い材料を用いることでさらなる耐熱性の改善が可能であるが、回路導体層１３と同じ銅であってもボイドを低減する効果は得られる。また、基板固着面と半導体素子との間で生じる熱応力が小さくなるよう、中間板の線膨張係数は、基板固着面の材料よりも小さい線膨張係数を有する材料が好ましい。 Here, copper is used as the intermediate plate 95, but if the material of the circuit conductor layer 13 which is the substrate fixing surface is aluminum, the melting point is higher than that of aluminum, the hardness is high, and solderability can be ensured. The same effect can be obtained with metals, alloys such as Kovar or 42 alloy, or titanium and ceramic plates plated with nickel and gold. When the material of the circuit conductor layer 13 is copper, the heat resistance can be further improved by using a material having a higher melting point and a higher hardness as the material of the intermediate plate 90, but the same copper as the circuit conductor layer 13 Even in the case, the effect of reducing the void can be obtained. Further, in order to reduce the thermal stress generated between the substrate fixing surface and the semiconductor element, it is preferable that the intermediate plate have a linear expansion coefficient smaller than that of the material of the substrate fixing surface.
図１５は実施の形態２による電力用半導体装置の構成を示す断面図である。実施の形態２による電力用半導体装置の製造方法は、実施の形態１による電力用半導体装置の製造方法と同じである。セラミック基板１１（ＡｌＮ製、40mm×25mm×厚さ0.635m、裏面導体層１２および回路導体層１３のパターン厚さ0.4mm）上に、ダイオード２１（15mm×15mm×厚さ0.3mm）と、ＩＧＢＴ２２がはんだによって搭載される。その際、厚さ0.15mmのはんだを２枚用い、中間板９５を挟むようにして搭載し、リフロー炉を用いてはんだ付けすることで、はんだダイボンド部３１を形成する。 FIG. 15 is a cross-sectional view showing the configuration of the power semiconductor device according to the second embodiment. The method of manufacturing the power semiconductor device according to the second embodiment is the same as the method of manufacturing the power semiconductor device according to the first embodiment. A diode 21 (15 mm × 15 mm × 0.3 mm thickness) and an IGBT 22 on a ceramic substrate 11 (AIN 40 mm × 25 mm × 0.635 m thickness, 0.4 mm thick pattern of the back surface conductor layer 12 and the circuit conductor layer 13) Is mounted by solder. At this time, two pieces of solder having a thickness of 0.15 mm are mounted so as to sandwich the intermediate plate 95, and soldered using a reflow furnace to form the solder die bonding portion 31.
次に、ケース５１（ＰＰＳ樹脂製、48mm×28mm×高さ12mm）を接着剤８（シリコーン製）を用いてセラミック基板１１に固定し、隙間を埋めることでダイレクトポッティング封止樹脂７の漏れを防止している。ケース５１には、ネジ止め端子６１１がケース外周部に形成された主端子６１がインサートモールドされており、ダイオード２１やＩＧＢＴ２２などの電力用半導体素子のソース電極およびドレイン電極といった大電流が流れる電極とはんだ３２で接続されている。また、ケース５１に形成された信号端子６２は、ＩＧＢＴのゲート電極や温度センサー電極などと、ワイヤ（アルミ製φ0.15ｍｍ）４でそれぞれ電気的に接続されている。最後に、ダイレクトポッティング封止樹脂７を６０℃に加熱した状態で流し込み、真空脱泡して加熱（１００℃、１．５時間→１４０℃、１．５時間）して硬化させて封止を完了し、パワーモジュールが完成する。 Next, the case 51 (made of PPS resin, 48 mm × 28 mm × 12 mm high) is fixed to the ceramic substrate 11 using the adhesive 8 (made of silicone), and the gap is filled to leak the direct potting sealing resin 7. It is preventing. In the case 51, a main terminal 61 having a screw terminal 611 formed on the outer periphery of the case is insert-molded, and an electrode through which a large current flows such as a source electrode and a drain electrode of a power semiconductor element such as a diode 21 or IGBT 22 It is connected by solder 32. Further, the signal terminal 62 formed in the case 51 is electrically connected to the gate electrode of the IGBT, the temperature sensor electrode, and the like by a wire (φ 0.15 mm made of aluminum) 4. Finally, direct potting sealing resin 7 is poured in a heated state at 60 ° C., vacuum degassing and heating (100 ° C., 1.5 hours → 140 ° C., 1.5 hours) to cure and seal Complete and complete the power module.
セラミック基板の材料は、ＡｌＮに限らず、アルミナやＳｉＮなどのセラミック材料でも同様の効果が得られる。さらに放熱性の必要があまりない場合には、ガラスエポキシ基板などを用いることも可能である。また、基板として、ベース板とセラミック基板の機能を併せ持つ金属基板を用いることで部品点数の削減が可能となり、軽量化や小型化が可能となる。ケースの材料はＰＰＳに限らず、ＬＣＰ（液晶ポリマー）などを用いることができる。また、ダイオードとＩＧＢＴが１対の１ｉｎ１でのモジュール構成を示したが、２対の２ｉｎ１や６対の６ｉｎ１であっても、主端子となる金属板上に信号端子を配置することで同様の効果が得られる。また、銅板の主端子６１を用いて電力用半導体素子との間をはんだを用いて接続したが、ワイヤボンドによってネジ止め端子６１１と電力用半導体素子間を接続しても同様の効果が得られる。また、ここではアルミ製のワイヤボンドを用いたが、銅製ワイヤやアルミ被服銅ワイヤ、または金ワイヤを用いても同様の効果が得られる。また、リボンボンドを用いたり、金属板を超音波接合するバスバーなどを用いても同様の効果が得られる。また、ダイレクトポッティング封止樹脂については、流し込んで常温硬化させる種類のものでも同様の効果が得られる。 The material of the ceramic substrate is not limited to AlN, and the same effect can be obtained with ceramic materials such as alumina and SiN. Furthermore, when heat dissipation is not required to a large extent, it is also possible to use a glass epoxy substrate or the like. In addition, by using a metal substrate having both functions of a base plate and a ceramic substrate as the substrate, the number of parts can be reduced, and weight reduction and miniaturization can be achieved. The material of the case is not limited to PPS, and LCP (liquid crystal polymer) or the like can be used. Also, although the module configuration in which the diode and the IGBT are 1 pair of 1 in 1 is shown, even if it is 2 pairs of 2 in 1 and 6 pairs of 6 in 1, similar signal can be arranged by arranging the signal terminal on the metal plate as the main terminal. An effect is obtained. In addition, although the main terminal 61 of the copper plate is used to connect to the power semiconductor element using solder, the same effect can be obtained by connecting the screw terminal 611 and the power semiconductor element by wire bonding. . Further, although a wire bond made of aluminum is used here, the same effect can be obtained by using a copper wire, an aluminum-coated copper wire, or a gold wire. The same effect can be obtained by using a ribbon bond or by using a bus bar or the like for ultrasonically bonding a metal plate. Further, as to the direct potting sealing resin, the same effect can be obtained even if it is of a type in which it is poured and cured at room temperature.
以上では、電力用半導体素子とセラミック基板の接続を行う接合材にはんだを用いたものを説明したが、Ａｇフィラーをエポキシ樹脂に分散させた導電性接着剤や、ナノ粒子を低温焼成させるＡｇナノパウダやＣｕナノパウダなどを用いた場合でも、ボイドが生じた場合にはんだと同様の効果が期待できる。 In the above, although the thing which used the solder for the joining material which connects the semiconductor element for electric powers and a ceramic substrate was demonstrated, the conductive adhesive which disperse | distributed Ag filler to the epoxy resin, Ag nano powder which carries out low temperature baking of nanoparticles. Even in the case of using Cu nanopowder or the like, the same effect as that of the solder can be expected when a void occurs.
実施の形態３．
図１６は実施の形態３による電力用半導体装置の概略構成を示す断面図である。セラミック基板１１（ＡｌＮ製、40mm×25mm×厚さ0.635mm、裏面導体層１２および回路導体層１３のパターン厚さ0.4mm）上に、ダイオード２１（15mm×15mm×厚さ0.3mm）と、ＩＧＢＴ２２がはんだによって搭載される。その際、厚さ0.15ｍｍのはんだ３０を２枚用い、中間板９０を挟むようにして搭載し、リフロー炉を用いてはんだ付けすることで、はんだダイボンド部３１を形成する。ここで、中間板は実施の形態２で示した中間板９５を用いても良いのは言うまでもない。
Third Embodiment
FIG. 16 is a cross sectional view showing a schematic configuration of the power semiconductor device according to the third embodiment. A diode 21 (15 mm × 15 mm × 0.3 mm thickness) and an IGBT 22 on a ceramic substrate 11 (made of AlN, 40 mm × 25 mm × 0.635 mm thickness, 0.4 mm thickness pattern of the back surface conductor layer 12 and the circuit conductor layer 13) Is mounted by solder. At this time, two pieces of solder 30 having a thickness of 0.15 mm are mounted so as to sandwich the intermediate plate 90, and soldered using a reflow furnace to form the solder die bonding portion 31. Here, it goes without saying that the intermediate plate may be the intermediate plate 95 shown in the second embodiment.
次に、メインリードフレーム６３および信号端子リードフレーム６４がセラミック基板上に位置決めされ、メインリードフレーム６３はダイオード２１やＩＧＢＴ２２など電力用半導体素子のソース電極およびドレイン電極といった大電流が流れる電極とはんだ３２で接続される。また、信号端子リードフレーム６４は、ＩＧＢＴのゲート電極や温度センサー電極などと、ワイヤ（アルミ製φ0.15ｍｍ）４でそれぞれ電気的に接続されている。 Next, the main lead frame 63 and the signal terminal lead frame 64 are positioned on the ceramic substrate, and the main lead frame 63 is an electrode and solder 32 through which a large current flows such as a source electrode and a drain electrode of a power semiconductor element such as a diode 21 or IGBT 22. Connected by Further, the signal terminal lead frame 64 is electrically connected to the gate electrode of the IGBT, the temperature sensor electrode, etc. by the wire (φ 0.15 mm made of aluminum) 4 respectively.
最後に、トランスファモールド封止樹脂７４を金型に流し込み、硬化させて封止を完了し、パワーモジュールが完成する。ここでは封止樹脂としてトランスファモールド樹脂を用いたが、低圧形成用樹脂を用いても同様の効果が得られる。 Finally, transfer mold sealing resin 74 is poured into a mold and cured to complete sealing, and the power module is completed. Although a transfer mold resin is used as the sealing resin here, the same effect can be obtained by using a low pressure forming resin.
以上のように、実施の形態１および実施の形態２で説明した中間板は、ケースを用いず、トランスファモールド封止樹脂や低圧形成用樹脂により絶縁封止した電力用半導体装置に適用することができる。実施の形態１や実施の形態２と同様、接合材中に発生した気泡が排出されやすくなり、ボイドの発生を抑制できるという効果を奏するのは言うまでもない。 As described above, the intermediate plate described in the first and second embodiments may be applied to a power semiconductor device insulated and sealed by a transfer mold sealing resin or a low voltage forming resin without using a case. it can. It goes without saying that the air bubbles generated in the bonding material are easily discharged as in the first embodiment and the second embodiment, and the generation of the void can be suppressed.
なお、本発明は、電力用半導体素子として、例えば高温動作も可能なワイドバンドギャップ半導体材料である炭化珪素（ＳｉＣ）等を用いた電力用半導体素子を実装する電力用半導体装置に適用すると、高い電流密度の回路を形成することができるため特に効果がある。ワイドバンドギャップ半導体材料としては、他に、窒化ガリウム系材料、ダイアモンドなどがある。 The present invention is high when applied to a power semiconductor device for mounting a power semiconductor device using, for example, silicon carbide (SiC), which is a wide band gap semiconductor material capable of high temperature operation, as a power semiconductor device. This is particularly effective because a circuit of current density can be formed. Other wide band gap semiconductor materials include gallium nitride-based materials and diamond.
以上に説明した各実施の形態の構成、動作に限定されることはなく、本発明の範囲内において、各実施の形態を組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。 The present invention is not limited to the configurations and operations of the respective embodiments described above, and the respective embodiments may be combined or the respective embodiments may be appropriately modified or omitted within the scope of the present invention. It is possible.
１１ セラミック基板（基板）、１２ 裏面導体層、１３ 回路導体層、２１ ダイオード（電力用半導体素子）、２２ ＩＧＢＴ（電力用半導体素子）、３０ はんだ、３１ はんだダイボンド部、３２ はんだ接合部、４ アルミワイヤボンド、５１ ケース、６１ 主端子、６１１、６１２ ネジ止め端子、６２ 信号端子、６３ メインリードフレーム、６４ 信号端子リードフレーム、７ ダイレクトポッティング封止樹脂、７４ トランスファモールド封止樹脂、８ 接着剤、９０、９５ 中間板 11 ceramic substrate (substrate), 12 back conductor layer, 13 circuit conductor layer, 21 diode (power semiconductor element), 22 IGBT (power semiconductor element), 30 solder, 31 solder die bond portion, 32 solder joint portion, 4 aluminum Wire bond, 51 case, 61 main terminal, 611, 612 screw terminal, 62 signal terminal, 63 main lead frame, 64 signal terminal lead frame, 7 direct potting sealing resin, 74 transfer mold sealing resin, 8 adhesive, 90, 95 Intermediate plate
Claims (9)
前記接合材中に、片面に複数の異なる高さの突起が形成され、他面にも複数の異なる高さの突起が形成されている中間板が挿入され、前記中間板の前記基板固着面に対向するが面が前記基板固着面に対して傾斜するとともに、前記中間板の前記素子固着面に対向する面が前記素子固着面に対して傾斜していることを特徴とする電力用半導体装置。 In a power semiconductor device in which an element fixing surface which is one surface of a power semiconductor element is fixed to a substrate fixing surface which is one surface of a substrate by a bonding material,
A plurality of projections of different heights are formed on one side of the bonding material, and an intermediate plate having a plurality of projections of different heights formed on the other side is inserted, and the intermediate plate is fixed to the substrate fixing surface A power semiconductor device characterized in that the facing surface is inclined with respect to the substrate fixing surface, and the surface of the intermediate plate facing the element fixing surface is inclined with respect to the element fixing surface.
前記接合材中に、板材の中央部から周辺部に向かって放射状に山折と谷折が交互に形成されて、前記基板固着面に対して傾斜した複数の平面を有する形状の中間板が挿入され、前記中間板の前記基板固着面に対向するが面が前記基板固着面に対して傾斜するとともに、前記中間板の前記素子固着面に対向する面が前記素子固着面に対して傾斜していることを特徴とする電力用半導体装置。 In a power semiconductor device in which an element fixing surface which is one surface of a power semiconductor element is fixed to a substrate fixing surface which is one surface of a substrate by a bonding material,
In the bonding material , mountain folds and valley folds are alternately formed radially from the central portion to the peripheral portion of the plate material, and an intermediate plate having a shape having a plurality of planes inclined with respect to the substrate fixing surface is inserted. A surface of the intermediate plate facing the substrate fixing surface is inclined with respect to the substrate fixing surface, and a surface of the intermediate plate facing the element fixing surface is inclined with respect to the element fixing surface. Power semiconductor device characterized in that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015154098A JP6504962B2 (en) | 2015-08-04 | 2015-08-04 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015154098A JP6504962B2 (en) | 2015-08-04 | 2015-08-04 | Power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017034152A JP2017034152A (en) | 2017-02-09 |
| JP6504962B2 true JP6504962B2 (en) | 2019-04-24 |
Family
ID=57987192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015154098A Active JP6504962B2 (en) | 2015-08-04 | 2015-08-04 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6504962B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111066142B (en) | 2017-08-25 | 2023-08-25 | 三菱电机株式会社 | Power semiconductor device and method for manufacturing power semiconductor device |
| KR102048478B1 (en) | 2018-03-20 | 2019-11-25 | 엘지전자 주식회사 | Power module of double-faced cooling and method for manufacturing thereof |
| US11562979B2 (en) | 2018-06-27 | 2023-01-24 | Mitsubishi Electric Corporation | Power module and method of manufacturing the same, and power conversion apparatus |
| WO2020021642A1 (en) * | 2018-07-24 | 2020-01-30 | 日立化成株式会社 | Circuit-package manufacturing method and circuit package |
| WO2020208739A1 (en) * | 2019-04-10 | 2020-10-15 | 新電元工業株式会社 | Semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2521624Y2 (en) * | 1991-03-07 | 1996-12-25 | 新電元工業株式会社 | Semiconductor device |
| JPH10270614A (en) * | 1997-03-25 | 1998-10-09 | Oki Electric Ind Co Ltd | Heat sink and semiconductor device |
| JPH10322010A (en) * | 1997-05-16 | 1998-12-04 | Toyota Motor Corp | Component bonding method and component used in the method |
| JP2002217364A (en) * | 2001-01-15 | 2002-08-02 | Nissan Motor Co Ltd | Semiconductor mounting structure |
| JP2003031718A (en) * | 2001-07-11 | 2003-01-31 | Mitsubishi Electric Corp | Power semiconductor device |
| JP4594237B2 (en) * | 2003-09-04 | 2010-12-08 | パナソニック株式会社 | Semiconductor device |
| JP2006269848A (en) * | 2005-03-25 | 2006-10-05 | Hitachi Ltd | Semiconductor device |
-
2015
- 2015-08-04 JP JP2015154098A patent/JP6504962B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017034152A (en) | 2017-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5656907B2 (en) | Power module | |
| JP6234630B2 (en) | Power module | |
| JP6504962B2 (en) | Power semiconductor device | |
| JP6120704B2 (en) | Semiconductor device | |
| JP6300633B2 (en) | Power module | |
| JP5863602B2 (en) | Power semiconductor device | |
| JP6265693B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2007311441A (en) | Power semiconductor module | |
| JP6337957B2 (en) | Semiconductor module unit and semiconductor module | |
| JP2016018866A (en) | Power module | |
| JP6287789B2 (en) | Power module and manufacturing method thereof | |
| WO2011040313A1 (en) | Semiconductor module, process for production thereof | |
| JP2016134540A (en) | Power semiconductor device | |
| JP6308780B2 (en) | Power module | |
| JP7196047B2 (en) | ELECTRICAL CIRCUIT, POWER CONVERTER, AND METHOD OF MANUFACTURING ELECTRICAL CIRCUIT | |
| JP6124810B2 (en) | Power module | |
| JP2015130457A (en) | Semiconductor device | |
| JP2012142466A (en) | Semiconductor device | |
| JP6945418B2 (en) | Semiconductor devices and manufacturing methods for semiconductor devices | |
| JP2015115471A (en) | Power semiconductor device | |
| JP6643481B2 (en) | Semiconductor module and method of manufacturing semiconductor module | |
| JP6129090B2 (en) | Power module and method for manufacturing power module | |
| JP6881304B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| JP2013120866A (en) | Semiconductor device | |
| JP2015026667A (en) | Semiconductor module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180322 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20181119 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181127 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181219 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190226 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190326 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 6504962 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |