JP6501044B1 - 半導体装置、及び半導体装置の製造方法 - Google Patents
半導体装置、及び半導体装置の製造方法 Download PDFInfo
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- JP6501044B1 JP6501044B1 JP2018548229A JP2018548229A JP6501044B1 JP 6501044 B1 JP6501044 B1 JP 6501044B1 JP 2018548229 A JP2018548229 A JP 2018548229A JP 2018548229 A JP2018548229 A JP 2018548229A JP 6501044 B1 JP6501044 B1 JP 6501044B1
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- electrode layer
- copper electrode
- thin film
- metal thin
- layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 288
- 239000010949 copper Substances 0.000 claims abstract description 287
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- 239000010936 titanium Substances 0.000 claims description 11
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 8
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- 229910052759 nickel Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
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- 238000002360 preparation method Methods 0.000 claims description 3
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- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
銅電極層上に接して形成され、その外周部よりも内側に銅電極層を露出した開口部を有し、銅電極層の酸化を防止する金属薄膜層と、開口部内にある島状金属薄膜層と、少なくとも開口部を覆い、開口部内の銅電極層の上面および島状金属薄膜層の上面から開口部の周辺の金属薄膜層の上面にかけての接合領域において銅電極層および金属薄膜層と接合する銅を主成分とする配線部材と、を備えた半導体装置。
まず、本発明の実施の形態1の半導体装置100の構成について説明する。
本実施の形態2においては、実施の形態1で用いた銅電極層2と金属薄膜層3の形状において、銅電極層2と金属薄膜層3との膜厚が均一ではなく、銅電極層2とワイヤ4とが接合する部分の金属薄膜層3の膜厚を薄くした点が異なる。このように、ワイヤ4と接合する部分の金属薄膜層3の膜厚を薄くしたので、ワイヤ4と銅電極層2との接合形成時に金属薄膜層3が排斥されやすくなり、良好な接合を形成しやすくなる。なお、その他の点については、実施の形態1と同様であるので、詳しい説明は省略する。
Claims (10)
- 半導体基板と、
前記半導体基板上に形成された銅電極層と、
前記銅電極層上に接して形成され、その外周部よりも内側に前記銅電極層を露出した開口部を有し、前記銅電極層の酸化を防止する金属薄膜層と、
前記開口部内にある島状金属薄膜層と、
少なくとも前記開口部を覆い、前記開口部内の前記銅電極層の上面および前記島状金属薄膜層の上面から前記開口部の周辺の前記金属薄膜層の上面にかけての接合領域において前記銅電極層および前記金属薄膜層と接合する銅を主成分とする配線部材と、
を備えた半導体装置。
- 半導体基板と、
前記半導体基板上に形成された銅電極層と、
前記銅電極層上に接して形成され、その外周部よりも内側に前記銅電極層を露出した開口部を有し、前記銅電極層の酸化を防止する金属薄膜層と、
少なくとも前記開口部を覆い、前記開口部内の前記銅電極層の上面から前記開口部の周辺の前記金属薄膜層の上面にかけての接合領域において前記銅電極層および前記金属薄膜層と接合する銅を主成分とする配線部材と、
を備えた半導体装置。 - 前記金属薄膜層は、2層以上の積層構造である、請求項1または請求項2に記載の半導体装置。
- 前記配線部材は、前記接合領域の前記開口部内で前記銅電極層の複数の凸部と接合している請求項2または請求項3に記載の半導体装置。
- 前記金属薄膜層は、前記接合領域において膜厚の異なる領域を備えた請求項1から請求項4のいずれか1項に記載の半導体装置。
- 前記金属薄膜層の合計の厚さは、1nm以上1000nm未満である請求項1から請求項5のいずれかに1項に記載の半導体装置。
- 前記金属薄膜層は、金、銀、パラジウム、ニッケル、コバルト、クロム、アルミニウム、チタン、窒化チタン、チタン・タングステン合金のいずれかを含む請求項1から請求項6のいずれか1項に記載の半導体装置。
- 前記銅電極層は、無電解めっき、電解めっき、スパッタ、焼結のいずれかで形成された膜である、請求項1から請求項7のいずれか1項に記載の半導体装置。
- 半導体基板を準備する半導体基板準備工程と、
前記半導体基板上に銅電極層を形成する銅電極層形成工程と、
前記銅電極層上に金属薄膜層を形成する金属薄膜層形成工程と、
前記金属薄膜層に開口部を形成し、少なくとも前記開口部を覆い、前記開口部内の前記銅電極層の上面から前記開口部の周辺の前記金属薄膜層の上面にかけての接合領域において前記銅電極層および前記金属薄膜層とする銅を主成分とする配線部材を形成する配線部材接合工程と、
を備えた半導体装置の製造方法。 - 前記銅電極層のおもて面に凹凸を形成する銅電極層加工工程と、を備えた請求項9に記載の半導体装置の製造方法。
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