JP6493161B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP6493161B2
JP6493161B2 JP2015217573A JP2015217573A JP6493161B2 JP 6493161 B2 JP6493161 B2 JP 6493161B2 JP 2015217573 A JP2015217573 A JP 2015217573A JP 2015217573 A JP2015217573 A JP 2015217573A JP 6493161 B2 JP6493161 B2 JP 6493161B2
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layer
semiconductor element
bonding
back electrode
solder
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JP2017092139A (en
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圭児 黒田
圭児 黒田
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は、裏面電極にＮｉ層を有する半導体素子が、Ｚｎ−Ａｌ系はんだを介してリードフレームに接合された半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element having a Ni layer on a back electrode is bonded to a lead frame via a Zn—Al solder.

従来から、裏面電極にＮｉ層を有する半導体素子を、Ｚｎ−Ａｌ系はんだを介してリードフレームに接合した半導体装置の製造方法が提案されている（例えば特許文献１参照）。半導体装置を製造する際には、裏面電極のＮｉ層とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、リフロー接合により半導体素子とリードフレームとを接合する。なお、裏面電極は、半導体素子の表面から順に、Ａｌ−Ｓｉ層、Ｔｉ層、およびＮｉ層が順次積層された層である。   Conventionally, a method of manufacturing a semiconductor device in which a semiconductor element having a Ni layer on a back electrode is joined to a lead frame via a Zn—Al solder has been proposed (see, for example, Patent Document 1). When manufacturing a semiconductor device, Zn—Al based solder is disposed between the Ni layer of the back electrode and the lead frame, and the semiconductor element and the lead frame are joined by reflow bonding. Note that the back electrode is a layer in which an Al—Si layer, a Ti layer, and a Ni layer are sequentially stacked from the surface of the semiconductor element.

これにより、半導体素子の裏面電極と、Ｚｎ−Ａｌ系はんだとの間には、Ｎｉ層とＺｎ−Ａｌ系はんだの成分のＡｌとによりＡｌ−Ｎｉ合金層が生成され、半導体素子とリードフレームとの接合性を高めることができる。   As a result, an Al—Ni alloy layer is generated between the back electrode of the semiconductor element and the Zn—Al based solder by the Ni layer and Al of the component of the Zn—Al based solder. It is possible to improve the bondability.

特開２００５−１８３６５０号公報JP 2005-183650 A

しかしながら、特許文献１に示す製造方法では、接合時に裏面電極のＮｉ層が、Ａｌ−Ｎｉ合金層の生成により消費されるため、接合後の裏面電極のＮｉ層が薄くなる。このＮｉ層が薄過ぎると、裏面電極のＮｉ層が半導体素子側で（具体的にはＮｉ層とＴｉ層の間で）剥離するおそれがある。   However, in the manufacturing method shown in Patent Document 1, since the Ni layer of the back electrode is consumed by the formation of the Al—Ni alloy layer during bonding, the Ni layer of the back electrode after bonding becomes thin. If this Ni layer is too thin, the Ni layer of the back electrode may be peeled off on the semiconductor element side (specifically, between the Ni layer and the Ti layer).

さらに、半導体素子とＺｎ−Ａｌ系はんだとの熱膨張差は、Ｚｎ−Ａｌ系はんだとリードフレームとの熱膨張差よりも大きい。このため、接合時に、半導体素子（裏面電極のＮｉ層）とＺｎ−Ａｌ系はんだとの界面において、Ｚｎ−Ｎｉ合金が生成された場合、半導体装置の使用時には、半導体素子とＺｎ−Ａｌ系はんだとの界面でクラックが発生することがあった。   Furthermore, the thermal expansion difference between the semiconductor element and the Zn—Al solder is larger than the thermal expansion difference between the Zn—Al solder and the lead frame. Therefore, when a Zn—Ni alloy is generated at the interface between the semiconductor element (the Ni layer of the back electrode) and the Zn—Al solder at the time of joining, the semiconductor element and the Zn—Al solder are used when the semiconductor device is used. Cracks may occur at the interface.

本発明は、このような点を鑑みてなされたものであり、その目的とするところは、半導体素子の裏面電極の剥離を抑え、半導体装置の使用時に、半導体素子とＺｎ−Ａｌ系はんだの界面のクラックの発生を抑えることができる半導体装置の製造方法を提供することにある。   The present invention has been made in view of the above points, and an object of the present invention is to suppress the peeling of the back electrode of the semiconductor element, and to use the interface between the semiconductor element and the Zn-Al solder when the semiconductor device is used. An object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the occurrence of cracks.

前記課題を鑑みて、本発明に係る半導体装置の製造方法は、裏面電極にＮｉ層を有する半導体素子を、Ｚｎ−Ａｌ系はんだを介してリードフレームに接合した半導体装置の製造方法であって、前記裏面電極と前記リードフレームとの間に、前記Ｚｎ−Ａｌ系はんだを配置し、接合温度が３９１〜４１９℃の範囲であり、かつ、以下の不等式を満たすように、前記半導体素子と前記リードフレームとを接合することを特徴とする。
０．２≦Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２≦０．７
ただし、Ｎ：接合前の裏面電極のＮｉ層の厚さ（μｍ）、
Ｒ：気体の状態定数（８．３１Ｊ／ｍｏｌ・Ｋ）、
Ｔ：接合温度（Ｋ）、
ｔ：接合温度保持時間（秒）。 In view of the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor element having a Ni layer on a back electrode is joined to a lead frame via a Zn-Al solder, The Zn—Al based solder is disposed between the back electrode and the lead frame, the semiconductor element and the lead are arranged so that the junction temperature is in the range of 391 to 419 ° C. and the following inequality is satisfied. It is characterized by joining the frame.
0.2 ≦ N− [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 ≦ 0.7
Where N is the thickness (μm) of the Ni layer of the back electrode before bonding,
R: gas state constant (8.31 J / mol · K),
T: Junction temperature (K),
t: Bonding temperature holding time (seconds).

本発明によれば、上述した不等式を満たすように、半導体素子とリードフレームの接合時に半導体素子の裏面電極のＮｉ層が、Ａｌ−Ｎｉ合金の生成により消費されても、裏面電極のＮｉ層の厚さを最適な厚さ（具体的には０．２〜０．７μｍ）に確保することができる。これにより、半導体装置の製造時に、裏面電極（Ｎｉ層）の剥離を回避することができるとともに、半導体装置の使用時に、半導体素子とＺｎ−Ａｌ系はんだの界面のクラックの発生を抑えることができる。   According to the present invention, even if the Ni layer of the back electrode of the semiconductor element is consumed by the formation of the Al—Ni alloy at the time of joining the semiconductor element and the lead frame so as to satisfy the above inequality, The thickness can be ensured to an optimum thickness (specifically, 0.2 to 0.7 μm). As a result, peeling of the back electrode (Ni layer) can be avoided during manufacture of the semiconductor device, and occurrence of cracks at the interface between the semiconductor element and the Zn—Al solder can be suppressed during use of the semiconductor device. .

本発明の実施形態に係る半導体装置の模式的断面図である。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. （ａ）は、Ｚｎ−Ａｌ系はんだに接合する前の半導体素子の裏面電極近傍の状態を示しており（ｂ）は、Ｚｎ−Ａｌ系はんだに接合した後の半導体素子の裏面電極近傍の状態を示した図である。(A) has shown the state of the back surface electrode vicinity of the semiconductor element before joining to Zn-Al type solder, (b) has shown the state of the back surface electrode vicinity of the semiconductor element after joining to Zn-Al type solder. FIG. 接合前の裏面電極のＮｉ層の厚さ０．１μｍ、接合温度４１５℃、接合温度保持時間９０秒の条件で接合したときの接合後のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図である。The thickness of the Ni layer of the back electrode before bonding, the thickness of the Ni layer after bonding, and the thickness of the Al—Ni alloy layer when bonded under the conditions of a bonding layer temperature of 415 ° C. and a bonding temperature holding time of 90 seconds. It is the figure which showed the relationship. （ａ）は、接合前の裏面電極のＮｉ層の厚さ０．４μｍ、接合温度４１５℃、接合温度保持時間９０秒の条件で接合したときの接合後のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図であり、（ｂ）は、接合前の裏面電極のＮｉ層の厚さ０．４μｍ、接合温度４１５℃、接合温度保持時間１８０秒の条件で接合したときの接合後のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図である。(A) shows the thickness of the Ni layer after bonding and the Al—Ni alloy when bonded under the conditions of the thickness of the Ni layer of the back electrode before bonding of 0.4 μm, the bonding temperature of 415 ° C., and the bonding temperature holding time of 90 seconds. It is the figure which showed the relationship of the thickness of a layer, (b) is when joining on the conditions of 0.4 micrometer of Ni layer thickness of the back surface electrode before joining, joining temperature 415 degreeC, and joining temperature holding time 180 seconds It is the figure which showed the relationship between the thickness of Ni layer after joining, and the thickness of an Al-Ni alloy layer. （ａ）は、接合前の裏面電極のＮｉ層の厚さ０．７μｍ、接合温度４００〜４１５℃、接合温度保持時間１５〜４５０秒の条件で接合したときの接合後のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図であり、（ｂ）は、接合前の裏面電極のＮｉ層の厚さ０．７μｍ、接合温度４１５℃、接合温度保持時間９０秒の条件で接合したときの接合後のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図である。(A) is the thickness of the Ni layer after bonding when the Ni layer thickness of the back electrode before bonding is 0.7 μm, the bonding temperature is 400 to 415 ° C., and the bonding temperature holding time is 15 to 450 seconds. It is the figure which showed the relationship of the thickness of an Al-Ni alloy layer, (b) is the conditions of thickness 0.7micrometer of Ni layer of the back electrode before joining, joining temperature 415 degreeC, and joining temperature holding time 90 second It is the figure which showed the relationship between the thickness of the Ni layer after joining, and the thickness of an Al-Ni alloy layer when joining by. 確認試験３の（１）〜（４）に示す、すべての接合試験片のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図である。It is the figure which showed the relationship between the thickness of Ni layer of all the joining test pieces shown in (1)-(4) of the confirmation test 3, and the thickness of an Al-Ni alloy layer. 接合温度の（保持時間）（１／２）と接合時のＮｉ層の消費量との関係を示した図である。It is the figure which showed the relationship between (holding time) (1/2) of joining temperature, and the consumption of the Ni layer at the time of joining. 接合温度の（１／接合温度）とＬｎ（ｋ２）との関係を示した図である。It is a diagram illustrating a relationship between the junction temperature (1 / bonding temperature) and Ln (k 2). 初晶Ｚｎが晶出した場合と、初晶Ｚｎが晶出していない場合の接合試験片の冷熱試験後のクラック長の結果を示した図である。It is the figure which showed the result of the crack length after the thermal test of the joining test piece when primary crystal Zn crystallizes and when primary crystal Zn does not crystallize. 実施例１，２および比較例１，２に係る接合試験片の冷熱試験後のクラック長の結果を示した図である。It is the figure which showed the result of the crack length after the thermal test of the joining test piece which concerns on Examples 1, 2 and Comparative Examples 1,2.

以下の本発明の実施形態に係る半導体装置の製造方法を以下に説明する。
図１は、本発明の実施形態に係る半導体装置１の模式的断面図であり、図２（ａ）は、Ｚｎ−Ａｌ系はんだに接合する前の半導体素子１０の裏面電極１５近傍の状態を示しており、図２（ｂ）は、Ｚｎ−Ａｌ系はんだに接合した後の半導体素子１０の裏面電極１５近傍の状態を示した図である。 A method for manufacturing a semiconductor device according to embodiments of the present invention will be described below.
FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2A shows a state in the vicinity of a back electrode 15 of a semiconductor element 10 before bonding to a Zn—Al solder. FIG. 2B shows a state in the vicinity of the back surface electrode 15 of the semiconductor element 10 after being bonded to the Zn—Al solder.

図１に示すように、本実施形態に係る半導体装置１は、銅基板等のリードフレーム１１，１７に、半導体素子１０を搭載した装置であり、これらは、樹脂１９により一体的にモールド成形されている。   As shown in FIG. 1, a semiconductor device 1 according to the present embodiment is a device in which a semiconductor element 10 is mounted on lead frames 11 and 17 such as a copper substrate, and these are integrally molded by a resin 19. ing.

半導体素子１０は、その表面側では、Ｎｉメッキされたターミナル１３に、Ｚｎ−Ａｌ系はんだ１４を介して接合されており、その裏面側では、後述する半導体素子１０の裏面電極１５（図２参照）が、Ｚｎ−Ａｌ系はんだ１６を介してリードフレーム１７に接合されている。さらに、半導体素子１０はワイヤ１８に接続されている。さらにターミナル１３は、Ｚｎ−Ａｌ系はんだ１２を介してリードフレーム１１に接合されている。   The semiconductor element 10 is joined to a Ni-plated terminal 13 via a Zn-Al based solder 14 on the front surface side, and on the rear surface side, a back electrode 15 of the semiconductor element 10 described later (see FIG. 2). ) Is bonded to the lead frame 17 via the Zn—Al solder 16. Further, the semiconductor element 10 is connected to the wire 18. Further, the terminal 13 is joined to the lead frame 11 via the Zn—Al solder 12.

リードフレーム１１，１７およびターミナル１３は、銅を母材として、その表面にＮｉ層が形成されている。Ｎｉ層は、メッキまたはスパッタリング等により形成される。さらに、Ｎｉ層の表面には、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはＰｄの薄膜が形成されていてもよい。このような薄膜を形成することにより、リードフレームに対する後述するＺｎ−Ａｌ系はんだの濡れ性を高めることができ、接合時には、薄膜を構成する金属は、はんだに拡散し、薄膜は略消滅する。   The lead frames 11 and 17 and the terminal 13 have copper as a base material and a Ni layer formed on the surface thereof. The Ni layer is formed by plating or sputtering. Furthermore, a thin film of Cu, Ag, Au, Pt, or Pd may be formed on the surface of the Ni layer. By forming such a thin film, the wettability of a Zn—Al-based solder, which will be described later, with respect to the lead frame can be increased. At the time of bonding, the metal constituting the thin film diffuses into the solder, and the thin film substantially disappears.

図２（ａ）に示すように、半導体素子１０の半導体素子本体１０ａの裏面には、裏面電極１５が形成されている。半導体素子本体１０ａは、Ｓｉ素子、またはＳｉＣ、ＧａＮなどのワイドギャップ半導体素子などを挙げることができる。   As shown in FIG. 2A, a back electrode 15 is formed on the back surface of the semiconductor element body 10 a of the semiconductor element 10. Examples of the semiconductor element body 10a include Si elements or wide gap semiconductor elements such as SiC and GaN.

裏面電極１５は、裏面側から順に第１層１５ｂ〜第４層１５ｅを積層した電極である。第１層１５ｂは、Ａｌ，Ａｌ−Ｓｉ，Ｎｉ−Ｓｉなどからなる層である。第２層１５ｃは、Ｔｉからなる層である。第３層１５ｄは、ＮｉまたはＮｉ−Ｐからなる層であり、本発明でいう「Ｎｉ層」に相当する。第４層１５ｅは、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはＰｄからなる層であり、Ｚｎ−Ａｌ系はんだと接合する際には、Ｚｎ−Ａｌ系はんだに拡散し、消滅する。   The back surface electrode 15 is an electrode in which a first layer 15b to a fourth layer 15e are stacked in order from the back surface side. The first layer 15b is a layer made of Al, Al—Si, Ni—Si, or the like. The second layer 15c is a layer made of Ti. The third layer 15d is a layer made of Ni or Ni—P and corresponds to the “Ni layer” in the present invention. The fourth layer 15e is a layer made of Cu, Ag, Au, Pt, or Pd, and diffuses into the Zn—Al based solder and disappears when bonded to the Zn—Al based solder.

半導体装置１を製造する際には、半導体素子１０の裏面電極１５とリードフレーム１７との間に、Ｚｎ−Ａｌ系はんだ１６を配置し、Ｚｎ−Ａｌ系はんだ１６を加熱して溶融し、Ｚｎ−Ａｌ系はんだ１６を介して、半導体素子１０とリードフレーム１７とを接合する。   When manufacturing the semiconductor device 1, a Zn—Al based solder 16 is disposed between the back electrode 15 of the semiconductor element 10 and the lead frame 17, and the Zn—Al based solder 16 is heated and melted. The semiconductor element 10 and the lead frame 17 are joined via the Al-based solder 16.

この際、接合温度を３９１〜４１９℃の範囲にして、半導体素子１０とリードフレーム１７とを接合する。これにより、図２（ｂ）に示すように、第４層１５ｅが消滅するとともに、第３層１５ｄ（Ｎｉ層）のＮｉとＺｎ−Ａｌ系はんだ１６のＡｌにより、半導体素子１０の第３層１５ｄとＺｎ−Ａｌ系はんだ１６との間に、Ａｌ３Ｎｉ２からなるＡｌ−Ｎｉ合金層１５ｆが形成される。ここで、接合温度が３９１℃未満である場合には、はんだが溶融しないため、Ａｌ−Ｎｉ合金層１５ｆが形成されず、接合温度が４１９℃を超えた場合には、ＺｎとＮｉの共存下で液相となるため、Ｚｎ中へのＮｉの拡散速度が大きくなり、Ｚｎ−Ｎｉ合金が形成されやすい。 At this time, the semiconductor element 10 and the lead frame 17 are bonded with the bonding temperature in the range of 391 to 419 ° C. As a result, as shown in FIG. 2B, the fourth layer 15e disappears, and the third layer 15d of the semiconductor element 10 is formed by Ni of the third layer 15d (Ni layer) and Al of the Zn—Al based solder 16. An Al—Ni alloy layer 15 f made of Al 3 Ni 2 is formed between 15 d and the Zn—Al based solder 16. Here, when the bonding temperature is lower than 391 ° C., the solder does not melt, so the Al—Ni alloy layer 15 f is not formed, and when the bonding temperature exceeds 419 ° C., Zn and Ni coexist. Therefore, the diffusion rate of Ni into Zn increases, and a Zn—Ni alloy is easily formed.

この接合温度の条件を前提に、以下の不等式を満たすように半導体素子１０とリードフレーム１７とを接合する。
０．２≦Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２≦０．７
ただし、Ｎ：接合前の裏面電極の第３層（Ｎｉ層）の厚さ（μｍ）、
Ｒ：気体の状態定数（８．３１Ｊ／ｍｏｌ・Ｋ）、
Ｔ：接合温度（Ｋ）、
ｔ：接合温度保持時間。 On the premise of this bonding temperature condition, the semiconductor element 10 and the lead frame 17 are bonded so as to satisfy the following inequality.
0.2 ≦ N− [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 ≦ 0.7
Where N is the thickness (μm) of the third layer (Ni layer) of the back electrode before bonding,
R: gas state constant (8.31 J / mol · K),
T: Junction temperature (K),
t: Bonding temperature holding time.

この式の上限値（０．７）および下限値（０．２）は、接合後の半導体素子１０の裏面電極１５の第３層（Ｎｉ層）１５ｄの厚さ（μｍ）を意味し、数式：〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２は、接合時におけるＮｉ層の消費量（厚さ（μｍ））を意味する。したがって、数式：Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２は、接合後に残存する、裏面電極１５のＮｉ層の厚さのことである。 The upper limit value (0.7) and the lower limit value (0.2) of this equation mean the thickness (μm) of the third layer (Ni layer) 15d of the back electrode 15 of the semiconductor element 10 after bonding. : [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 means the consumption (thickness (μm)) of the Ni layer at the time of bonding. Therefore, the formula: N− [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 is the thickness of the Ni layer of the back electrode 15 remaining after bonding. It is.

上述した不等式を満たすように、半導体素子１０とリードフレーム１７の接合時に半導体素子１０の裏面電極１５の第３層（Ｎｉ層）１５ｄが、Ａｌ−Ｎｉ合金の生成により消費されても、裏面電極１５の第３層（Ｎｉ層）１５ｄの厚さを最適な厚さ（具体的には０．２〜０．７μｍ）に確保することができる。   Even if the third layer (Ni layer) 15d of the back electrode 15 of the semiconductor element 10 is consumed due to the generation of the Al—Ni alloy at the time of joining the semiconductor element 10 and the lead frame 17 so as to satisfy the above inequality, the back electrode The thickness of the 15th third layer (Ni layer) 15d can be ensured to an optimum thickness (specifically, 0.2 to 0.7 μm).

これにより、半導体装置１の製造時に、裏面電極１５の第３層（Ｎｉ層）１５ｄの剥離を回避することができるとともに、半導体装置１の使用時に、半導体素子１０とＺｎ−Ａｌ系はんだ１６の界面のクラックの発生を抑えることができる。また、接合前のＺｎ−Ａｌ系はんだのＡｌの含有率は、４〜６質量％の範囲にあることが好ましく、接合後のＺｎ−Ａｌ系はんだのＡｌの含有率は、３〜５質量％の範囲にあることが好ましい。接合前のＡｌの含有率が４質量％未満になると、Ｚｎ−Ａｌ系はんだの融点が増加し、接合前のＡｌの含有率が６質量％を超えると、Ｚｎ−Ａｌ系はんだの表面のＡｌが酸化する割合が増加して、Ｚｎ−Ａｌ系はんだのボイド発生率が増加することがある。   Thereby, peeling of the 3rd layer (Ni layer) 15d of the back surface electrode 15 can be avoided at the time of manufacture of the semiconductor device 1, and at the time of use of the semiconductor device 1, the semiconductor element 10 and the Zn-Al solder 16 can be prevented. Generation of cracks at the interface can be suppressed. Further, the Al content of the Zn—Al solder before joining is preferably in the range of 4 to 6 mass%, and the Al content of the Zn—Al solder after joining is 3 to 5 mass%. It is preferable that it exists in the range. When the Al content before bonding is less than 4% by mass, the melting point of the Zn—Al solder increases, and when the Al content before bonding exceeds 6% by mass, the Al on the surface of the Zn—Al solder is increased. Oxidizing rate may increase, and the void generation rate of Zn-Al solder may increase.

〔確認試験１：裏面電極のＮｉ層の最適厚さ〕
半導体素子本体の裏面に、第１層に相当するＡｌ−Ｓｉ層、第２層に相当するＴｉ層、第３層に相当するＮｉ層（厚さ０．１μｍ、０．４μｍ、０．７μｍ、１．０μｍ、１．５μｍ、２．０μｍ、または３．０μｍ）、第４層に相当するＡｕ層（０．１μｍ）の順に、積層し、裏面電極を形成した。その後、目視で、裏面電極の状態を確認した。 [Confirmation test 1: Optimal thickness of Ni layer on back electrode]
On the back surface of the semiconductor element body, an Al—Si layer corresponding to the first layer, a Ti layer corresponding to the second layer, a Ni layer corresponding to the third layer (thickness 0.1 μm, 0.4 μm, 0.7 μm, 1.0 μm, 1.5 μm, 2.0 μm, or 3.0 μm) and an Au layer (0.1 μm) corresponding to the fourth layer were laminated in this order to form a back electrode. Then, the state of the back electrode was confirmed visually.

この結果、Ｎｉ層が１．０μｍ以上となる裏面電極は、半導体素子本体から剥離していることがわかった。これは、Ｎｉ層を厚くすることにより、裏面電極が半導体素子本体から剥離する方向に応力が作用しているからであると考えられる。この結果、半導体素子の裏面電極のＮｉ層の最適厚さは、０．７μｍ以下である。   As a result, it was found that the back electrode having a Ni layer of 1.0 μm or more was peeled from the semiconductor element body. This is presumably because stress is acting in the direction in which the back electrode is peeled off from the semiconductor element body by increasing the thickness of the Ni layer. As a result, the optimum thickness of the Ni layer on the back electrode of the semiconductor element is 0.7 μm or less.

〔確認試験２：裏面電極のＮｉ層の上限の厚さ（Ｚｎ−Ｎｉ合金生成の観点から）〕
確認試験１と同様の構成の裏面電極のＮｉ層の厚さが、０．１μｍ、０．４μｍ、０．７μｍ、１．０μｍ、１．５μｍ、２．０μｍ、３．０μｍの半導体素子を準備した。これらの半導体素子の裏面電極のＮｉ層とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置した。次に、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４００℃、接合時間９０秒で、Ｚｎ−Ａｌ系はんだを介して、半導体素子とリードフレームとを接合し、接合試験片を作製した。得られた接合試験片のＮｉ層とＺｎ−Ａｌ系はんだとの界面にＺｎ−Ｎｉ合金の生成の有無を確認した。この結果を表１に示す。 [Confirmation test 2: Upper limit thickness of Ni layer of back electrode (from the viewpoint of Zn-Ni alloy formation)]
Prepared are semiconductor elements having a Ni layer thickness of 0.1 μm, 0.4 μm, 0.7 μm, 1.0 μm, 1.5 μm, 2.0 μm, and 3.0 μm on the back electrode having the same configuration as that in Confirmation Test 1. did. Zn—Al solder was disposed between the Ni layer on the back electrode of these semiconductor elements and the lead frame. Next, the semiconductor element and the lead frame are bonded via a Zn-Al solder under an inert gas atmosphere (hydrogen gas 10 volume%, nitrogen gas 90 volume%) at a bonding temperature of 400 ° C. and a bonding time of 90 seconds. Then, a joining test piece was produced. The presence or absence of the production | generation of a Zn-Ni alloy was confirmed in the interface of Ni layer and Zn-Al type solder of the obtained joining test piece. The results are shown in Table 1.

Figure 0006493161
Figure 0006493161

以上のことから、半導体素子の裏面電極のＮｉ層の厚さが、０．７μｍ以下であれば、Ｚｎ−Ｎｉ合金の生成が抑えられる。Ｎｉ層のＮｉの熱伝導率は、半導体素子のＳｉおよびＺｎ−Ａｌ系はんだのＺｎ−Ａｌ合金の熱伝導率よりも小さいため、Ｎｉ層の厚さが増加するにつれて、接合界面の熱伝導性が低下する。このため、Ｎｉ層の厚さが１．０μｍ以上のものは、局部的に温度が高くなり（Ｚｎ−Ｎｉ合金の生成開始温度（４１９℃）以上となり）、Ｚｎ−Ｎｉ合金が生成されたと考えられる。したがって、Ｚｎ−Ｎｉ合金が生成された接合試験片は、クラックが発生しやすいと考えられる。   From the above, when the thickness of the Ni layer on the back electrode of the semiconductor element is 0.7 μm or less, the formation of Zn—Ni alloy can be suppressed. Since the thermal conductivity of Ni in the Ni layer is smaller than the thermal conductivity of the semiconductor element Si and Zn—Al alloy of the Zn—Al solder, the thermal conductivity of the bonding interface increases as the Ni layer thickness increases. Decreases. For this reason, when the thickness of the Ni layer is 1.0 μm or more, the temperature locally increases (becomes higher than the formation start temperature of the Zn—Ni alloy (419 ° C.)), and it is considered that the Zn—Ni alloy was produced. It is done. Therefore, it is considered that the bonding test piece in which the Zn—Ni alloy is generated is likely to crack.

〔確認試験３：接合条件の最適範囲〕
（１）Ｎｉ層厚さ０．１μｍの場合
確認試験１に示す裏面電極のＮｉ層が、０．１μｍの半導体素子のＮｏ．１〜９の半導体素子を９個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４１５℃、接合温度保持時間９０秒のリフロー接合条件で、半導体素子とリードフレームとをリフロー接合し、Ｎｏ．１〜９の接合試験片を作製した。得られた半導体素子の裏面電極のＮｉ層の厚さ（残存する厚さ）と、Ｎｉ層とＺｎ−Ａｌ系はんだとの界面に形成されたＡｌ−Ｎｉ合金層の厚さを測定した。この結果を表２および図３に示す。表２の結果から明らかなように、すべての接合試験片で、裏面電極がＺｎ−Ａｌ系はんだから剥離していた。なお、同じ条件で接合しても、Ａｌ−Ｎｉ合金層（金属間化合物層）は、３次元に成長するため、Ｎｉ層の厚さと、Ａｌ−Ｎｉ合金層の厚さとの関係には、バラツキが生じている。 [Confirmation test 3: Optimum range of joining conditions]
(1) When Ni layer thickness is 0.1 μm The Ni layer of the back electrode shown in Confirmation Test 1 is No. of a 0.1 μm semiconductor element. Nine semiconductor elements 1 to 9 were prepared. Then, Zn—Al solder is disposed between the back electrode and the lead frame, under an inert gas atmosphere (hydrogen gas 10 vol%, nitrogen gas 90 vol%), a bonding temperature 415 ° C., and a bonding temperature holding time 90. Reflow bonding of the semiconductor element and the lead frame under the reflow bonding conditions of seconds, 1 to 9 bonding test pieces were prepared. The thickness (remaining thickness) of the Ni layer of the back electrode of the obtained semiconductor element and the thickness of the Al—Ni alloy layer formed at the interface between the Ni layer and the Zn—Al based solder were measured. The results are shown in Table 2 and FIG. As is clear from the results in Table 2, the back electrode was peeled off from the Zn—Al solder in all the joint test pieces. Even if the bonding is performed under the same conditions, the Al—Ni alloy layer (intermetallic compound layer) grows three-dimensionally. Therefore, the relationship between the thickness of the Ni layer and the thickness of the Al—Ni alloy layer varies. Has occurred.

Figure 0006493161
Figure 0006493161

（２）Ｎｉ層厚さ０．４μｍの場合
（２−１）接合温度４１５℃、接合温度保持時間９０秒の場合
確認試験１に示す裏面電極のＮｉ層が、０．４μｍの半導体素子のＮｏ．１０〜４４の半導体素子を３５個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４１５℃、接合温度保持時間９０秒のリフロー接合条件で、半導体素子とリードフレームとをリフロー接合し、Ｎｏ．１０〜４４の接合試験片を作製した。得られた半導体素子の裏面電極のＮｉ層の厚さと、Ｎｉ層とＺｎ−Ａｌ系はんだとの界面に形成されたＡｌ−Ｎｉ合金層の厚さを測定した。この結果を表３および図４（ａ）に示す。表３の結果から明らかなように、すべての接合試験片で、裏面電極の剥離は無かった。 (2) When Ni layer thickness is 0.4 μm (2-1) When the junction temperature is 415 ° C. and the junction temperature holding time is 90 seconds, the Ni layer of the back electrode shown in Confirmation Test 1 is 0.4 μm of the semiconductor element No. . Thirty-five semiconductor elements of 10 to 44 were prepared. Then, Zn—Al solder is disposed between the back electrode and the lead frame, under an inert gas atmosphere (hydrogen gas 10 vol%, nitrogen gas 90 vol%), a bonding temperature 415 ° C., and a bonding temperature holding time 90. Reflow bonding of the semiconductor element and the lead frame under the reflow bonding conditions of seconds, Ten to 44 joining test pieces were prepared. The thickness of the Ni layer of the back electrode of the obtained semiconductor element and the thickness of the Al—Ni alloy layer formed at the interface between the Ni layer and the Zn—Al solder were measured. The results are shown in Table 3 and FIG. As is clear from the results in Table 3, there was no peeling of the back electrode in all the bonding test pieces.

Figure 0006493161
Figure 0006493161

（２−２）接合温度４１５℃、接合温度保持時間１８０秒の場合
確認試験１に示す裏面電極のＮｉ層が、０．４μｍの半導体素子のＮｏ．４５〜６５の半導体素子を２１個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４１５℃、接合温度保持時間１８０秒のリフロー接合条件で、半導体素子とリードフレームとをリフロー接合し、Ｎｏ．４５〜６５の接合試験片を作製した。得られた半導体素子の裏面電極のＮｉ層の厚さと、Ｎｉ層とＺｎ−Ａｌ系はんだとの界面に形成されたＡｌ−Ｎｉ合金層の厚さを測定した。この結果を表４および図４（ｂ）に示す。表４の結果から明らかなように、すべての接合試験片で、裏面電極がＺｎ−Ａｌ系はんだから剥離していた。 (2-2) In the case where the bonding temperature is 415 ° C. and the bonding temperature holding time is 180 seconds, the Ni layer of the back electrode shown in Confirmation Test 1 is No. of the semiconductor element having a thickness of 0.4 μm. 21 semiconductor elements of 45 to 65 were prepared. Then, Zn—Al solder is disposed between the back electrode and the lead frame, in an inert gas atmosphere (hydrogen gas 10 vol%, nitrogen gas 90 vol%), a bonding temperature 415 ° C., and a bonding temperature holding time 180. Reflow bonding of the semiconductor element and the lead frame under the reflow bonding conditions of seconds, 45 to 65 joining test pieces were prepared. The thickness of the Ni layer of the back electrode of the obtained semiconductor element and the thickness of the Al—Ni alloy layer formed at the interface between the Ni layer and the Zn—Al solder were measured. The results are shown in Table 4 and FIG. 4 (b). As is clear from the results in Table 4, the back electrode was peeled off from the Zn—Al solder in all the joint test pieces.

Figure 0006493161
Figure 0006493161

（３）Ｎｉ層厚さ０．７μｍの場合
（３−１）接合温度４００〜４１５℃、接合温度保持時間１５〜４５０秒の場合
確認試験１に示す裏面電極のＮｉ層が、０．７μｍの半導体素子のＮｏ．６６〜８０の半導体素子を１５個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４００〜４１５℃、接合温度保持時間１５〜４５０秒の表５に示すリフロー接合条件で、半導体素子とリードフレームとをリフロー接合し、Ｎｏ．６６〜８０の接合試験片を作製した。得られた半導体素子の裏面電極のＮｉ層の厚さと、Ｎｉ層とＺｎ−Ａｌ系はんだとの界面に形成されたＡｌ−Ｎｉ合金層の厚さを測定した。この結果を表５および図５（ａ）に示す。表５の結果から明らかなように、すべての接合試験片で、裏面電極の剥離は無かった。 (3) When the Ni layer thickness is 0.7 μm (3-1) When the bonding temperature is 400 to 415 ° C. and the bonding temperature holding time is 15 to 450 seconds The Ni layer of the back electrode shown in Confirmation Test 1 is 0.7 μm No. of semiconductor element. Fifteen semiconductor elements 66 to 80 were prepared. Then, Zn—Al solder is disposed between the back electrode and the lead frame, and under an inert gas atmosphere (hydrogen gas 10 volume%, nitrogen gas 90 volume%), the bonding temperature is 400 to 415 ° C., and the bonding temperature is maintained. Under the reflow bonding conditions shown in Table 5 for 15 to 450 seconds, the semiconductor element and the lead frame were reflow bonded. 66-80 joint test pieces were produced. The thickness of the Ni layer of the back electrode of the obtained semiconductor element and the thickness of the Al—Ni alloy layer formed at the interface between the Ni layer and the Zn—Al solder were measured. The results are shown in Table 5 and FIG. As is clear from the results in Table 5, there was no peeling of the back electrode in all the bonding test pieces.

Figure 0006493161
Figure 0006493161

（３−２）接合温度４１５℃、接合温度保持時間９０秒の場合
確認試験１に示す裏面電極のＮｉ層が、０．７μｍの半導体素子のＮｏ．８１〜１１１の半導体素子を３１個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、不活性ガス雰囲気下（水素ガス１０体積％、窒素ガス９０体積％）、接合温度４１５℃、接合温度保持時間９０秒のリフロー条件で、半導体素子とリードフレームとをリフロー接合し、Ｎｏ．８１〜１１１の接合試験片を作製した。得られた半導体素子の裏面電極のＮｉ層の厚さと、Ｎｉ層とＺｎ−Ａｌ系はんだとの界面に形成されたＡｌ−Ｎｉ合金層の厚さを測定した。この結果を表６および図５（ｂ）に示す。表６の結果から明らかなように、すべての接合試験片で、裏面電極の剥離は無かった。 (3-2) When the junction temperature is 415 ° C. and the junction temperature holding time is 90 seconds, the Ni layer of the back electrode shown in the confirmation test 1 is 0.7 μm in the semiconductor element No. 31 semiconductor elements 81 to 111 were prepared. Then, Zn—Al solder is disposed between the back electrode and the lead frame, under an inert gas atmosphere (hydrogen gas 10 vol%, nitrogen gas 90 vol%), a bonding temperature 415 ° C., and a bonding temperature holding time 90. Reflow bonding of the semiconductor element and the lead frame under the reflow conditions of seconds, 81 to 111 bonding test pieces were prepared. The thickness of the Ni layer of the back electrode of the obtained semiconductor element and the thickness of the Al—Ni alloy layer formed at the interface between the Ni layer and the Zn—Al solder were measured. The results are shown in Table 6 and FIG. As is clear from the results in Table 6, there was no peeling of the back electrode in all the bonding test pieces.

Figure 0006493161
Figure 0006493161

（４）超音波接合の場合（Ａｌ−Ｎｉ合金層なしの場合）
確認試験１に示す裏面電極のＮｉ層が、０．５μｍ，０．７μｍの半導体素子のＮｏ．１１２，１１３の半導体素子を２個準備した。そして、裏面電極とリードフレームとの間に、Ｚｎ−Ａｌ系はんだを配置し、室温で１０秒間超音波振動を印加して、半導体素子とリードフレームとを接合した。これにより、Ａｌ−Ｎｉ合金層（層厚み０μｍ）が形成されていないＮｏ．１１２，１１３の接合試験片を作製した。 (4) For ultrasonic bonding (without Al-Ni alloy layer)
The Ni layer of the back electrode shown in Confirmation Test 1 has a semiconductor element No. of 0.5 μm and 0.7 μm. Two semiconductor elements 112 and 113 were prepared. Then, Zn—Al solder was placed between the back electrode and the lead frame, and ultrasonic vibration was applied for 10 seconds at room temperature to join the semiconductor element and the lead frame. Thereby, No. in which the Al—Ni alloy layer (layer thickness 0 μm) was not formed. 112 and 113 bonding test pieces were produced.

得られた接合試験片を３５０℃に加熱して、接合試験片に熱応力を付与した。この結果、表７に示すように、Ａｌ−Ｎｉ合金層（層厚み０μｍ）が形成されていない接合試験片では、半導体素子の裏面電極のＮｉ層とＺｎ−Ａｌ系はんだとの界面で剥離が確認された。   The obtained joining test piece was heated to 350 ° C., and thermal stress was applied to the joining test piece. As a result, as shown in Table 7, in the joining test piece in which the Al—Ni alloy layer (layer thickness: 0 μm) is not formed, peeling occurs at the interface between the Ni layer on the back electrode of the semiconductor element and the Zn—Al based solder. confirmed.

なお、Ｎｏ．１０〜４４、Ｎｏ．６６〜１１１の接合試験片のうち、接合後に、０．１〜１．７μｍの範囲の厚さのＡｌ−Ｎｉ合金層が形成された接合試験片に対して、３５０℃に加熱して、接合試験片に熱応力を付与した。しかしながら、半導体素子の裏面電極の剥離は無かった。したがって、接合後は、少なくとも、０．１μｍのＡｌ−Ｎｉ（Ａｌ３Ｎｉ２）合金層が存在することが好ましい。 In addition, No. 10-44, no. Among the joining test pieces of 66 to 111, after joining, the joining test piece on which an Al—Ni alloy layer having a thickness in the range of 0.1 to 1.7 μm was formed was heated to 350 ° C. and joined. Thermal stress was applied to the test piece. However, there was no peeling of the back electrode of the semiconductor element. Therefore, it is preferable that at least a 0.1 μm Al—Ni (Al 3 Ni 2 ) alloy layer exists after bonding.

Figure 0006493161
Figure 0006493161

図６は、確認試験３の（１）〜（４）に示す、すべての接合試験片のＮｉ層の厚さとＡｌ−Ｎｉ合金層の厚さの関係を示した図である。なお、図６に示す○印は、剥離無し、×印は隔離有りを示している。図６に示すように、接合後の裏面電極のＮｉ層の厚さが０．２〜０．７μｍの範囲で、裏面電極のＮｉ層の剥離が少ない傾向にあり、接合後の裏面電極のＮｉ層の厚さが０．２μｍ未満である場合には、裏面電極のＮｉ層の剥離が多いと言える。   FIG. 6 is a diagram showing the relationship between the thickness of the Ni layer and the thickness of the Al—Ni alloy layer of all the joining test pieces shown in (1) to (4) of Confirmation Test 3. In FIG. 6, the ◯ marks indicate no peeling, and the X marks indicate isolation. As shown in FIG. 6, when the thickness of the Ni layer of the back electrode after bonding is in the range of 0.2 to 0.7 μm, the Ni layer of the back electrode tends to be less peeled. When the thickness of the layer is less than 0.2 μm, it can be said that there is much peeling of the Ni layer of the back electrode.

そこで、これらの試験結果には、バラツキがあるため、統計解析手法である応答曲面法で、接合温度の保持時間とＮｉ層の消費量との関係を統計解析した。この結果を図７に示す。図７は、接合温度の（保持時間）（１／２）と接合時のＮｉ層の消費量との関係を示した図である。なお、Ｎｉ層の消費量は、接合前のＮｉ層の厚さから接合後のＮｉ層の厚さを差し引いた値である。次に、図７に示す、接合温度４００℃、４０７℃、４１５℃の３つの温度におけるグラフの傾きから、Ｎｉ層の消費速度を算出した。この結果を、表８に示す。 Therefore, since these test results have variations, the response surface method, which is a statistical analysis method, was used to statistically analyze the relationship between the holding time of the junction temperature and the consumption of the Ni layer. The result is shown in FIG. FIG. 7 is a diagram showing the relationship between the (holding time) (1/2) of the junction temperature and the consumption of the Ni layer at the time of joining. The consumption amount of the Ni layer is a value obtained by subtracting the thickness of the Ni layer after bonding from the thickness of the Ni layer before bonding. Next, the consumption rate of the Ni layer was calculated from the slopes of the graphs at three temperatures of 400 ° C., 407 ° C., and 415 ° C. shown in FIG. The results are shown in Table 8.

Figure 0006493161
Figure 0006493161

ここで、一般に、Ｎｉ層の消費量は、以下に示す、温度と時間の関数を用いたアレニウスの式で表すことができる。
ｋ２＝Ａ・ｅｘｐ（−Ｅ／ＲＴ）
ただし、ｋ：Ｎｉ層消費速度、Ａ：定数、Ｅ：活性エネルギー（Ｊ／ｍｏｌ）、Ｒ：気体の状態定数８．３１（Ｊ／ｍｏｌ・Ｋ）、Ｔ：接合温度（Ｋ）
この式の両辺で対数を取ると、
Ｌｎ（ｋ２）＝ｌｎＡ−Ｅ／ＲＴ
となる。 Here, in general, the consumption amount of the Ni layer can be expressed by the Arrhenius equation using the function of temperature and time shown below.
k 2 = A · exp (−E / RT)
However, k: Ni layer consumption rate, A: constant, E: active energy (J / mol), R: gas state constant 8.31 (J / mol · K), T: junction temperature (K)
Taking the logarithm on both sides of this formula,
Ln (k 2) = lnA- E / RT
It becomes.

ここで、ＡおよびＥを求めるため、表８に示す値から、図８に示すアレニウスプロットを実施した。なお、図８のＹ軸は、μｍをｍに変化してプロットしたものである。図８の結果から、Ｅ＝１４７１７０Ｊ／ｍｏｌ、Ａ＝０．０００１１８を得た。これにより、接合時のＮｉ層の消費量は、〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２で表すことができる。ただし、Ｒ：気体の状態定数（８．３１Ｊ／ｍｏｌ・Ｋ）、Ｔ：接合温度（Ｋ）、ｔ：接合温度保持時間（秒）である。 Here, in order to obtain A and E, the Arrhenius plot shown in FIG. 8 was performed from the values shown in Table 8. The Y axis in FIG. 8 is plotted by changing μm to m. From the results of FIG. 8, E = 147170 J / mol and A = 0.000118 were obtained. Thereby, the consumption amount of the Ni layer at the time of joining can be represented by [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 . Where R: gas state constant (8.31 J / mol · K), T: junction temperature (K), and t: junction temperature holding time (seconds).

そして、図６より、接合後の裏面電極のＮｉ層の厚さは、０．２〜０．７μｍの範囲であればよいことから、
０．２≦Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２≦０．７（ただし、Ｎ：接合前の裏面電極のＮｉ層の厚さ（μｍ））
ただし、Ｎ：接合前の裏面電極のＮｉ層の厚さ（μｍ）、
Ｒ：気体の状態定数（８．３１Ｊ／ｍｏｌ・Ｋ）、
Ｔ：接合温度（Ｋ）、
ｔ：接合温度保持時間（秒）
の不等式の条件を満たせば、半導体素子の裏面電極の剥離を抑え、接合試験片の使用時に、半導体素子とＺｎ−Ａｌ系はんだの界面のクラックの発生を抑えることができる、と考えられる。 And from FIG. 6, since the thickness of Ni layer of the back surface electrode after joining should just be the range of 0.2-0.7 micrometer,
0.2 ≦ N− [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 ≦ 0.7 (where N is the Ni layer of the back electrode before bonding) Thickness (μm))
Where N is the thickness (μm) of the Ni layer of the back electrode before bonding,
R: gas state constant (8.31 J / mol · K),
T: Junction temperature (K),
t: Bonding temperature holding time (seconds)
If the condition of the inequality is satisfied, it is considered that the peeling of the back electrode of the semiconductor element can be suppressed, and the occurrence of cracks at the interface between the semiconductor element and the Zn—Al solder can be suppressed when the bonding test piece is used.

〔確認試験４：接合後のＺｎ−Ａｌ系はんだのＡｌ量について〕
さらに、上述したＮｏ．１〜１１１の半導体素子とリードフレームとを接合したＺｎ−Ａｌ系はんだのＡｌの含有率を測定し、接合部分の断面をＳＥＭにより観察した。接合後のＺｎ-Ａｌ系はんだのＡｌの含有率が３質量％未満のものは、初晶Ｚｎの量が、それ以外のものに比べて多くなっていた。一方で、Ａｌの含有率が５質量％以上の場合には、初晶Ｚｎが晶出していない、または、初晶Ｚｎがほとんど晶出していない。 [Confirmation test 4: Al content of Zn-Al solder after joining]
Furthermore, the above-mentioned No. The Al content of the Zn-Al solder in which the semiconductor elements 1-111 and the lead frame were joined was measured, and the cross section of the joined part was observed by SEM. When the Zn content in the Zn-Al solder after bonding was less than 3% by mass, the amount of primary Zn was higher than that of the other. On the other hand, when the Al content is 5% by mass or more, the primary Zn is not crystallized or the primary Zn is hardly crystallized.

そこで、初晶Ｚｎが晶出した場合（すなわち、３質量％≦Ａｌ含有率≦５質量％）と、初晶Ｚｎが晶出していない場合（Ａｌ含有率＞５質量％）の接合試験片を作製し、−４０℃〜２５０℃の温度サイクルを１サイクルとして、１００サイクルで冷熱試験を行った。   Therefore, when the primary crystal Zn is crystallized (that is, 3% by mass ≦ Al content ≦ 5% by mass) and when the primary crystal Zn is not crystallized (Al content> 5% by mass) The sample was prepared, and a temperature test of -40 ° C to 250 ° C was taken as one cycle, and a thermal test was performed in 100 cycles.

その結果、図９に示すように、初晶Ｚｎが存在する方が、クラック長が小さく（クラック進展速度が小さく）、信頼性が高いことがわかった。なお、クラックは、半導体素子の裏面電極から３０μｍ以内の位置で進展し易い。このため、接合後のＺｎ−Ａｌ系はんだが３質量％≦Ａｌ含有率≦５質量％で、半導体素子の裏面電極から少なくとも３０μｍ以内の位置で初晶Ｚｎを晶出させることが好ましい。   As a result, as shown in FIG. 9, it was found that the presence of primary crystal Zn had a small crack length (small crack growth rate) and high reliability. In addition, a crack is easy to progress in the position within 30 micrometers from the back surface electrode of a semiconductor element. For this reason, it is preferable to crystallize primary Zn at a position within 3 μm ≦ Al content ≦ 5% by mass and at least 30 μm from the back electrode of the semiconductor element.

以下に、本発明の実施例を説明する。   Examples of the present invention will be described below.

（実施例１）
確認試験１に示す半導体素子を準備し、接合試験片を作製した。具体的には、Ｚｎ−Ａｌ系はんだによる接合後、Ｚｎ−Ａｌ系はんだがＺｎ−ｘＡｌ（３≦ｘ≦５）となり、０．２≦Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２≦０．７の不等式の条件を満たすように作製した。すなわち、Ｎ＝０．７μｍ、Ｔ＝４００℃、ｔ＝３０秒の接合条件で、半導体素子とリードフレームを接合した。なお、数式の値は、０．５８５であり、０．２〜０．７の範囲内である。 Example 1
The semiconductor element shown in the confirmation test 1 was prepared, and the joining test piece was produced. Specifically, after bonding with the Zn—Al solder, the Zn—Al solder becomes Zn—xAl (3 ≦ x ≦ 5), and 0.2 ≦ N− [0.000118 × exp (−147170 / RT) It was fabricated so as to satisfy the inequality condition of 1/2 × 10 6 × (t) 1/2 ≦ 0.7. That is, the semiconductor element and the lead frame were bonded under the bonding conditions of N = 0.7 μm, T = 400 ° C., and t = 30 seconds. In addition, the value of numerical formula is 0.585 and exists in the range of 0.2-0.7.

（実施例２）
実施例１と同じようにして、接合試験片を作製した。実施例１と相違する点は、Ｚｎ−Ａｌ系はんだによる接合後、Ｚｎ−Ａｌ系はんだがＺｎ−ｘＡｌ（ｘ＞５）となり、上述した不等式の条件を満たすように、半導体素子とリードフレームを接合した点である。すなわち、Ｎ＝０．７μｍ、Ｔ＝４００℃、ｔ＝３０秒の接合条件で、半導体素子とリードフレームを接合した。なお、数式の値は、０．５８５であり、０．２〜０．７の範囲内である。 (Example 2)
In the same manner as in Example 1, a joining test piece was produced. The difference from Example 1 is that after joining with Zn—Al solder, the Zn—Al solder becomes Zn—xAl (x> 5), and the semiconductor element and the lead frame are so arranged as to satisfy the above inequality condition. It is a joined point. That is, the semiconductor element and the lead frame were bonded under the bonding conditions of N = 0.7 μm, T = 400 ° C., and t = 30 seconds. In addition, the value of numerical formula is 0.585 and exists in the range of 0.2-0.7.

（比較例１）
実施例１と同じようにして、接合試験片を作製した。実施例１と相違する点は、上述した不等式の条件を満さないように、半導体素子とリードフレームを接合した点である。すなわち、Ｎ＝０．７μｍ、Ｔ＝４１５℃、ｔ＝４５０秒の接合条件で、半導体素子とリードフレームを接合した。なお、数式の値は、０．１０５であり、０．２〜０．７の範囲を外れている。なお、比較例１では、Ｚｎ−Ａｌ系はんだによる接合後、Ｚｎ−Ａｌ系はんだがＺｎ−ｘＡｌ（３≦ｘ≦５）である点は同じである。 (Comparative Example 1)
In the same manner as in Example 1, a joining test piece was produced. The difference from the first embodiment is that the semiconductor element and the lead frame are joined so as not to satisfy the above inequality condition. That is, the semiconductor element and the lead frame were bonded under the bonding conditions of N = 0.7 μm, T = 415 ° C., and t = 450 seconds. Note that the value of the mathematical formula is 0.105, which is out of the range of 0.2 to 0.7. Note that Comparative Example 1 is the same in that the Zn—Al solder is Zn—xAl (3 ≦ x ≦ 5) after joining with the Zn—Al solder.

（比較例２）
実施例１と同じようにして、接合試験片を作製した。実施例１と相違する点は、Ｚｎ−Ａｌ系はんだによる接合後、Ｚｎ−Ａｌ系はんだがＺｎ−ｘＡｌ（ｘ＞５）となり、上述した不等式の条件を満さないように、半導体素子とリードフレームを接合した点である。すなわち、Ｎ＝０．７μｍ、Ｔ＝４１５℃、ｔ＝４５０秒の接合条件で、半導体素子とリードフレームを接合した。なお、上述した数式の値は、０．１０５であり、０．２〜０．７の範囲を外れている。 (Comparative Example 2)
In the same manner as in Example 1, a joining test piece was produced. The difference from Example 1 is that after bonding with Zn—Al solder, the Zn—Al solder becomes Zn—xAl (x> 5), and the semiconductor element and the lead are not satisfied so that the above inequality condition is not satisfied. This is the point where the frames are joined. That is, the semiconductor element and the lead frame were bonded under the bonding conditions of N = 0.7 μm, T = 415 ° C., and t = 450 seconds. In addition, the value of the numerical formula mentioned above is 0.105, and is outside the range of 0.2-0.7.

（評価試験と結果）
実施例１、２および比較例１、２の接合試験片に対して、−４０℃〜２５０℃の温度サイクルを１サイクルとして、１００サイクルで冷熱試験を行った。この結果、図１０に示すように、実施例１の如く、Ｚｎ−Ａｌ系はんだがＺｎ−ｘＡｌ（３≦ｘ≦５）となり、上述した不等式の条件を満たす接合試験片が、最も耐久性が高いことがわかった。 (Evaluation test and results)
With respect to the joining test pieces of Examples 1 and 2 and Comparative Examples 1 and 2, a temperature test of −40 ° C. to 250 ° C. was taken as one cycle, and a cooling test was performed in 100 cycles. As a result, as shown in FIG. 10, the Zn—Al based solder becomes Zn—xAl (3 ≦ x ≦ 5) as in Example 1, and the joining test piece that satisfies the above inequality equation has the most durability. I found it expensive.

以上、本発明の実施の形態を詳述してきたが、具体的な構成はこの実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲における設計変更があっても、それらは本発明に含まれるものである。   Although the embodiment of the present invention has been described in detail above, the specific configuration is not limited to this embodiment, and even if there is a design change within a scope not departing from the gist of the present invention, they are not limited to this embodiment. It is included in the invention.

１：半導体装置、１０：半導体素子、１５：裏面電極、１５ｄ：第３層（Ｎｉ層）、１６：Ｚｎ−Ａｌ系はんだ、１７：リードフレーム。 1: Semiconductor device, 10: Semiconductor element, 15: Back electrode, 15d: Third layer (Ni layer), 16: Zn—Al solder, 17: Lead frame.

Claims (1)

裏面電極にＮｉ層を有する半導体素子を、Ｚｎ−Ａｌ系はんだを介してリードフレームに接合した半導体装置の製造方法であって、
前記裏面電極と前記リードフレームとの間に、前記Ｚｎ−Ａｌ系はんだを配置し、接合温度が３９１〜４１９℃の範囲であり、かつ、以下の不等式を満たすように、前記半導体素子と前記リードフレームとを接合することを特徴とする半導体装置の製造方法。
０．２≦Ｎ−〔０．０００１１８×ｅｘｐ（−１４７１７０／ＲＴ）〕１／２×１０６×（ｔ）１／２≦０．７
ただし、Ｎ：接合前の裏面電極のＮｉ層の厚さ（μｍ）、
Ｒ：気体の状態定数（８．３１Ｊ／ｍｏｌ・Ｋ）、
Ｔ：接合温度（Ｋ）、
ｔ：接合温度保持時間（秒）。 A method of manufacturing a semiconductor device in which a semiconductor element having a Ni layer on a back electrode is joined to a lead frame via a Zn-Al solder,
The Zn—Al based solder is disposed between the back electrode and the lead frame, the semiconductor element and the lead are arranged so that the junction temperature is in the range of 391 to 419 ° C. and the following inequality is satisfied. A method of manufacturing a semiconductor device, comprising joining a frame.
0.2 ≦ N− [0.000118 × exp (−147170 / RT)] 1/2 × 10 6 × (t) 1/2 ≦ 0.7
Where N is the thickness (μm) of the Ni layer of the back electrode before bonding,
R: gas state constant (8.31 J / mol · K),
T: Junction temperature (K),
t: Bonding temperature holding time (seconds).
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