JP6435794B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6435794B2
JP6435794B2 JP2014229968A JP2014229968A JP6435794B2 JP 6435794 B2 JP6435794 B2 JP 6435794B2 JP 2014229968 A JP2014229968 A JP 2014229968A JP 2014229968 A JP2014229968 A JP 2014229968A JP 6435794 B2 JP6435794 B2 JP 6435794B2
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insulating substrate
resin case
heat sink
semiconductor device
plate
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JP2016096188A (en
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傳田　俊男
俊男 傳田
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

ＤＣ−ＤＣコンバータにはダイオードチップを内蔵したパワー半導体モジュールが用いられているものがある。
図５は，かかるパワー半導体モジュールの一例の断面図である。また、図６は、図５に示したパワー半導体モジュールの平面図である。なお、図５は、図６のＶ−Ｖ矢視断面図である。図５及び図６に示したパワー半導体モジュール１０１は、絶縁基板１０２に半導体チップ１０６が搭載されている。絶縁基板１０２は、絶縁板１０３と、絶縁板１０３の一方の主面に形成された回路板１０４と、絶縁板１０３の他方の主面に形成された放熱板１０５とからなる。回路板１０４は、回路パターンを構成するように絶縁板１０３上に選択的に形成され、この回路板１０４に、半導体チップ１０６が、はんだ１０７により接合されている。 Some DC-DC converters use a power semiconductor module incorporating a diode chip.
FIG. 5 is a cross-sectional view of an example of such a power semiconductor module. FIG. 6 is a plan view of the power semiconductor module shown in FIG. 5 is a cross-sectional view taken along line VV in FIG. In the power semiconductor module 101 shown in FIGS. 5 and 6, a semiconductor chip 106 is mounted on an insulating substrate 102. The insulating substrate 102 includes an insulating plate 103, a circuit board 104 formed on one main surface of the insulating plate 103, and a heat radiating plate 105 formed on the other main surface of the insulating plate 103. The circuit board 104 is selectively formed on the insulating plate 103 so as to form a circuit pattern, and a semiconductor chip 106 is joined to the circuit board 104 by solder 107.

樹脂ケース１０９は絶縁基板１０２と接着剤１１０により接着されている。樹脂ケース１０９には、外部端子１１１ａ及び外部端子１１１ｂが一体的に設けられている。外部端子１１１ａの一端と、半導体チップ１０６とが、ボンディングワイヤ１１２ａにより、外部端子１１１ｂの一端と絶縁基板１０２の回路板１０４とが、１１２ｂによって電気的に接続されている。   The resin case 109 is bonded to the insulating substrate 102 with an adhesive 110. The resin case 109 is integrally provided with an external terminal 111a and an external terminal 111b. One end of the external terminal 111a and the semiconductor chip 106 are electrically connected by a bonding wire 112a, and one end of the external terminal 111b and the circuit board 104 of the insulating substrate 102 are electrically connected by 112b.

また、ボンディングワイヤ１１２ａとボンディングワイヤ１１２ｂが配線された樹脂ケース１０９内に、エポキシ樹脂等の絶縁性熱硬化性樹脂からなる封止材１１３が注入、固化されて、樹脂ケース１０９内の回路板１０４や半導体チップ１０６や外部端子１１１ａ、１１１ｂやボンディングワイヤ１１２ａ、１１２ｂ等を保護している。なお、図６では理解を容易にするために封止材１１３の図示を省略している。
上記構成を具備する半導体装置は、特許文献１に記載がある。 Further, a sealing material 113 made of an insulating thermosetting resin such as an epoxy resin is injected into the resin case 109 in which the bonding wire 112 a and the bonding wire 112 b are wired, and solidified, so that the circuit board 104 in the resin case 109 is solidified. In addition, the semiconductor chip 106, the external terminals 111a and 111b, the bonding wires 112a and 112b, and the like are protected. In FIG. 6, the sealing material 113 is not shown for easy understanding.
A semiconductor device having the above structure is described in Patent Document 1.

近年、絶縁基板の熱伝導率を高めて放熱効果を高めるために、絶縁基板を構成する絶縁板に、熱伝導性フィラーを含む有機絶縁板を用いたものがある。このような熱伝導性フィラーを含む有機絶縁板の熱膨張係数は比較的小さく、そのために、放熱板との熱膨張係数差が相対的に大きくなり、よって絶縁基板の初期反り量が大きくなる。   In recent years, in order to increase the thermal conductivity of an insulating substrate and enhance the heat dissipation effect, there is one in which an organic insulating plate containing a heat conductive filler is used as an insulating plate constituting the insulating substrate. The organic insulating plate containing such a heat conductive filler has a relatively small thermal expansion coefficient, and therefore, the difference in thermal expansion coefficient from the heat radiating plate is relatively large, thereby increasing the initial warpage of the insulating substrate.

また、パワー半導体モジュールの耐熱性、耐圧性を高めるために、封止材にエポキシ樹脂が用いられたものがある。エポキシ樹脂は硬化収縮率が大きいので、ケース内に封止材を注入し、固化した後は、封止材の収縮により樹脂ケースが中心に向けて引っ張られ、この樹脂ケースに接着している絶縁基板も同様に引っ張られて絶縁基板の反りが生じる。絶縁基板は、放熱板が冷却器に取り付けられるため、絶縁基板の反りを抑制することは、冷却器との密着性を向上させるために重要である。   Moreover, in order to improve the heat resistance and pressure resistance of a power semiconductor module, there is one in which an epoxy resin is used as a sealing material. Since the epoxy resin has a large cure shrinkage rate, after injecting the sealing material into the case and solidifying it, the resin case is pulled toward the center by the shrinkage of the sealing material, and the insulation that adheres to this resin case The substrate is also pulled in the same manner, causing warpage of the insulating substrate. Since the heat sink is attached to the cooler in the insulating substrate, suppressing the warpage of the insulating substrate is important for improving the adhesion to the cooler.

反りを低減する基板に関し、パターン形成された金属板の一主面と反対面側に平坦に樹脂が形成され、この樹脂の表面に凹部を設けたものがある（特許文献２）。また、パワー半導体装置に関し、金属ベースを複数枚に分割し、この金属ベース間に仕切り板を設けたものがある（特許文献３）。   With respect to a substrate for reducing warpage, there is a substrate in which a resin is formed flat on one surface opposite to a main surface of a patterned metal plate and a recess is provided on the surface of the resin (Patent Document 2). Further, there is a power semiconductor device in which a metal base is divided into a plurality of pieces and a partition plate is provided between the metal bases (Patent Document 3).

実用新案登録第３１９１１１２号Utility Model Registration No. 3191112 特開平１０−２７０８３０号公報JP-A-10-270830 特開平１０−９３０１６号公報Japanese Patent Laid-Open No. 10-93016

しかし、特許文献２、特許文献３は絶縁基板の反りの抑制について、なお改良の余地があった。
そこで、本発明は、絶縁基板の反りを適切な範囲に調整することのできる半導体装置を提供することを目的とする。 However, Patent Document 2 and Patent Document 3 still have room for improvement with respect to suppression of warpage of the insulating substrate.
Therefore, an object of the present invention is to provide a semiconductor device capable of adjusting the warpage of an insulating substrate within an appropriate range.

上記目的を達成するために以下のような半導体装置が提供される。
この半導体装置は、回路板、有機絶縁板及び放熱板を順次に積層してなる絶縁基板と、該絶縁基板の回路板に接合された半導体素子と、該絶縁基板と該半導体素子とを収容する樹脂ケースと、該樹脂ケースと一体的に成形され、一端が該樹脂ケースの内側に露出し他端が該樹脂ケースより外方に延出する外部端子と、該半導体素子のおもて面に形成された電極及び該絶縁基板の回路板の少なくとも一つに電気的に接続し、かつ、該外部端子の一端に電気的に接続するボンディングワイヤと、該樹脂ケースの内側に注入して固化され、該半導体素子、該絶縁基板及び該ボンディングワイヤを封止する熱硬化性樹脂よりなる封止材と、を備えている。該絶縁基板の放熱板に、該絶縁基板の長手方向の中央部において短手方向に沿って線状に溝が形成されていて、前記樹脂ケースが、前記封止材の仕切り板を備え、前記仕切り板が、前記絶縁基板の放熱板に形成された溝から該放熱板の厚さ方向の延長線上に位置する。 In order to achieve the above object, the following semiconductor device is provided.
The semiconductor device accommodates an insulating substrate formed by sequentially stacking a circuit board, an organic insulating plate, and a heat sink, a semiconductor element bonded to the circuit board of the insulating substrate, and the insulating substrate and the semiconductor element. A resin case, an external terminal formed integrally with the resin case, one end exposed inside the resin case and the other end extending outward from the resin case, and a front surface of the semiconductor element A bonding wire electrically connected to at least one of the formed electrode and the circuit board of the insulating substrate and electrically connected to one end of the external terminal, and injected into the resin case and solidified. And a sealing material made of a thermosetting resin for sealing the semiconductor element, the insulating substrate, and the bonding wire. In the heat sink of the insulating substrate, a groove is formed linearly along the short side direction in the central portion in the longitudinal direction of the insulating substrate, and the resin case includes the partition plate of the sealing material, A partition plate is positioned on an extension line in the thickness direction of the heat sink from a groove formed in the heat sink of the insulating substrate.

本発明によれば、絶縁基板の反りを調整できるようにして、平坦又は所定の範囲の若干の反り量に収めることができる。   According to the present invention, it is possible to adjust the warpage of the insulating substrate so as to be flat or within a certain amount of warpage within a predetermined range.

本発明の実施形態１のパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module of Embodiment 1 of this invention. 図１のパワー半導体モジュールの説明図である。It is explanatory drawing of the power semiconductor module of FIG. 本発明の実施形態２のパワー半導体モジュールの説明図である。It is explanatory drawing of the power semiconductor module of Embodiment 2 of this invention. 放熱板の厚さと絶縁基板の反りの目標値からの変位量との関係を示すグラフである。It is a graph which shows the relationship between the thickness of a heat sink, and the displacement amount from the target value of the curvature of an insulated substrate. 従来のパワー半導体モジュールの一例の断面図である。It is sectional drawing of an example of the conventional power semiconductor module. 図５のパワー半導体モジュールの平面図である。It is a top view of the power semiconductor module of FIG.

（実施形態１）
本発明の半導体装置の実施形態を、図面を用いて具体的に説明する。
本発明の実施形態１の半導体装置を図１に断面図で示す。本実施形態の半導体装置は、パワー半導体モジュール１として構成されたものである。絶縁基板２に複数の半導体チップ６が搭載されている。 (Embodiment 1)
Embodiments of a semiconductor device of the present invention will be specifically described with reference to the drawings.
A semiconductor device according to Embodiment 1 of the present invention is shown in a sectional view in FIG. The semiconductor device of this embodiment is configured as a power semiconductor module 1. A plurality of semiconductor chips 6 are mounted on the insulating substrate 2.

絶縁基板２は、有機絶縁板３と、有機絶縁板３の一方の主面に形成された回路板４と、有機絶縁板３の他方の主面に形成された放熱板５とからなる。換言すれば、絶縁基板２は回路板４、有機絶縁板３及び放熱板５を順次に積層してなる。絶縁基板２は、略長方形の平面形状を有している。   The insulating substrate 2 includes an organic insulating plate 3, a circuit board 4 formed on one main surface of the organic insulating plate 3, and a heat radiating plate 5 formed on the other main surface of the organic insulating plate 3. In other words, the insulating substrate 2 is formed by sequentially laminating the circuit board 4, the organic insulating board 3, and the heat sink 5. The insulating substrate 2 has a substantially rectangular planar shape.

有機絶縁板３は、エポキシ樹脂等の絶縁性を有する樹脂よりなる。有機絶縁板３は、熱伝導率を向上させるために、フィラーを含むことが好ましい。フィラーの有無やフィラー量の多寡により絶縁基板２の反りの程度は異なる。したがって、反りの調整をフィラー量の調整によって行うことは可能である。しかし、有機絶縁板３に添加するフィラー量は熱伝導のために好ましい量とし、あわせて、後述するように放熱板５に溝５ａ、５ｂを形成することにより反りの調整を行う方が、高い放熱性を維持しながら反りを調整できるので好ましい。
回路板４は、一例では銅箔よりなり、回路パターンを構成するように有機絶縁板３上に選択的に形成されている。この回路板４に、半導体チップ６が、はんだ７により接合されて電気的かつ機械的に接続している。もっとも、回路板４と半導体チップ６との接合は、はんだ７にはんだに限られず、銀ペースト等の金属ペーストを用いた焼結材でもよい。回路板４には、半導体チップ６の他にコンデンサチップ８が取り付けられている。 The organic insulating plate 3 is made of an insulating resin such as an epoxy resin. The organic insulating plate 3 preferably contains a filler in order to improve the thermal conductivity. The degree of warping of the insulating substrate 2 varies depending on the presence or absence of the filler and the amount of filler. Therefore, it is possible to adjust the warpage by adjusting the amount of filler. However, the amount of filler added to the organic insulating plate 3 is a preferable amount for heat conduction, and in addition, it is higher to adjust the warp by forming grooves 5a and 5b in the heat radiating plate 5 as described later. This is preferable because warpage can be adjusted while maintaining heat dissipation.
The circuit board 4 is made of copper foil, for example, and is selectively formed on the organic insulating board 3 so as to form a circuit pattern. A semiconductor chip 6 is joined to the circuit board 4 by solder 7 and is electrically and mechanically connected. However, the joining of the circuit board 4 and the semiconductor chip 6 is not limited to the solder 7 but may be a sintered material using a metal paste such as a silver paste. In addition to the semiconductor chip 6, a capacitor chip 8 is attached to the circuit board 4.

放熱板５は、図示しない冷却板に接続して半導体チップ６からの熱を伝える。放熱板５は、アルミニウムや銅などの熱伝導性の良好な金属板よりなる。
半導体チップ６は、本実施形態ではダイオードである。半導体チップ６の個数や種類は問わない。また、半導体チップ６は基板として単結晶シリコンの他、シリコンカーバイド（ＳｉＣ）やガリウムナイトライド（ＧａＮ）等のワイドバンドギャップ半導体を用いることもできる。 The heat radiating plate 5 is connected to a cooling plate (not shown) and transfers heat from the semiconductor chip 6. The heat sink 5 is made of a metal plate having good thermal conductivity such as aluminum or copper.
The semiconductor chip 6 is a diode in this embodiment. The number and type of semiconductor chips 6 are not limited. The semiconductor chip 6 can also use a wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) in addition to single crystal silicon as a substrate.

樹脂ケース９は中空（枠形状）の略直方体の箱型形状を有し、絶縁基板２と半導体チップ６とを収容する空間が形成されている。樹脂ケース９の底面と絶縁基板２の有機絶縁板３の周縁とが接着剤１０により接着されて、樹脂ケース９と絶縁基板との隙間をなくし、隙間から封止材１３が外部に漏れ出るのを防止している。樹脂ケース９は、好適にはポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）等の樹脂よりなる。樹脂ケース９には、リードよりなる外部端子１１ａおよび外部端子１１ｂが金型を用いたトランスファー成型によって一体的に設けられている。この外部端子１１ａおよび外部端子１１ｂの一端は、樹脂ケース９の内側で露出している。また、外部端子１１ａの一端と半導体チップ６とがボンディングワイヤ１２ａにより、外部端子１１ｂの一端と絶縁基板２の回路板４とが、ボンディングワイヤ１２ｂによって電気的に接続されている。   The resin case 9 has a hollow (frame shape), substantially rectangular parallelepiped box shape, and a space for accommodating the insulating substrate 2 and the semiconductor chip 6 is formed. The bottom surface of the resin case 9 and the peripheral edge of the organic insulating plate 3 of the insulating substrate 2 are bonded by the adhesive 10, eliminating the gap between the resin case 9 and the insulating substrate, and the sealing material 13 leaks out from the gap. Is preventing. The resin case 9 is preferably made of a resin such as polyphenylene sulfide resin (PPS resin). The resin case 9 is integrally provided with external terminals 11a and external terminals 11b made of leads by transfer molding using a mold. One end of the external terminal 11 a and the external terminal 11 b is exposed inside the resin case 9. In addition, one end of the external terminal 11a and the semiconductor chip 6 are electrically connected by a bonding wire 12a, and one end of the external terminal 11b and the circuit board 4 of the insulating substrate 2 are electrically connected by a bonding wire 12b.

また、ボンディングワイヤ１２ａとボンディングワイヤ１２ｂが配線された後の樹脂ケース９の上端部の開口から、エポキシ樹脂やウレタン樹脂等の絶縁性熱硬化性樹脂からなる封止材１３が注入され、さらに固化されて、樹脂ケース９内の回路板４や半導体チップ６や外部端子１１ａ、１１ｂやボンディングワイヤ１２ａ、１２ｂ等を保護している。   A sealing material 13 made of an insulating thermosetting resin such as epoxy resin or urethane resin is injected from the opening at the upper end of the resin case 9 after the bonding wire 12a and the bonding wire 12b are wired, and further solidified. Thus, the circuit board 4, the semiconductor chip 6, the external terminals 11a and 11b, the bonding wires 12a and 12b, etc. in the resin case 9 are protected.

図２（ａ）に図１のパワー半導体モジュール１の平面図を、図２（ｂ）に図２（ａ）のｂ−ｂ線で切断した断面図を、図２（ｃ）に図１のパワー半導体モジュール１の背面図をそれぞれ示す。なお、図１は、図２（ａ）のＩ−Ｉ矢視断面図であり、図２（ｂ）は図２（ａ）のIIb−IIb矢視断面図である。また図２（ａ）及び図２（ｂ）では理解を容易にするために封止材１３の図示を省略している。本実施形態のパワー半導体モジュール１は、絶縁基板２の放熱板５に、その長手方向の中央部から短手方向に線状に延びる溝５ａを有している。また、短手方向の中央部から長手方向に線状に延びる溝５ｂを有している。   2A is a plan view of the power semiconductor module 1 of FIG. 1, FIG. 2B is a cross-sectional view taken along line bb of FIG. 2A, and FIG. The rear view of the power semiconductor module 1 is shown, respectively. 1 is a cross-sectional view taken along the line II in FIG. 2A, and FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. 2A and 2B, the sealing material 13 is not shown for easy understanding. The power semiconductor module 1 of the present embodiment has a groove 5a that extends linearly from the center in the longitudinal direction to the heat sink 5 of the insulating substrate 2 in the lateral direction. Moreover, it has the groove | channel 5b extended linearly in a longitudinal direction from the center part of a transversal direction.

溝５ａ、溝５ｂの作用効果について説明する。パワー半導体モジュール１が組み立てられたときに、絶縁基板２は、ほぼ平坦又は外側に凸になるような若干の反りを有していることが好ましい。また、外側に向かって凸になるときの反り量は、所定の範囲の若干量に収まることが好ましい。かかる絶縁基板２の反りに関して、絶縁基板２の製造法について説明すると、パワー半導体モジュール１に組み立てられる前の絶縁基板２は、回路板４と、有機絶縁板３と、放熱板５とを順次に積層し、熱プレスにより圧着することにより製造される。製造された絶縁基板２は、有機絶縁板３の線膨張係数と放熱板５の線膨張係数とに相違があるため、望ましい形状の反りを有していない場合がある。例えば、有機絶縁板３に含まれ得るフィラーの有無（添加量）や、放熱板５の材質によっては、パワー半導体モジュール１が組み立てられたときに外側に凹になるような反り（これを「逆反り」という。）が生じることさえある。   The effects of the grooves 5a and 5b will be described. When the power semiconductor module 1 is assembled, the insulating substrate 2 preferably has a slight warp that is substantially flat or convex outward. Further, it is preferable that the amount of warping when convexing outward falls within a certain amount within a predetermined range. Regarding the warpage of the insulating substrate 2, the manufacturing method of the insulating substrate 2 will be described. The insulating substrate 2 before being assembled into the power semiconductor module 1 includes the circuit board 4, the organic insulating board 3, and the heat sink 5 in order. It is manufactured by laminating and pressing by hot pressing. The manufactured insulating substrate 2 has a difference between the linear expansion coefficient of the organic insulating plate 3 and the linear expansion coefficient of the heat radiating plate 5, and thus may not have a desired shape of warpage. For example, depending on the presence / absence (addition amount) of filler that can be included in the organic insulating plate 3 and the material of the heat sink 5, the warp that is concave outward when the power semiconductor module 1 is assembled (this is referred to as “reverse anti-reverse” May even occur).

この点、本実施形態のパワー半導体モジュール１は、絶縁基板２の放熱板５に溝５ａ、５ｂが形成されていることから、有機絶縁板３の線膨張係数と放熱板５の線膨張係数との相違による反り量を減少させることができる。また、放熱板５に溝５ａ、５ｂが形成されていることにより、放熱板５の曲げ剛性を下げ、これによりパワー半導体モジュール１の組み立て時において樹脂ケース９に注入した封止材１３が固化するときの収縮による反りを所定量の範囲に調整するのを容易にできる。   In this respect, in the power semiconductor module 1 of the present embodiment, since the grooves 5a and 5b are formed in the heat radiating plate 5 of the insulating substrate 2, the linear expansion coefficient of the organic insulating plate 3 and the linear expansion coefficient of the heat radiating plate 5 are It is possible to reduce the amount of warping due to the difference. Further, since the grooves 5a and 5b are formed in the heat radiating plate 5, the bending rigidity of the heat radiating plate 5 is lowered, thereby solidifying the sealing material 13 injected into the resin case 9 when the power semiconductor module 1 is assembled. It is possible to easily adjust the warp due to shrinkage to a predetermined range.

絶縁基板２の反りは、長手方向ばかりでなく短手方向においても生じる。したがって、本実施形態のパワー半導体モジュール１は、溝５ａばかりでなく、溝５ｂを有している。
溝５ａは、絶縁基板２の長手方向の中央部であることが好ましい。中央部は、必ずしも長手方向を二等分する真中の位置に限られない。長手方向を中央部と端部とに分類したときの中央部に溝５ａが位置していればよい。溝５ａは、絶縁基板２のサイズにもよるが、１本あれば十分であるが、中央部に２本以上を有していてもよい。
溝５ｂは、絶縁基板２の短手方向の中央部であることが好ましい。中央部は、必ずしも短手方向を二等分する真中の位置に限られない。短手方向を中央部と端部とに分類したときの中央部に溝５ｂが位置していればよい。溝５ｂは、絶縁基板２のサイズにもよるが、１本あれば十分であるが、中央部に２本以上を有していてもよい。 Warpage of the insulating substrate 2 occurs not only in the longitudinal direction but also in the lateral direction. Therefore, the power semiconductor module 1 of the present embodiment has not only the groove 5a but also the groove 5b.
The groove 5a is preferably a central portion in the longitudinal direction of the insulating substrate 2. The central portion is not necessarily limited to the middle position that bisects the longitudinal direction. The groove 5a should just be located in the center part when classifying a longitudinal direction into a center part and an edge part. Although one groove 5a is sufficient although it depends on the size of the insulating substrate 2, two or more grooves 5a may be provided in the central portion.
The groove 5b is preferably the central portion of the insulating substrate 2 in the short direction. The central portion is not necessarily limited to the middle position that bisects the short direction. It suffices if the groove 5b is located in the center when the short direction is classified into the center and the end. Although one groove 5b is sufficient although it depends on the size of the insulating substrate 2, two or more grooves 5b may be provided in the central portion.

溝５ａ、溝５ｂの断面形状は、図２（ｂ）に示すようにＶ溝とすることができる。Ｖ溝に限られず、Ｕ溝でもよい。溝５ａ、溝５ｂを形成するための加工方法は特に問わないが、エンドミル等による切削加工を実施することができる。
溝５ａ、溝５ｂの幅、すなわち、放熱板５の表面における溝５ａ、溝５ｂの開口の幅は、加工工具によるが、例えば１ｍｍ以下とすることができる。 The cross-sectional shapes of the grooves 5a and 5b can be V-grooves as shown in FIG. The groove is not limited to a V groove, and may be a U groove. The processing method for forming the grooves 5a and 5b is not particularly limited, but cutting with an end mill or the like can be performed.
The widths of the grooves 5a and 5b, that is, the widths of the openings of the grooves 5a and 5b on the surface of the heat radiating plate 5, depending on the processing tool, can be set to 1 mm or less, for example.

溝５ａ、溝５ｂの深さ、すなわち放熱板５の表面から溝５ａ、溝５ｂの最深部までの厚み方向の距離は、絶縁基板２の曲げ強度を考慮して放熱板５の厚さの２０〜５０％程度とすることが好ましい。
溝５ａ、溝５ｂは、有機絶縁板３に対向する側の放熱板５の表面に形成してもよい。この場合、熱プレスにより有機絶縁板３と圧着する前に、放熱板５の表面に溝５ａ、溝５ｂを形成しておく。 The depth of the grooves 5a and 5b, that is, the distance in the thickness direction from the surface of the heat sink 5 to the deepest portion of the grooves 5a and 5b is 20 times the thickness of the heat sink 5 in consideration of the bending strength of the insulating substrate 2. It is preferable to be about ˜50%.
The groove 5 a and the groove 5 b may be formed on the surface of the heat radiating plate 5 on the side facing the organic insulating plate 3. In this case, the groove 5a and the groove 5b are formed on the surface of the heat radiating plate 5 before being bonded to the organic insulating plate 3 by hot pressing.

図１に示す本実施形態のパワー半導体モジュールは、樹脂ケース９に、封止材１３を仕切る仕切り板９ａ、９ｂを備えている。仕切り板９ａは、樹脂ケース９の長手方向の中央部において短手方向に沿って延びるものであり、仕切り板９ｂは、短手方向の中央部において長手方向に沿って延びるものである。   The power semiconductor module of this embodiment shown in FIG. 1 includes partition plates 9 a and 9 b that partition the sealing material 13 in the resin case 9. The partition plate 9a extends along the short direction at the center portion in the longitudinal direction of the resin case 9, and the partition plate 9b extends along the longitudinal direction at the center portion in the short direction.

本実施形態のパワー半導体モジュール１は、仕切り板９ａ、９ｂにより、４つの仕切られた区画を備えている。仕切られた区画ごとに封止材１３が固化する。したがって、封止材１３が収縮するときのエリアが分割されているので、絶縁基板２に作用する圧縮力が、仕切り板を有しない場合に比べて小さくなる。したがって、絶縁基板２の反り量を減少させることができ、また、絶縁基板２が過度に反ることを抑制して、反りを所定量の範囲に調整するのを容易にできる。   The power semiconductor module 1 according to the present embodiment includes four partitions divided by partition plates 9a and 9b. The sealing material 13 is solidified for each partitioned section. Therefore, since the area when the sealing material 13 contracts is divided, the compressive force acting on the insulating substrate 2 is smaller than when the partition plate is not provided. Therefore, the amount of warping of the insulating substrate 2 can be reduced, and the warping of the insulating substrate 2 can be easily controlled by suppressing the insulating substrate 2 from being excessively warped.

仕切り板９ａ、９ｂは、樹脂ケース９と同じ材料により、トランスファー成型により樹脂ケース９と同時に成形される。仕切り板９ａ、９ｂの幅は、金型で成形可能なサイズとして１〜２ｍｍ幅程度でよい。   The partition plates 9a and 9b are formed simultaneously with the resin case 9 by transfer molding using the same material as the resin case 9. The width of the partition plates 9a and 9b may be about 1 to 2 mm as a size that can be molded by a mold.

仕切り板９ａ、９ｂによる樹脂ケース内の封止材１３の区分けは、なるべく仕切り板９ａ、９ｂにより区分けされた各封止材１３の収縮が同程度になるようにするのがよい。図１及び図２に示すパワー半導体モジュール１は、封止材１３が仕切り板９ａ、９ｂにより四分割されるが、分割数は４個に限られない。   As for the partitioning of the sealing material 13 in the resin case by the partition plates 9a and 9b, the shrinkage of the sealing materials 13 partitioned by the partition plates 9a and 9b is preferably as much as possible. In the power semiconductor module 1 shown in FIGS. 1 and 2, the sealing material 13 is divided into four parts by the partition plates 9a and 9b, but the number of divisions is not limited to four.

仕切り板９ａ、９ｂは、半導体チップ６やボンディングワイヤ１２ａの大きさや配置に応じて、半導体チップ６及びボンディングワイヤ１２ａを避けるように設けられている。図示した例では、４つの区画それぞれに、半導体チップ６およびボンディングワイヤ１２ａと、ボンディングワイヤ１２ｂのいずれかが収容されている。
また、仕切り板９ｂは、半導体チップ６とボンディングワイヤ１２ｂとの間において、半導体チップ６寄りに設けると、半導体チップ６を接合しているはんだ７のフィレット部を起点とした樹脂剥離の進展を抑制して信頼性を高めることができる。もっとも、半導体チップ６のおもて面に形成された電極にボンディングワイヤ１２ａを接続するワイヤボンダが、仕切り板９ｂに干渉するのは避けなければならない。したがって、仕切り板９ｂは、作製上の観点からワイヤボンダが仕切りに干渉しない限度で、半導体チップ６に近づけた位置に設けることが、信頼性を高めるために好ましい。 The partition plates 9a and 9b are provided so as to avoid the semiconductor chip 6 and the bonding wire 12a according to the size and arrangement of the semiconductor chip 6 and the bonding wire 12a. In the illustrated example, one of the semiconductor chip 6, the bonding wire 12a, and the bonding wire 12b is accommodated in each of the four sections.
Further, when the partition plate 9b is provided near the semiconductor chip 6 between the semiconductor chip 6 and the bonding wire 12b, the progress of the resin peeling from the fillet portion of the solder 7 joining the semiconductor chip 6 is suppressed. And can improve reliability. However, it must be avoided that the wire bonder connecting the bonding wire 12a to the electrode formed on the front surface of the semiconductor chip 6 interferes with the partition plate 9b. Therefore, it is preferable to provide the partition plate 9b at a position close to the semiconductor chip 6 as far as the wire bonder does not interfere with the partition from the viewpoint of manufacturing.

仕切り板９ａ、９ｂと絶縁基板２とは、接着剤により接着することが好ましい。もっとも、仕切り板９ａ、９ｂにより樹脂ケース９内の封止材１３がほぼ分離されていれば必ずしも接着されなくてもよい。   The partition plates 9a and 9b and the insulating substrate 2 are preferably bonded with an adhesive. However, as long as the sealing material 13 in the resin case 9 is substantially separated by the partition plates 9a and 9b, it does not necessarily have to be bonded.

仕切り板９ａ、９ｂは、好適には絶縁基板２の放熱板５の溝５ａ、５ｂから放熱板５の厚さ方向の延長線上に位置するように設ける。換言すれば、パワー半導体モジュール１を上方からみて、仕切り板９ａ、９ｂの位置を、溝５ａ、５ｂの位置と一致させる。仕切り板９ａ、９ｂと溝５ａ、５ｂは有機絶縁板３を挟んで対向している。このことにより、封止材１３の収縮と絶縁基板２の反りとを調整して、絶縁板の反り量を適切な範囲に調整することができる。   The partition plates 9 a and 9 b are preferably provided so as to be located on the extended line in the thickness direction of the heat sink 5 from the grooves 5 a and 5 b of the heat sink 5 of the insulating substrate 2. In other words, when the power semiconductor module 1 is viewed from above, the positions of the partition plates 9a and 9b are made to coincide with the positions of the grooves 5a and 5b. The partition plates 9a and 9b and the grooves 5a and 5b face each other with the organic insulating plate 3 interposed therebetween. Thereby, the shrinkage of the sealing material 13 and the warp of the insulating substrate 2 can be adjusted, and the warp amount of the insulating plate can be adjusted to an appropriate range.

仕切り板９ａ、９ｂの上端は、樹脂ケース９の上端と同一平面に位置することが好ましい、換言すれば仕切り板９ａ、９ｂの高さは、樹脂ケース９の側壁の高さと同じとすることである。このことにより、封止材１３を仕切り板９ａ、９ｂの上端近傍まで注入することができ、よって封止材１３によるボンディングワイヤ１２ａ、１２ｂの絶縁性能を高く維持することができる。また、仕切り板９ａ、９ｂの上端が、樹脂ケース９の上端と同一平面に位置することにより、パワー半導体モジュール１の上に、他の部品を載置することができる。   It is preferable that the upper ends of the partition plates 9a and 9b are located in the same plane as the upper end of the resin case 9. In other words, the height of the partition plates 9a and 9b is the same as the height of the side wall of the resin case 9. is there. As a result, the sealing material 13 can be injected to the vicinity of the upper ends of the partition plates 9a and 9b, so that the insulation performance of the bonding wires 12a and 12b by the sealing material 13 can be maintained high. In addition, since the upper ends of the partition plates 9 a and 9 b are positioned on the same plane as the upper end of the resin case 9, other components can be placed on the power semiconductor module 1.

（実施形態２）
図３に本発明の実施形態２の半導体装置の平面図（図３（ａ））及び断面図（図３（ｂ））で示す。なお、図３（ｂ）は図３（ａ）のIIIb−IIIb矢視断面図である。また、図３（ｂ）では理解を容易にするために封止材１３の図示を省略している。また、図３において、図１及び図２に示したのと同じ部材については図１、図２と同一の符号を付している。したがって、本実施形態において、実施形態１のパワー半導体モジュール１と同一部材についての重複する説明は省略する。 (Embodiment 2)
FIG. 3 is a plan view (FIG. 3A) and a cross-sectional view (FIG. 3B) of the semiconductor device according to the second embodiment of the present invention. FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb in FIG. Further, in FIG. 3B, the sealing material 13 is not shown for easy understanding. In FIG. 3, the same members as those shown in FIGS. 1 and 2 are denoted by the same reference numerals as those in FIGS. Therefore, in this embodiment, the overlapping description about the same member as the power semiconductor module 1 of Embodiment 1 is abbreviate | omitted.

本実施形態のパワー半導体モジュール２１は、樹脂ケース９が、当該樹脂ケース９の上面から部分的に突出する突起部９ｃを有している。突起部９ｃは、樹脂ケース９の上面の一つの角部において樹脂ケース９の長手方向及び短手方向に沿って当該角部に隣接する位置にそれぞれ一つずつと、長手方向の一辺に沿って二個が形成されている。   In the power semiconductor module 21 of the present embodiment, the resin case 9 has a protruding portion 9 c that partially protrudes from the upper surface of the resin case 9. The protrusions 9c are arranged at one corner on the upper surface of the resin case 9 at positions adjacent to the corner along the longitudinal and short sides of the resin case 9, and along one side in the longitudinal direction. Two are formed.

突起部９ｃを有することにより、封止材１３を樹脂ケース９の上面まで満たされるような量で注入することができる。これにより封止材１３による絶縁性を十分に確保することができる。また、封止材１３の注入時、又は封止材１３が注入された後であって固化前の搬送時に、樹脂ケース９の上面に封止材１３が乗り上げた場合であっても、封止材１３は、突起部９ｃの側面に回り込み上面には乗り上げない。したがって、本実施形態のパワー半導体モジュール２１は、外観不良にならない。また、封止材１３を注入するときの作業性を向上させることができる。更に、樹脂ケース９の上面の突起部９ｃの上面に封止材１３が乗り上げないことから、樹脂ケース９上に蓋や部品を載置するための平板を取り付けた場合であっても、これらとの接着性の低下を招くことはない。   By having the protruding portion 9 c, the sealing material 13 can be injected in such an amount as to fill the upper surface of the resin case 9. Thereby, the insulation by the sealing material 13 can be sufficiently ensured. Further, even when the sealing material 13 rides on the upper surface of the resin case 9 during the injection of the sealing material 13 or after the sealing material 13 is injected and transported before solidification, the sealing material 13 is sealed. The material 13 goes around the side surface of the protruding portion 9c and does not ride on the upper surface. Therefore, the power semiconductor module 21 of this embodiment does not have a poor appearance. Moreover, workability | operativity when inject | pouring the sealing material 13 can be improved. Furthermore, since the sealing material 13 does not run on the upper surface of the protrusion 9c on the upper surface of the resin case 9, even when a flat plate for mounting a lid or a part is mounted on the resin case 9, This does not cause a decrease in adhesiveness.

突起部９ｃの数は、蓋を平坦に支持できるという観点から、最低３個があればよい。もっとも、樹脂ケース９の寸法精度や突起部９ｃの高さの精度を考慮すると、確実に支持できるように図３に示したように角部に隣接しケース９の長手方向及び短手方向に沿ったそれぞれに突起部９ｃを有することが好ましい。   The number of the protrusions 9c may be at least three from the viewpoint that the lid can be supported flat. However, in consideration of the dimensional accuracy of the resin case 9 and the accuracy of the height of the protrusion 9c, it is adjacent to the corner portion along the longitudinal direction and the short direction of the case 9 as shown in FIG. In addition, it is preferable that each has a protrusion 9c.

また、突起部９ｃの位置は、ボンディングワイヤ１２ａおよびボンディングワイヤ１２ｂをワイヤボンディングする際に、押さえ治具と干渉しない位置とすることが望ましい。   Further, it is desirable that the position of the protruding portion 9c is a position that does not interfere with the pressing jig when the bonding wire 12a and the bonding wire 12b are wire bonded.

樹脂ケース９の上面からの突起部９ｃの高さは、封止材１３が上面に乗り上げた場合であっても突起部９ｃには乗り上げない高さとして、０．１〜１ｍｍ程度あれば十分である。   The height of the protruding portion 9c from the upper surface of the resin case 9 is sufficient if it is about 0.1 to 1 mm as a height that does not ride on the protruding portion 9c even when the sealing material 13 rides on the upper surface. is there.

実施形態１のパワー半導体モジュール１において、絶縁基板２の放熱板５にアルミニウム板を用い、この放熱板の厚さと絶縁基板の反りの目標値からの変位量との関係をグラフにした。その結果を図４に示す。
放熱板５の厚さが厚くなるほど、単位長当たりの反り量が小さくなる。そして、本実施形態１では、仕切り板９ａ、９ｂが設けられて封止材１３のエリアを分割するとともに、放熱板５には溝５ａ、５ｂが形成されているから、封止材１３の硬化収縮率を見掛け上小さくすることができていて、目標値からの変位量を小さく調整できる。図４では、目標値からの変位量を２〜２．５割低減することができた。 In the power semiconductor module 1 of the first embodiment, an aluminum plate is used as the heat sink 5 of the insulating substrate 2, and the relationship between the thickness of the heat sink and the amount of displacement from the target value of the warp of the insulating substrate is graphed. The result is shown in FIG.
As the thickness of the heat sink 5 increases, the amount of warpage per unit length decreases. And in this Embodiment 1, since partition plate 9a, 9b is provided and the area of the sealing material 13 is divided | segmented, since the groove | channel 5a, 5b is formed in the heat sink 5, hardening of the sealing material 13 is carried out. The shrinkage rate can be apparently reduced, and the amount of displacement from the target value can be adjusted small. In FIG. 4, the amount of displacement from the target value could be reduced by 20 to 2.5%.

１ パワー半導体モジュール
２ 絶縁基板
３ 有機絶縁板
４ 回路板
５ 放熱板
５ａ、５ｂ 溝
６ 半導体チップ
９ 樹脂ケース
９ａ、９ｂ 仕切り板
９ｃ 突起部
１１ａ、１１ｂ 外部端子
１２ａ、１２ｂ ボンディングワイヤ
１３ 封止材 DESCRIPTION OF SYMBOLS 1 Power semiconductor module 2 Insulation board 3 Organic insulation board 4 Circuit board 5 Heat sink 5a, 5b Groove 6 Semiconductor chip 9 Resin case 9a, 9b Partition plate 9c Protrusion part 11a, 11b External terminal 12a, 12b Bonding wire 13 Sealing material

Claims (5)

放熱板、有機絶縁板及び回路板を順次に積層してなる絶縁基板と、
該絶縁基板の回路板に接合された半導体素子と、
該絶縁基板と該半導体素子とを収容する樹脂ケースと、
該樹脂ケースと一体的に成形され、一端が該樹脂ケースの内側に露出し他端が該樹脂ケースより外方に延出する外部端子と、
該半導体素子のおもて面に形成された電極及び該絶縁基板の回路板の少なくとも一つに電気的に接続し、かつ、該外部端子の一端に電気的に接続するボンディングワイヤと、
該樹脂ケースの内側に注入されて固化され、該半導体素子、該絶縁基板及び該ボンディングワイヤを封止する熱硬化性樹脂よりなる封止材と、
を備え、
該絶縁基板の放熱板に、該絶縁基板の長手方向の中央部において短手方向に沿って線状に溝が形成されていて、
前記樹脂ケースが、前記封止材の仕切り板を備え、前記仕切り板が、前記絶縁基板の放熱板に形成された溝から該放熱板の厚さ方向の延長線上に位置する
ことを特徴とする半導体装置。 An insulating substrate formed by sequentially laminating a heat sink, an organic insulating plate, and a circuit board;
A semiconductor element bonded to the circuit board of the insulating substrate;
A resin case for housing the insulating substrate and the semiconductor element;
An external terminal formed integrally with the resin case, one end exposed to the inside of the resin case and the other end extending outward from the resin case;
A bonding wire electrically connected to at least one of an electrode formed on the front surface of the semiconductor element and a circuit board of the insulating substrate, and electrically connected to one end of the external terminal;
A sealing material made of a thermosetting resin that is injected and solidified inside the resin case and seals the semiconductor element, the insulating substrate, and the bonding wire;
With
In the heat sink of the insulating substrate, a groove is formed in a linear shape along the short direction in the central portion in the longitudinal direction of the insulating substrate ,
The resin case is provided with a partition plate of the sealing member, wherein the partition plate, and characterized that you position from the insulation trenches formed in the heat sink substrate on the thickness direction of the extension line of the heat radiating plate Semiconductor device. 前記絶縁基板の放熱板に、更に前記絶縁基板の短手方向の中央部において長手方向に沿って線状に溝が形成されている請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a groove is formed in a linear shape along the longitudinal direction in a central portion of the insulating substrate in the short direction of the heat sink of the insulating substrate. 前記絶縁基板の放熱板の溝の深さが、該放熱板の厚さの２０〜５０％である請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein a depth of the groove of the heat sink of the insulating substrate is 20 to 50% of a thickness of the heat sink. 前記仕切り板の上端が、前記樹脂ケースの上端と同一平面に位置する請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein an upper end of the partition plate is located in the same plane as an upper end of the resin case. 前記樹脂ケースが、該樹脂ケースの上面から部分的に突出する突起部を有する請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the resin case has a protrusion partly protruding from an upper surface of the resin case.
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