JP6420079B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6420079B2 JP6420079B2 JP2014139876A JP2014139876A JP6420079B2 JP 6420079 B2 JP6420079 B2 JP 6420079B2 JP 2014139876 A JP2014139876 A JP 2014139876A JP 2014139876 A JP2014139876 A JP 2014139876A JP 6420079 B2 JP6420079 B2 JP 6420079B2
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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Description
したがって、このようなエレクトロマイグレーションを減らすための研究が活発に行われている。
また、本発明の一実施形態による半導体装置は、第1電圧が提供される第1パワーレールと、第1不純物領域に接続される第1ソース電極と、前記第1電圧と異なる第2電圧が提供される第2パワーレールと、第2不純物領域に接続される第2ソース電極と、前記第1不純物領域及び第2不純物領域上に第1方向に延長して形成されたゲート電極と、前記第1不純物領域上に形成された第1ドレイン電極と、前記第2不純物領域上に形成された第2ドレイン電極と、前記第1ドレイン電極と前記第2ドレイン電極に接続され、クローズドループを形成する連結配線と、を備え、前記第1ドレイン電極と前記第2ドレイン電極に接続され、U字状に形成された連結配線と、前記クローズドループを形成する連結配線と前記U字状に形成された連結配線に接続されるブリッジ配線をさらに含むことを特徴とする。
周辺回路1050は、SoCシステム1000が外部装置(例えば、メイン ボード)と円滑に接続するのに必要な環境を提供する。これによって、周辺回路1050はSoCシステム1000に接続される外部装置が互換可能なようにする多様なインターフェースを備える。
12 第1不純物領域
14 第2不純物領域
22 ゲート電極
24a 第1ソース電極
24b 第2ソース電極
26a 第1ドレイン電極
26b 第2ドレイン電極
32 ゲートコンタクト
34 パワーレールコンタクト
36 ドレインコンタクト
42 分配配線
44 第1パワーレール
46 第2パワーレール
52 入力コンタクト
62 入力配線
64 連結配線
Claims (19)
- 第1電圧が提供される第1パワーレールと、第1不純物領域に接続される第1ソース電極と、
前記第1電圧と異なる第2電圧が提供される第2パワーレールと、第2不純物領域に接続される第2ソース電極と、
前記第1不純物領域及び第2不純物領域上に第1方向に延長して形成されたゲート電極と、
前記第1不純物領域上に形成された第1ドレイン電極と、
前記第2不純物領域上に形成された第2ドレイン電極と、
前記第1ドレイン電極と前記第2ドレイン電極に接続され、クローズドループを形成する連結配線と、
ブリッジ(bridge)配線と、を備え、
前記連結配線は、
クローズドループを形成する第1の連結配線と、
前記第1の連結配線と分離してクローズドループを形成する第2の連結配線を含み、
前記ブリッジ配線は、前記第1の連結配線と前記第2の連結配線に接続されることを特徴とする半導体装置。 - 前記連結配線は、前記第1ソース電極及び第2ソース電極、ゲート電極、第1ドレイン電極及び第2ドレイン電極より高く形成されることを特徴とする請求項1に記載の半導体装置。
- 前記連結配線は、U字状に形成された第1連結配線と、前記第1方向に延長形成された第2連結配線を含み、
前記第2連結配線は、前記第1連結配線より高く形成されることを特徴とする請求項1に記載の半導体装置。 - 前記第1連結配線は、前記第1ドレイン電極及び第2ドレイン電極の一側に延長して形成された第3連結配線と、前記第1ドレイン電極及び第2ドレイン電極の他側に延長して形成された第4連結配線と、を含み、
前記第4連結配線は前記第3連結配線より高く形成されることを特徴とする請求項3に記載の半導体装置。 - 前記第1不純物領域はN型不純物領域を含み、
前記第2不純物領域はP型不純物領域を含むことを特徴とする請求項1に記載の半導体装置。 - 前記第1電圧は電源電圧を含み、
前記第2電圧は接地電圧を含むことを特徴とする請求項1に記載の半導体装置。 - 基板から突出し、前記第1方向と交差する第2方向に延長して形成されたアクティブフィンをさらに含み、
前記第1不純物領域及び第2不純物領域は前記アクティブフィン内に形成されることを特徴とする請求項1に記載の半導体装置。 - 前記ゲート電極と前記アクティブフィンとの間に形成されたゲート絶縁膜と、前記ゲート電極の一側に配置されたアクティブフィン上に形成されたスペーサをさらに含み、
前記ゲート絶縁膜は、前記スペーサの側壁に沿って上部に延長されることを特徴とする請求項7に記載の半導体装置。 - 前記ブリッジ配線は、前記第1の連結配線及び第2の連結配線より高く形成されることを特徴とする請求項1に記載の半導体装置。
- 第1電圧が提供される第1パワーレールと、第1不純物領域に接続される第1ソース電極と、
前記第1電圧と異なる第2電圧が提供される第2パワーレールと、第2不純物領域に接続される第2ソース電極と、
前記第1不純物領域及び第2不純物領域上に第1方向に延長して形成されたゲート電極と、
前記第1不純物領域上に形成された第1ドレイン電極と、
前記第2不純物領域上に形成された第2ドレイン電極と、
前記第1ドレイン電極と前記第2ドレイン電極に接続され、クローズドループを形成する連結配線と、を備え、
前記第1ドレイン電極と前記第2ドレイン電極に接続され、U字状に形成された連結配線と、
前記クローズドループを形成する連結配線と前記U字状に形成された連結配線に接続されるブリッジ配線をさらに含むことを特徴とする半導体装置。 - 第1トランジスタと、
前記第1トランジスタと異なる第2トランジスタと、
前記第1トランジスタ及び第2トランジスタの出力端と回路要素(circuit element)に接続され、クローズドループ(closed loop)を形成する連結配線と、
ブリッジ(bridge)配線と、を備え、
前記連結配線は、
クローズドループを形成する第1の連結配線と、
前記第1の連結配線と分離してクローズドループを形成する第2の連結配線を含み、
前記ブリッジ配線は、前記第1の連結配線と前記第2の連結配線に接続されることを特徴とする半導体装置。 - 前記第1トランジスタはPMOSトランジスタを含み、
前記第2トランジスタはNMOSトランジスタを含むことを特徴とする請求項11に記載の半導体装置。 - 前記第1トランジスタのソース電極には第1電圧が提供され、
前記第2トランジスタのソース電極には前記第1電圧と異なる第2電圧が提供されることを特徴とする請求項11に記載の半導体装置。 - 前記第1電圧は電源電圧を含み、
前記第2電圧は接地電圧を含むことを特徴とする請求項13に記載の半導体装置。 - 前記回路要素は、抵抗、キャパシタ、インダクタ、ダイオード、トランジスタのうち少なくとも一つを含むことを特徴とする請求項11に記載の半導体装置。
- 前記第1トランジスタと前記第2トランジスタは、
第1電圧が印加される第1パワーレールと前記第1電圧と異なる第2電圧が印加される第2パワーレールとの間に直列接続されることを特徴とする請求項11に記載の半導体装置。 - 前記第1トランジスタは、互いに並列連結された複数の第1トランジスタを含み、
前記第2トランジスタは、互いに並列連結された複数の第2トランジスタを含むことを特徴とする請求項16に記載の半導体装置。 - 前記第1電圧は電源電圧を含み、
前記第2電圧は接地電圧を含むことを特徴とする請求項16に記載の半導体装置。 - 前記半導体装置はインバータ(inverter)を含むことを特徴とする請求項11に記載の半導体装置。
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US201361845555P | 2013-07-12 | 2013-07-12 | |
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- 2014-06-26 DE DE102014212359.3A patent/DE102014212359B4/de active Active
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CN104282655A (zh) | 2015-01-14 |
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