JP6320546B2 - 演算増幅回路 - Google Patents
演算増幅回路 Download PDFInfo
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Description
ここで、前記出力増幅段は、
第1のpウェルが形成され、短絡されたゲートとドレインとが第1のノードに接続され、ソースが第2のノードに接続された第1のnMOSFETと、
第2のpウェルが形成され、ゲートが前記第1のノードに接続され、ドレインが第1の基準端子に接続され、ソースが前記出力端子に接続された第2のnMOSFETと、
第1のnウェルが形成され、短絡されたゲートとドレインとが第3のノードに接続され、ソースが前記第2のノードに接続された第1のpMOSFETと、
第2のnウェルが形成され、ゲートが前記第3のノードに接続され、ドレインが第2の基準端子に接続され、ソースが前記出力端子に接続された第2のpMOSFETと
を備える。
前記第1のpウェルと前記第2のpウェルとは、
第4のノードに接続され、
前記第1のnウェルと前記第2のnウェルとは、
第5のノードに接続され、
前記第4のノードと前記第5のノードとのうち少なくとも一方は、
前記出力端子に接続される。
以下では演算増幅回路200,演算増幅回路200−1を説明する。以下の説明では電圧を電圧<VOUT>のように表記し、端子を端子VOUTのように表記する。電圧<VOUT>は端子VOUTの電圧を意味する。また、端子の電圧は、端子の電位と同じ意味である。
図1は、実施の形態1の演算増幅回路200−1の前提となる、プッシュプル型ソースフォロワ回路を有する演算増幅回路200の回路構成を示す。プッシュプル型ソースフォロワ回路は図1の出力増幅段202の範囲202Aが対応する。演算増幅回路200は、非反転入力端子である差動入力端子VIP及び反転入力端子である差動入力端子VIM、バイアス入力端子VBIAS、出力端子VOUTを有する。演算増幅回路200は、差動増幅段201と、出力増幅段202とを備える。差動増幅段201は、差動入力端子VIPと差動入力端子VIMとの電位差を増幅し、第1の電圧<VA>を出力する。出力増幅段202は、差動増幅段201の出力する第1の電圧<VA>を増幅し、増幅した電圧を、出力端子VOUTから第2の電圧である出力電圧<VOUT>として出力する。
(2)第2のnMOSFET110及び第2のpMOSFET108は、ソースが出力端子VOUTに接続されている。
(3)第1のnMOSFET109は、第2のnMOSFET110のレプリカである。
(4)第1のpMOSFET107は、第2のpMOSFET108のレプリカである。
(5)第3のpMOSFET106は、差動増幅段201が出力する第1の電圧<VA>をゲートに受けて増幅する。
(6)第3のnMOSFET105は、バイアス入力端子VBIASから入力されるバイアス電圧をゲートに受けてバイアス電流を生成する。
(2)第1のpMOSFET107のゲート端子VGPは、第1のpMOSFET107のドレイン及び第3のnMOSFET105のドレインと接続される。
(3)第1のnMOSFET109及び第1のpMOSFET107のソースは、互いに接続される。
(4)第2のnMOSFET110及び第2のpMOSFET108は、ソースが出力端子VOUTに接続され、ゲートがゲート端子VGN及びゲート端子VGPに接続され、ドレインが、それぞれ電源端子VDD及び接地端子VSSに接続される。
(5)また、第1のnMOSFET109及び第2のnMOSFET110のウェル電位は、接地端子VSSから供給される。
(6)第1のpMOSFET107及び第2のpMOSFET108のウェル電位は、電源端子VDDから供給される。
<VG>=<VGN>−<VGP> 式(1)
すなわち、第1のnMOSFET109及び第1のpMOSFET107は、第2のnMOSFET110及び第2のpMOSFET108のレプリカとして機能することで、AB級動作を実現する。ここで、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のゲート幅をそれぞれW107、W108、W109、W110とし、ゲート長をそれぞれL107、L108、L109、L110とする。そして、以下に示す式(2)が成り立つ場合には、バイアス状態における第2のnMOSFET110及び第2のpMOSFET108に流れる電流は、第1のnMOSFET109及び第1のpMOSFET107に流れる電流のN倍となる。
(W108/L108)/(W107/L107)
=(W110/L110)/(W109/L109)
=N 式(2)
図3は、演算増幅回路200−1の回路図である。演算増幅回路200−1は、第1の電圧<VA>を出力する差動増幅段201の第1の電圧<VA>を増幅し、出力端子VOUTから増幅された電圧を第2の電圧として出力する出力増幅段202−1を備えている。図3の演算増幅回路200−1では、プッシュプル型ソースフォロワ回路は出力増幅段202−1の範囲202A−1が対応する。
(2)第2のnMOSFET110は第2のpウェルPW2が形成されている。第2のnMOSFET110は、ゲートが第1のノードN(1)に接続され、ドレインが第1の基準端子231に接続され、ソースが出力端子VOUTに接続される。図3では、第1の基準端子231は電源端子VDDが対応する。
(3)第1のpMOSFET107は第1のnウェルNW1が形成されている。第1のpMOSFET107は、短絡されたゲートとドレインとが第3のノードN(3)に接続され、ソースが第2のノードN(2)に接続されている。図3では、第3のノードN(3)は第1のpMOSFET107のゲート端子VGPが対応する。
(4)第2のpMOSFET108は第2のnウェルNW2が形成されている。第2のpMOSFET108は、ゲートが第3のノードN(3)に接続され、ドレインが第2の基準端子232に接続され、ソースが出力端子VOUTに接続されている。図3では、第2の基準端子232は接地端子VSSが対応する。図3では、第4のノードN(4)及び第5のノードN(5)は、出力端子VOUTが対応する。
(5)第1のpウェルPW1と第2のpウェルPW2とは、第4のノードN(4)に接続され、第1のnウェルNW1と第2のnウェルNW2とは、第5のノードN(5)に接続されている。
(6)第4のノードN(4)と第5のノードN(5)とのうち少なくとも一方は、出力端子VOUTに接続される。つまり、図3の場合は、第4のノードN(4)及び第5のノードN(5)は出力端子VOUTに接続しているが、この接続は例であり、第4のノードN(4)と第5のノードN(5)とのうち少なくとも一方が出力端子VOUTに接続すればよい。第4のノードN(4)のみが出力端子VOUTに接続する場合は、第5のノードN(5)は図1のように電源端子VDDに接続すればよい。一方、第5のノードN(5)のみが出力端子VOUTに接続する場合は、第4のノードN(4)は図1のように接地端子VSSに接続すればよい。
(7)第3のpMOSFET106は、ゲートが第6のノードN(6)に接続され、ドレインが第1のノードN(1)に接続され、ソースが第1の基準端子231に接続される。
図3では、第6のノードN(6)は、例えばpMOOSFET103のドレイン端子が対応する。
(8)第3のnMOSFET105は、ゲートが第7のノードN(7)に接続され、ドレインが第3のノードN(3)に接続され、ソースが第2の基準端子232に接続される。図3では、第7のノードN(7)は、バイアス入力端子VBIASが対応する。
(9)第6のノードN(6)と、第7のノードN(7)との一方は、第1の電圧<VA>が供給され、第6のノードN(6)と、第7のノードN(7)との他方は、バイアス電圧<VBIAS>が供給される。図3では、第6のノードN(6)に第1の電圧<VA>が供給され、第7のノードN(7)にバイアス電圧<VBIAS>が供給されるけれども、この供給は一例である。第6のノードN(6)にバイアス電圧<VBIAS>が供給され、第7のノードN(7)に第1の電圧<VA>が供給される構成でも構わない。この構成は図9で後述する。
図3に示す演算増幅回路200−1における第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のそれぞれのゲート幅及びゲート長について式(2)が成り立つとすると、次の式(3)、式(4)が成り立つ。
|<VGS107>|=|<VGS108>| 式(3)
|<VGS109>|=|<VGS110>| 式(4)
ここで、<VGS107>〜<VGS110>は、それぞれ、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のゲート―ソース間電圧である。レプリカである第1のpMOSFET107、レプリカである第1のnMOSFET109のソースが接続されるノードの電位を<VS>とすると、式(3)、式(4)より、式(5)が成り立つ。ここで<VOUT>は出力端子VOUTの電圧である。
<VS>=<VOUT> 式(5)
つまり、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のソース電位はいずれも出力端子VOUTの電圧に等しくなる。
したがって、第1のpMOSFET107と第2のpMOSFET108とのnウェルと、第1のnMOSFET109と第2のnMOSFET110とのpウェルとを出力端子VOUTに接続して電位を供給した場合、ソース―ウェル間の電位差はゼロとなるため、基板バイアス効果による閾値電圧の増加は抑制される。このため、図3に示す実施の形態1の演算増幅回路200−1は、図1の演算増幅回路200に対し、広い出力電圧範囲を有する。
次に、第1のpMOSFET107、第2のpMOSFET108、第1のnMOSFET109、第2のnMOSFET110のウェルのレイアウトの構成方法を示す。まず、第1のpMOSFET107及び第2のpMOSFET108の場合を説明する。
図9は、演算増幅回路200−2の回路図である。つまり、図9に示す演算増幅回路200−2のように、差動増幅段201−1は2つのpMOSFETを有する差動対211−1を備える構成とする。これに伴い、差動増幅段201−1は図3の差動増幅段201に対してMOSFETの極性が反対になっている。例えば図9では、図3の差動増幅段201のnMOSFET100に対して、対応するpMOSFETをpMOSFET100−1とした。このように差動増幅段201−1は図3の差動増幅段201のnMOSFETをpMOSFETに置き換え、pMOSFETをnMOSFETに置き換え、上下を反転した構成である。上下を反転した構成とは、言い換えれば、電源端子VDDと接地端子VSSとに関して、接続を上下逆にした構成である。図9に示すように、第3のnMOSFET105のゲートは出力電圧<VA>を受け、第3のpMOSFET106のゲートはバイアス電圧<VBIAS>を受ける構成としてもよい。
Claims (8)
- 第1の電圧を出力する差動増幅段の前記第1の電圧を増幅し、出力端子から増幅された電圧を出力する出力増幅段を備えた演算増幅回路において、
前記出力増幅段は、
第1のpウェルが形成され、短絡されたゲートとドレインとが第1のノードに接続され、ソースが第2のノードに接続された第1のnMOSFETと、
第2のpウェルが形成され、ゲートが前記第1のノードに接続され、ドレインが第1の基準端子に接続され、ソースが前記出力端子に接続された第2のnMOSFETと、
第1のnウェルが形成され、短絡されたゲートとドレインとが第3のノードに接続され、ソースが前記第2のノードに接続された第1のpMOSFETと、
第2のnウェルが形成され、ゲートが前記第3のノードに接続され、ドレインが第2の基準端子に接続され、ソースが前記出力端子に接続された第2のpMOSFETと
を備え、
前記第1のpウェルと前記第2のpウェルとは、
第4のノードに接続され、
前記第1のnウェルと前記第2のnウェルとは、
第5のノードに接続され、
前記第4のノードと前記第5のノードとのうち少なくとも一方は、
前記出力端子に接続された演算増幅回路。 - 前記出力増幅段は、さらに、
ゲートが第6のノードに接続され、ドレインが前記第1のノードに接続され、ソースが前記第1の基準端子に接続された第3のpMOSFETと、
ゲートが第7のノードに接続され、ドレインが前記第3のノードに接続され、ソースが前記第2の基準端子に接続された第3のnMOSFETと
を備え、
前記第6のノードと、前記第7のノードとの一方は、
前記第1の電圧が供給され、
前記第6のノードと、前記第7のノードとの他方は、
バイアス電圧が供給される請求項1に記載の演算増幅回路。 - 前記第1のnウェルと前記第2のnウェルとは、
互いに分離され、配線層によって前記第5のノードに接続された請求項1または2に記載の演算増幅回路。 - 前記第1のnウェルと前記第2のnウェルとは、
単一のnウェルによって単一の領域として形成され、配線層によって前記第5のノードに接続された請求項1または2に記載の演算増幅回路。 - 前記第1のpウェルと前記第2のpウェルとは、
第3のnウェルにより互いに分離され、配線層によって前記第4のノードに接続された請求項1〜4のいずれか一項に記載の演算増幅回路。 - 前記第1のpウェルと前記第2のpウェルとは、
単一のpウェルによって単一の領域として形成され、配線層によって前記第4のノードに接続された請求項1〜4のいずれか一項に記載の演算増幅回路。 - 前記差動増幅段は、
2つのnMOSFETを有する差動対を備えた請求項1〜6のいずれか一項に記載の演算増幅回路。 - 前記差動増幅段は、
2つのpMOSFETを有する差動対を備えた請求項1〜6のいずれか一項に記載の演算増幅回路。
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