JP6291792B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP6291792B2
JP6291792B2 JP2013225514A JP2013225514A JP6291792B2 JP 6291792 B2 JP6291792 B2 JP 6291792B2 JP 2013225514 A JP2013225514 A JP 2013225514A JP 2013225514 A JP2013225514 A JP 2013225514A JP 6291792 B2 JP6291792 B2 JP 6291792B2
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吉清 臼井
吉清 臼井
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Fuji Electric Co Ltd
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Description

この発明は、半導体集積回路チップを搭載した半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device on which a semiconductor integrated circuit chip is mounted and a method for manufacturing the same.

図７および図８は、従来の半導体装置５００の構成図であり、図７（ａ）は外形の上面図、図７（ｂ）は図７（ａ）のＸ−Ｘ線で切断した要部断面図、図７（ｃ）は図７（ａ）のＹ−Ｙ線で切断した要部断面図、図８（ａ）は図７（ａ）のエポキシ樹脂を外した内部を拡大したＡ部の要部平面図、図８（ｂ）は図８（ａ）のＸ−Ｘ線で切断した要部断面図である。   7 and 8 are configuration diagrams of a conventional semiconductor device 500. FIG. 7A is a top view of the outer shape, and FIG. 7B is a main portion cut along line XX of FIG. 7A. Sectional view, FIG. 7C is a cross-sectional view of the main part cut along line YY in FIG. 7A, and FIG. 8A is an enlarged view of part A with the epoxy resin removed in FIG. 7A. FIG. 8B is a cross-sectional view of the main part taken along line XX of FIG. 8A.

この半導体装置５００は、アイランド２（ダイパッド）と、リード端子１と、アイランド２に固着する高耐圧ＩＣチップ５および低耐圧の制御ＩＣチップ７を備える。高耐圧ＩＣチップ５および制御ＩＣチップ７とリード端子１を接続するボンディングワイヤ１０と、全体を封止するエポキシ樹脂１１とを備える。   The semiconductor device 500 includes an island 2 (die pad), a lead terminal 1, a high breakdown voltage IC chip 5 and a low breakdown voltage control IC chip 7 fixed to the island 2. A high-voltage IC chip 5 and a control IC chip 7 are provided with a bonding wire 10 for connecting the lead terminal 1 and an epoxy resin 11 for sealing the whole.

高耐圧ＩＣチップ５の裏面と制御ＩＣチップ７の裏面は導電性接着剤８を介してアイランド２に固着する。また、リード端子１の内グランド電位にあるＧＮＤリード端子１ａとアイランド２は接続されず、アイランド２は浮遊電位となる。   The back surface of the high voltage IC chip 5 and the back surface of the control IC chip 7 are fixed to the island 2 via the conductive adhesive 8. Further, the GND lead terminal 1a at the internal ground potential of the lead terminal 1 and the island 2 are not connected, and the island 2 becomes a floating potential.

高耐圧ＩＣチップ５の表面の図示しない電極パッドおよび制御ＩＣチップ７の表面の図示しない電極パッドはリード端子１とボンディングワイヤ１０で接続する。
図１７は、高耐圧ＩＣチップ５および制御ＩＣ７に形成される回路図である。これら回路により主回路電流を流すＭＯＳＦＥＴ２０１，２０２が駆動される。 An electrode pad (not shown) on the surface of the high voltage IC chip 5 and an electrode pad (not shown) on the surface of the control IC chip 7 are connected to the lead terminal 1 by a bonding wire 10.
FIG. 17 is a circuit diagram formed in the high voltage IC chip 5 and the control IC 7. These circuits drive MOSFETs 201 and 202 through which main circuit current flows.

高耐圧ＩＣチップ５は、レベルシフト回路５０１、ハイサイド駆動回路５０２を備えている。ハイサイド駆動回路５０２の電源はＶＢである。レベルシフト回路５０１はセット用のＭＯＳＦＥＴ（ＳＥＴ）とリセット用のＭＯＳＦＥＴ（ＲＥＳＥＴ）およびダイオードＤと抵抗Ｒで構成される。   The high breakdown voltage IC chip 5 includes a level shift circuit 501 and a high side drive circuit 502. The power source of the high side drive circuit 502 is VB. The level shift circuit 501 includes a set MOSFET (SET), a reset MOSFET (RESET), a diode D, and a resistor R.

制御ＩＣ７は、ローサイド駆動回路７０１と電源制御回路７０２を備えている。制御ＩＣ７に形成される回路の電源は、ＶＣＣである。この例では、電源制御回路７０２を備えたものについて示しているがこれに限ったものではない。外部からの信号に基づいてローサイド駆動回路７０１およびハイサイド駆動回路５０２への信号を出力する回路であればよい。   The control IC 7 includes a low side drive circuit 701 and a power supply control circuit 702. The power source of the circuit formed in the control IC 7 is VCC. In this example, the power supply control circuit 702 is shown, but the present invention is not limited to this. Any circuit that outputs signals to the low-side drive circuit 701 and the high-side drive circuit 502 based on an external signal may be used.

ＭＯＳＦＥＴ２０１，２０２は直列接続され、ＭＯＳＦＥＴ２０１のドレインに主回路電源Ｖｄｃが印加され、ＭＯＳＦＥＴ２０２のソースはグランド電位のＣＯＭに接続している。この２直列でインバータ回路の一つのアームを構成し、接続点Ｋは図示しないモータなどの負荷に接続する。この接続点Ｋと高耐圧ＩＣチップ５のＶＳ端子は接続する。ＶＢ端子（この端子の電圧はＶＢ）のグランドに対する電圧はＶＳ端子（この端子の電圧はＶＳ）の電圧（中間電位）にブートストラップコンデンサＣｂの電圧Ｅ（１５Ｖ程度）が加わった電圧である。   The MOSFETs 201 and 202 are connected in series, the main circuit power supply Vdc is applied to the drain of the MOSFET 201, and the source of the MOSFET 202 is connected to the ground potential COM. The two series form one arm of the inverter circuit, and the connection point K is connected to a load such as a motor (not shown). The connection point K and the VS terminal of the high voltage IC chip 5 are connected. The voltage with respect to the ground of the VB terminal (the voltage of this terminal is VB) is a voltage obtained by adding the voltage E (about 15 V) of the bootstrap capacitor Cb to the voltage (intermediate potential) of the VS terminal (the voltage of this terminal is VS).

ＭＯＳＦＥＴ２０１，２０２のオン・オフにより、ＶＳはグランド電位からＶｄｃまで振られる。
図９は、高耐圧ＩＣチップ５の要部断面図である。高耐圧ＩＣチップ５は、ｐ型基板１５の表面層に配置される第１ｎウェル領域１６、第２ｎウェル領域１７、第１ｐ領域１８、第２ｐ領域１９を備える。第１ｎウェル領域１６の表面層に配置されるｐウェル領域２０と、ｐウェル領域２０の表面層に配置されるｎドレイン領域２１、ｎソース領域２２、ｐコンタクト領域２３と、ポリシリコンのゲート電極２４を備える。第１ｎウェル領域１６の表面層に配置されるｐドレイン領域２５、ｐソース領域２６、ｎコンタクト領域２７と、ポリシリコンのゲート電極２８を備える。第１ｐ領域１８の表面層に配置されるｎソース領域２９、ゲート電極３０、第２ｎウェル領域１７の表面層に配置されるｎドレイン領域３１を備える。第１ｐ領域１８の表面層に配置されるｐコンタクト領域３２と、第２ｐ領域１９の表面層に配置されるｐコンタクト領域３３と、第１ｎウェル領域１６と第２ｎウェル領域１７に跨って配置されるｎコンタクト領域３４と、第１ｐ領域１８と第２ｐ領域１９に跨って配置されるｐコンタクト領域３５を備える。各ドレイン領域、各ソース領域、各ゲート電極に接続するドレイン電極Ｄ、ソース電極Ｓ、ゲート金属電極Ｇを備える。ｐコンタクタ領域およびｎコンタクト領域に接続する金属電極３６，３７，３８，３９，４０，４１，４２を備える。金属電極４０，４１はＶＳ、ＶＢに接続し、ソース電極Ｓを含む金属電極４２はＧＮＤに接続する。ＶＳはインバータ回路の中間電位、ＶＢはＶＳに昇圧電位（例えば、１５Ｖ程度）が加わったハイサイド側の第１ｎウェル領域１６の電位である。そのため、常時、ｐウェル領域２０と第１ｎウェル領域１６のｐｎ接合は逆バイアスされている。ｐ型基板１５は、第１ｐ領域１８および第２ｐ領域１９を介してグランド電位（ＧＮＤ）になっている。ｐ型基板１５は導電性接着剤８を介して浮遊電位にあるアイランド２に固着されている。この半導体装置５００は、レベルシフト、高耐圧終端領域（ＨＶＪＴ）、浮遊電位基準回路領域で構成される。 By turning on and off the MOSFETs 201 and 202, VS is swung from the ground potential to Vdc.
FIG. 9 is a cross-sectional view of the main part of the high voltage IC chip 5. The high breakdown voltage IC chip 5 includes a first n well region 16, a second n well region 17, a first p region 18, and a second p region 19 that are disposed on the surface layer of the p-type substrate 15. A p-well region 20 disposed in the surface layer of the first n-well region 16, an n-drain region 21, an n-source region 22, a p-contact region 23 disposed in the surface layer of the p-well region 20, and a polysilicon gate electrode 24. A p drain region 25, a p source region 26, an n contact region 27, and a polysilicon gate electrode 28 are provided on the surface layer of the first n well region 16. An n source region 29 disposed on the surface layer of the first p region 18, a gate electrode 30, and an n drain region 31 disposed on the surface layer of the second n well region 17 are provided. The p contact region 32 disposed in the surface layer of the first p region 18, the p contact region 33 disposed in the surface layer of the second p region 19, and the first n well region 16 and the second n well region 17. N contact region 34, and p contact region 35 disposed across first p region 18 and second p region 19. Each drain region, each source region, a drain electrode D connected to each gate electrode, a source electrode S, and a gate metal electrode G are provided. Metal electrodes 36, 37, 38, 39, 40, 41, and 42 connected to the p contactor region and the n contact region are provided. The metal electrodes 40 and 41 are connected to VS and VB, and the metal electrode 42 including the source electrode S is connected to GND. VS is an intermediate potential of the inverter circuit, and VB is a potential of the first n-well region 16 on the high side obtained by adding a boosted potential (for example, about 15 V) to VS. Therefore, the pn junction between the p well region 20 and the first n well region 16 is always reverse-biased. The p-type substrate 15 is at the ground potential (GND) through the first p region 18 and the second p region 19. The p-type substrate 15 is fixed to the island 2 at a floating potential via the conductive adhesive 8. The semiconductor device 500 includes a level shift, a high breakdown voltage termination region (HVJT), and a floating potential reference circuit region.

また、図中の符号でＲ１はｐ型基板１５の横方向抵抗、Ｒ２はｐ型基板の縦方向抵抗、Ｒ３は第１ｐ領域１８または第１ｐ領域１８と第２ｐ領域を合わせた縦方向抵抗である。
図１０は、制御ＩＣチップ７の要部断面図である。制御ＩＣチップ７は、ｐ型基板１５ａの表面層に配置されるｎウェル領域４３、ｐウェル領域４４、ｐウェル領域４５、ｎ領域４６を備える。ｎウェル領域４３の表面層に配置されるｐドレイン領域４７、ｐソース領域４８、ゲート電極４９およびｎコンタクト領域５０とを備える。ｐウェル領域４４の表面層に配置されるｎドレイン領域５１、ｎソース領域５２、ゲート電極５３およびｐコンタクト領域５４とを備える。ｐウェル領域４５の表面層に配置されるｐコンタクト領域５５を備える。各ドレイン領域、ソース領域、ゲート電極に接続するドレイン電極Ｄ、ソース電極Ｓ、ゲート金属電極Ｇを備える。ｐコンタクタ領域、ｎコンタクト領域に接続する金属電極５６，５７，５８，５９，６０を備える。ｐ型基板１５ａは導電性接着剤８を介して浮遊電位にあるアイランド２に固着されている。金属電極５７，５８，６０はＶＣＣ、金属電極５６，５９はＧＮＤに接続する。ＶＣＣは制御ＩＣチップ７の電源電圧である。 In the figure, R1 is a lateral resistance of the p-type substrate 15, R2 is a longitudinal resistance of the p-type substrate, and R3 is a longitudinal resistance of the first p region 18 or the combination of the first p region 18 and the second p region. is there.
FIG. 10 is a cross-sectional view of the main part of the control IC chip 7. The control IC chip 7 includes an n-well region 43, a p-well region 44, a p-well region 45, and an n-region 46 that are disposed on the surface layer of the p-type substrate 15a. A p drain region 47, a p source region 48, a gate electrode 49, and an n contact region 50 are provided in the surface layer of the n well region 43. An n drain region 51, an n source region 52, a gate electrode 53, and a p contact region 54 are provided in the surface layer of the p well region 44. A p contact region 55 is provided on the surface layer of the p well region 45. Each drain region, source region, drain electrode D connected to the gate electrode, source electrode S, and gate metal electrode G are provided. Metal electrodes 56, 57, 58, 59, 60 connected to the p contactor region and the n contact region are provided. The p-type substrate 15 a is fixed to the island 2 at a floating potential via the conductive adhesive 8. The metal electrodes 57, 58 and 60 are connected to VCC, and the metal electrodes 56 and 59 are connected to GND. VCC is a power supply voltage of the control IC chip 7.

また、図中の符号でＲ４はｐ型基板１５の横方向抵抗、Ｒ５はｐ型基板の縦方向抵抗、Ｒ６はｐウェル領域４５の縦方向抵抗である。
図１１および図１２は、従来の半導体装置５００の製造方法であり、工程順に示した要部製造工程断面図である。 In the figure, R4 is a lateral resistance of the p-type substrate 15, R5 is a longitudinal resistance of the p-type substrate, and R6 is a longitudinal resistance of the p-well region 45.
11 and 12 are cross-sectional views of the main part manufacturing process shown in the order of steps in the conventional method for manufacturing the semiconductor device 500.

図１１（ａ）において、リード端子１とアイランド２を備えたリードフレーム４を準備する。リード端子１とアイランド２は後述する図６の外枠３で互いに接続している。
つぎに、図１１（ｂ）において、高耐圧ＩＣチップ５と制御ＩＣチップ７をアイランド２に導電性接着剤８を介して固着する。 In FIG. 11A, a lead frame 4 having lead terminals 1 and islands 2 is prepared. The lead terminal 1 and the island 2 are connected to each other by an outer frame 3 shown in FIG.
Next, in FIG. 11 (b), the high voltage IC chip 5 and the control IC chip 7 are fixed to the island 2 via the conductive adhesive 8.

つぎに、図１１（ｃ）において、リード端子１、高耐圧ＩＣチップ５、制御ＩＣチップ７をボンディングワイヤ１０で接続する。
つぎに、図１２（ｄ）において、モールド樹脂である、例えば、エポキシ樹脂１１で全体を封止する。 Next, in FIG. 11C, the lead terminal 1, the high voltage IC chip 5, and the control IC chip 7 are connected by bonding wires 10.
Next, in FIG. 12D, the whole is sealed with, for example, an epoxy resin 11 which is a mold resin.

つぎに、図１２（ｅ）において、アイランド２とリード端子１および各リード端子１同士を外枠３から切り離し、リード端子１を折り曲げてフォーミングして、半導体装置５００が完成する。   Next, in FIG. 12E, the island 2, the lead terminal 1, and each lead terminal 1 are separated from the outer frame 3, and the lead terminal 1 is bent and formed to complete the semiconductor device 500.

図１３は、従来の半導体装置５００に形成される寄生トランジスタの等価回路であり、同図（ａ）は高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２の等価回路、同図（ｂ）は制御ＩＣチップ７内に形成される寄生トランジスタ１３の等価回路である。   FIG. 13 is an equivalent circuit of a parasitic transistor formed in a conventional semiconductor device 500. FIG. 13A is an equivalent circuit of the parasitic transistor 12 formed in the high voltage IC chip 5, and FIG. 3 is an equivalent circuit of a parasitic transistor 13 formed in the control IC chip 7.

高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２は、図９に示すｐウェル領域２０、第１ｎウェル領域１６、ｐ型基板１５ａで形成されるＰＮＰバイポーラトランジスタである。一方、制御ＩＣチップ７内に形成される寄生トランジスタ１３は，図１０に示すｐソース領域４８、ｎウェル領域４３、ｐ型基板１５で形成されるＰＮＰバイポーラトランジスタである。   The parasitic transistor 12 formed in the high voltage IC chip 5 is a PNP bipolar transistor formed by the p well region 20, the first n well region 16, and the p type substrate 15a shown in FIG. On the other hand, the parasitic transistor 13 formed in the control IC chip 7 is a PNP bipolar transistor formed by the p source region 48, the n well region 43, and the p type substrate 15 shown in FIG.

高耐圧ＩＣチップ５の動作において、第１ｎウェル領域１６がｐウェル領域２０の電位より低くなると、寄生トランジスタ１２がオンして、寄生トランジスタ１２は短絡状態になる。そのとき、ＶＳからｐ型基板１５を通って表面のＧＮＤに貫通電流６１が流れる。この貫通電流６１はｐ型基板１５の横方向抵抗Ｒ１を経由し第１ｐ領域、第２ｐ領域の縦方向抵抗Ｒ３を通って流れる電流６１ａと、ｐ型基板１５の縦方向抵抗Ｒ２と導電性接着剤８を通ってアイランド２に流れ込む電流６１ｂに分かれる。電流６１ｂはアイランド２からｐ型基板１５へ流れ込む電流６１ｃと、アイランド２を通って制御ＩＣチップ７側に流れる電流６１ｄに分かれる。電流６１ａと電流６１ｃは合流して第１ｐ領域、第２ｐ領域の縦方向抵抗Ｒ３を介して表面のＧＮＤに流れる電流６１ｅとなる。   In the operation of the high breakdown voltage IC chip 5, when the first n-well region 16 becomes lower than the potential of the p-well region 20, the parasitic transistor 12 is turned on and the parasitic transistor 12 is short-circuited. At that time, a through current 61 flows from VS through the p-type substrate 15 to the surface GND. This through current 61 is a current 61a flowing through the vertical resistance R3 of the first p region and the second p region via the lateral resistance R1 of the p-type substrate 15, and the vertical resistance R2 of the p-type substrate 15 and conductive bonding. The current 61 b flows into the island 2 through the agent 8. The current 61b is divided into a current 61c flowing from the island 2 into the p-type substrate 15 and a current 61d flowing through the island 2 to the control IC chip 7 side. The current 61a and the current 61c merge to become a current 61e that flows to the surface GND through the vertical resistance R3 in the first p region and the second p region.

アイランド２から制御ＩＣチップ７に入り込んだ電流６１ｄはｐ型基板１５ａの縦方向抵抗Ｒ５，横方向抵抗Ｒ４，ｐウェル領域４５の縦方向抵抗Ｒ６を通って表面のＧＮＤへ流れて行く。   The current 61d that enters the control IC chip 7 from the island 2 flows to the surface GND through the vertical resistance R5 of the p-type substrate 15a, the horizontal resistance R4, and the vertical resistance R6 of the p-well region 45.

貫通電流６１は、Ｒ１〜Ｒ６によって抑制されて、寄生トランジスタ１２は破壊することは少ない。
一方、高耐圧ＩＣチップ５の動作において、１０ｋＨｚ〜５００ｋＨｚの高周波でＶＢの電位は例えば１５Ｖ〜４１５Ｖの間で変動する。つまり急峻なｄＶ／ｄｔを有する電圧で振られることになる。このＶＢの変動（ｄＶ／ｄｔ）が第１ｎウェル領域１６の電位変動となり、ｐ型基板１５と第１ｎウェル領域１６のｐｎ接合の接合容量Ｃを通して変位電流６２（Ｃ×ｄＶ／ｄｔ）が流れる。この変位電流６２は大きい場合は１Ａ以上あり、ｐ型基板１５の横方向抵抗Ｒ１を経由し縦方向抵抗Ｒ３を介してアイランド２へ流れ出す。 The through current 61 is suppressed by R1 to R6, and the parasitic transistor 12 is rarely destroyed.
On the other hand, in the operation of the high withstand voltage IC chip 5, the potential of VB fluctuates between 15 V and 415 V, for example, at a high frequency of 10 kHz to 500 kHz. That is, it is shaken with a voltage having a steep dV / dt. This variation in VB (dV / dt) becomes the potential variation in the first n-well region 16, and a displacement current 62 (C × dV / dt) flows through the junction capacitance C of the pn junction between the p-type substrate 15 and the first n-well region 16. . When the displacement current 62 is large, it is 1 A or more, and flows out to the island 2 via the lateral resistance R1 of the p-type substrate 15 and the longitudinal resistance R3.

アイランド２に流れ出した変位電流６２は、ｐ型基板１５ａの縦方向抵抗Ｒ５、横方向抵抗Ｒ４、ｐウェル領域４５の縦方向抵抗Ｒ６を経由して、制御ＩＣチップ７の表面側ＧＮＤへ流れて行く。   The displacement current 62 flowing out to the island 2 flows to the surface side GND of the control IC chip 7 via the vertical resistance R5, the horizontal resistance R4 of the p-type substrate 15a, and the vertical resistance R6 of the p-well region 45. go.

この変位電流６２は振動電流であり、この変位電流６２とＲ４，Ｒ５，Ｒ６により発生する電圧によって、制御ＩＣチップ７のグランド電位にあるｐ型基板１５ａの電位が変動し、この電位変動により制御ＩＣチップ７に形成された図示しない回路が誤動作を起こす。   The displacement current 62 is an oscillating current, and the potential of the p-type substrate 15a at the ground potential of the control IC chip 7 varies depending on the voltage generated by the displacement current 62 and R4, R5, and R6. A circuit (not shown) formed on the IC chip 7 malfunctions.

また、特許文献１には、複数のＩＣチップが絶縁基板を介して、リードフレームのアイランドに固着した例が開示されている。   Patent Document 1 discloses an example in which a plurality of IC chips are fixed to an island of a lead frame via an insulating substrate.

特許６０−１８９９５８号公報Japanese Patent No. 60-189958

前記した制御ＩＣチップ７のグランド電位の変動を防止する方策について説明する。
図１４は、アイランド２とＧＮＤリード端子１ａをボンディングワイヤ１０ａで接続した半導体装置６００の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。 A method for preventing the fluctuation of the ground potential of the control IC chip 7 will be described.
FIG. 14 is a configuration diagram of a semiconductor device 600 in which the island 2 and the GND lead terminal 1a are connected by a bonding wire 10a. FIG. 14 (a) is a plan view of the main part, and FIG. 14 (b) is a diagram of FIG. It is principal part sectional drawing cut | disconnected by XX.

図１５は、図１４の高耐圧ＩＣチップ５と制御ＩＣチップ７に形成される寄生トランジスタ１２，１３の等価回路図である。図１５には貫通電流６１および変位電流６２も示した。   FIG. 15 is an equivalent circuit diagram of the parasitic transistors 12 and 13 formed in the high voltage IC chip 5 and the control IC chip 7 of FIG. FIG. 15 also shows a through current 61 and a displacement current 62.

図１６は、高耐圧ＩＣチップ５からアイランド２に貫通電流６１と変位電流６２が流れる様子を説明した図である。
図１４〜図１６に示すように、アイランド２とＧＮＤリード端子１ａを接続して、アイランド２の電位をグランド電位にしっかりと固定する。これによって、制御ＩＣチップ７のグランド電位の変動は抑制され、高耐圧ＩＣチップ５で発生したノイズ（グランド電位の変動）はグランドへ吸収されて、制御ＩＣチップ７に導入されるノイズは防止される。 FIG. 16 is a diagram for explaining how the through current 61 and the displacement current 62 flow from the high voltage IC chip 5 to the island 2.
As shown in FIGS. 14 to 16, the island 2 and the GND lead terminal 1a are connected to firmly fix the potential of the island 2 to the ground potential. As a result, fluctuations in the ground potential of the control IC chip 7 are suppressed, and noise (fluctuation in ground potential) generated in the high voltage IC chip 5 is absorbed into the ground, and noise introduced into the control IC chip 7 is prevented. The

その結果、制御ＩＣチップ７の誤動作を防止することができる。
しかし、ＶＢ端子に高い電圧（４００Ｖ程度）が印加され、高耐圧ＩＣチップ５の寄生トランジスタ１２がオンすると、貫通電流６１はｐ型基板１５の小さな縦方向抵抗Ｒ２を介してアイランド２へ流れ込む。この縦方向抵抗Ｒ２は横方向抵抗Ｒ１の１／１０以下と小さく、さらにこの印加電圧は数百Ｖと高いために、図１５および図１６に示すように、寄生トランジスタ１２に大きな貫通電流６１が流れて、寄生トランジスタ１２が形成される高耐圧ＩＣチップ５を破壊させる場合がある。 As a result, malfunction of the control IC chip 7 can be prevented.
However, when a high voltage (about 400 V) is applied to the VB terminal and the parasitic transistor 12 of the high voltage IC chip 5 is turned on, the through current 61 flows into the island 2 via the small vertical resistance R2 of the p-type substrate 15. Since the vertical resistance R2 is as small as 1/10 or less of the horizontal resistance R1 and the applied voltage is as high as several hundred volts, a large through current 61 is generated in the parasitic transistor 12 as shown in FIGS. In some cases, the high breakdown voltage IC chip 5 on which the parasitic transistor 12 is formed is destroyed.

但し、制御ＩＣチップ７の寄生トランジスタ１３がオンした場合にも、制御ＩＣチップ７からアイランド２に向かって図示しない貫通電流が流れるが、ＶＣＣから印加される電圧は３０Ｖ程度と低いため、貫通電流は小さく寄生トランジスタ１３が形成される制御ＩＣチップ７を破壊させることはない。   However, even when the parasitic transistor 13 of the control IC chip 7 is turned on, a through current (not shown) flows from the control IC chip 7 toward the island 2, but the voltage applied from VCC is as low as about 30 V. The control IC chip 7 on which the parasitic transistor 13 is formed is not destroyed.

このように、変位電流６２（ノイズ）による制御ＩＣチップ７の誤動作を防止することと、貫通電流６１による高耐圧ＩＣチップ５の破壊を防止することを両立させることは困難である。   As described above, it is difficult to achieve both the prevention of malfunction of the control IC chip 7 due to the displacement current 62 (noise) and the destruction of the high voltage IC chip 5 due to the through current 61.

また、特許文献１では、絶縁基板上のＩＣチップが搭載されているので、貫通電流は発生しない。しかし、絶縁基板のキャパシタにより一方のＩＣチップで発生した電位変動が絶縁基板のキャパシタとアイランドを介して他方のＩＣチップに伝達し、他方のＩＣチップを誤動作させることが想定される。   Further, in Patent Document 1, since an IC chip on an insulating substrate is mounted, no through current is generated. However, it is assumed that the potential fluctuation generated in one IC chip by the capacitor on the insulating substrate is transmitted to the other IC chip via the capacitor and island on the insulating substrate, causing the other IC chip to malfunction.

この発明の目的は、前記の課題を解決して、ノイズの導入による制御ＩＣの誤動作を防止し、貫通電流による高耐圧ＩＣの破壊を防止する半導体装置およびその製造方法を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves the above-described problems, prevents malfunction of a control IC due to introduction of noise, and prevents destruction of a high-breakdown-voltage IC due to through current.

前記の目的を達成するために、
高い電圧で駆動する高耐圧ＩＣチップと、前記高耐圧ＩＣチップを駆動する前記電圧より低い電圧で駆動する制御ＩＣチップと、前記高耐圧ＩＣチップと前記制御ＩＣチップが共に接着剤を介して固着し、前記高耐圧ＩＣチップおよび前記制御ＩＣチップに共通の基準電位に接続される金属板と、を備える半導体装置において、
前記高耐圧ＩＣチップの裏側は絶縁性接着剤を介して前記金属板に固着され、前記制御ＩＣチップの裏側は導電性接着剤を介して前記金属板に固着され、前記高耐圧ＩＣチップおよび前記制御ＩＣチップの両者の表側に基準電位が印加される各電極パッドを備える構成とする。 To achieve the above objective,
A high voltage IC chip that is driven at a high voltage, a control IC chip that is driven at a voltage lower than the voltage that drives the high voltage IC chip, and the high voltage IC chip and the control IC chip are fixed together via an adhesive. And a metal plate connected to a reference potential common to the high breakdown voltage IC chip and the control IC chip,
The back side of the high voltage IC chip is fixed to the metal plate via an insulating adhesive, and the back side of the control IC chip is fixed to the metal plate via a conductive adhesive. Each electrode pad to which a reference potential is applied is provided on both front sides of the control IC chip.

この発明によれば、ノイズの導入による制御ＩＣの誤動作を防止し、貫通電流による高耐圧ＩＣの破壊を防止する半導体装置およびその製造方法を提供することができる。   According to the present invention, it is possible to provide a semiconductor device that prevents malfunction of the control IC due to the introduction of noise and prevents the breakdown of the high voltage IC due to through current, and a method for manufacturing the same.

この発明に係る第１実施例の半導体装置１００の構成図であり、（ａ）は要部平面図、（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device 100 of 1st Example based on this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of the same figure (a). . 半導体装置１００の動作を説明する図である。FIG. 6 is a diagram for explaining the operation of the semiconductor device 100. 半導体装置１００に形成される寄生トランジスタの等価回路であり、（ａ）は高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２の等価回路、（ｂ）は制御ＩＣチップ７内に形成される寄生トランジスタ１３の等価回路である。2 is an equivalent circuit of a parasitic transistor formed in the semiconductor device 100, (a) is an equivalent circuit of the parasitic transistor 12 formed in the high voltage IC chip 5, and (b) is a parasitic circuit formed in the control IC chip 7. 3 is an equivalent circuit of the transistor 13. この発明に係わる第２実施例の半導体装置の要部製造工程断面図である。It is principal part manufacturing process sectional drawing of the semiconductor device of 2nd Example concerning this invention. 図４に続く、この発明に係わる第２実施例の半導体装置の要部製造工程断面図である。FIG. 5 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 4; リードフレームの要部平面図である。It is a principal part top view of a lead frame. 従来の半導体装置５００の構成図であり、（ａ）は外形の上面図、（ｂ）は図７（ａ）のＸ−Ｘ線で切断した要部断面図、（ｃ）は図７（ａ）のＹ−Ｙ線で切断した要部断面図である。7A and 7B are configuration diagrams of a conventional semiconductor device 500, in which FIG. 7A is a top view of an outer shape, FIG. 7B is a cross-sectional view of a main part cut along line XX in FIG. 7A, and FIG. It is principal part sectional drawing cut | disconnected by the YY line | wire of (). 図７のエポキシ樹脂１１を外した構成図であり、（ａ）は図７（ａ）のエポキシ樹脂を外したＡ部の要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図である。It is the block diagram which removed the epoxy resin 11 of FIG. 7, (a) is a principal part top view of the A section which removed the epoxy resin of FIG. 7 (a), (b) is the XX line of (a). It is the principal part sectional drawing cut | disconnected. 高耐圧ＩＣチップ５の要部断面図である。3 is a cross-sectional view of a main part of the high voltage IC chip 5. FIG. 制御ＩＣチップ７の要部断面図である。3 is a cross-sectional view of a main part of a control IC chip 7. FIG. 従来の半導体装置５００の要部製造工程断面図である。FIG. 10 is a cross-sectional view of a main part manufacturing process of a conventional semiconductor device 500. 図１に続く、従来の半導体装置５００の要部製造工程断面図である。FIG. 2 is a main-part manufacturing process cross-sectional view of a conventional semiconductor device 500, following FIG. 1; 従来の半導体装置５００に形成される寄生トランジスタの等価回路であり、（ａ）は高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２の等価回路、（ｂ）は制御ＩＣチップ７内に形成される寄生トランジスタ１３の等価回路である。2 is an equivalent circuit of a parasitic transistor formed in a conventional semiconductor device 500, (a) is an equivalent circuit of a parasitic transistor 12 formed in the high voltage IC chip 5, and (b) is formed in a control IC chip 7. This is an equivalent circuit of the parasitic transistor 13. アイランド２とＧＮＤリード端子１ａをボンディングワイヤ１０ａで接続した半導体装置６００の構成図であり、（ａ）は要部平面図、（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。FIG. 2 is a configuration diagram of a semiconductor device 600 in which an island 2 and a GND lead terminal 1a are connected by a bonding wire 10a, where (a) is a plan view of a main part, and (b) is a cross-sectional view taken along line XX in FIG. FIG. 図１４の高耐圧ＩＣチップ５と制御ＩＣチップ７に形成される寄生ダイオード１２，１３の等価回路図である。FIG. 15 is an equivalent circuit diagram of parasitic diodes 12 and 13 formed in the high voltage IC chip 5 and the control IC chip 7 of FIG. 14. 高耐圧ＩＣチップ５からアイランド２に貫通電流６１と変位電流６２が流れる様子を説明した図である。It is a figure explaining a mode that penetration current 61 and displacement current 62 flow into island 2 from high voltage IC chip 5. 高耐圧ＩＣチップ５に形成される回路図である。3 is a circuit diagram formed in the high voltage IC chip 5. FIG.

実施の形態を以下の実施例で説明する。従来と同一部位には同一の符号を付した。   Embodiments will be described in the following examples. The same parts as those in the prior art are denoted by the same reference numerals.

図１は、この発明に係る第１実施例の半導体装置１００の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。図１（ａ）および図１（ｂ）は図８（ａ）および図８（ｂ）に相当した図であり、エポキシ樹脂１１の内部を示した図である。外形は図７（ａ）と同じである。   FIG. 1 is a block diagram of a semiconductor device 100 according to a first embodiment of the present invention, where FIG. 1 (a) is a plan view of the main part, and FIG. 1 (b) is an XX line of FIG. 1 (a). It is the principal part sectional drawing cut | disconnected. FIGS. 1A and 1B are views corresponding to FIGS. 8A and 8B, and show the inside of the epoxy resin 11. The outer shape is the same as in FIG.

この半導体装置１００は、外部導出端子であるリード端子１と、ダイパッド（金属板）であるアイランド２と、アイランド２に固着する高耐圧ＩＣチップ５および低耐圧の制御ＩＣチップ７を備える。高耐圧ＩＣチップ５および制御ＩＣチップ７とリード端子１を接続するボンディングワイヤ１０と、全体を封止するモールド樹脂であるエポキシ樹脂１１とを備える。   The semiconductor device 100 includes a lead terminal 1 that is an external lead-out terminal, an island 2 that is a die pad (metal plate), a high breakdown voltage IC chip 5 that is fixed to the island 2, and a low breakdown voltage control IC chip 7. A bonding wire 10 that connects the high-voltage IC chip 5 and the control IC chip 7 to the lead terminal 1 and an epoxy resin 11 that is a mold resin for sealing the whole are provided.

また、リード端子１のうち基準電位（グランド電位）にあるＧＮＤリード端子１ａとアイランドはボンデングワイヤ１０ａで接続され基準電位（グランド電位）に固定されている高耐圧ＩＣチップ５の表面の図示しないグランドパッドおよび制御ＩＣチップ７の表面の図示しないグランドパッドはリード端子１とボンディングワイヤ１０で接続する。   In addition, the GND lead terminal 1a at the reference potential (ground potential) of the lead terminal 1 and the island are connected by a bonding wire 10a and the surface of the high breakdown voltage IC chip 5 fixed to the reference potential (ground potential) is not shown. A ground pad (not shown) on the surface of the control IC chip 7 is connected to the lead terminal 1 by a bonding wire 10.

以上の構成は、半導体装置６００と同じである。半導体装置６００と異なる点は、高耐圧ＩＣチップ５の裏面は絶縁性接着剤６を介してアイランド２に固着し、制御ＩＣチップ７の裏面は導電性接着剤８を介してアイランド２に固着する点である。   The above configuration is the same as that of the semiconductor device 600. The difference from the semiconductor device 600 is that the back surface of the high voltage IC chip 5 is fixed to the island 2 via the insulating adhesive 6, and the back surface of the control IC chip 7 is fixed to the island 2 via the conductive adhesive 8. Is a point.

図２は、半導体装置１００の動作を説明する図である。また、図３は、半導体装置１００に形成される寄生トランジスタの等価回路であり、同図（ａ）は高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２の等価回路、同図（ｂ）は制御ＩＣチップ７内に形成される寄生トランジスタ１３の等価回路である。点線１４で囲った範囲が半導体基板である。図３には、図２で示した電流の流れも示した。   FIG. 2 is a diagram for explaining the operation of the semiconductor device 100. 3 is an equivalent circuit of a parasitic transistor formed in the semiconductor device 100. FIG. 3A is an equivalent circuit of the parasitic transistor 12 formed in the high voltage IC chip 5, and FIG. 3 is an equivalent circuit of a parasitic transistor 13 formed in the control IC chip 7. A range surrounded by a dotted line 14 is a semiconductor substrate. FIG. 3 also shows the current flow shown in FIG.

高耐圧ＩＣチップ５内に形成される寄生トランジスタ１２は図２で示すｐウェル領域２０、第１ｎウェル領域１６、ｐ型基板１５で形成される寄生ＰＮＰＴｒである。一方、制御ＩＣチップ７内に形成される寄生トランジスタ１３はｐソース領域４８、ｎウェル領域、ｐ型基板１５ａで形成される寄生ＰＮＰＴｒである。   The parasitic transistor 12 formed in the high breakdown voltage IC chip 5 is a parasitic PNPTr formed of the p-well region 20, the first n-well region 16, and the p-type substrate 15 shown in FIG. On the other hand, the parasitic transistor 13 formed in the control IC chip 7 is a parasitic PNPTr formed by the p source region 48, the n well region, and the p type substrate 15a.

高耐圧ＩＣチップ５の動作において、例えば、サージ電圧が印加されて、第１ｎウェル領域１６がｐウェル領域２０の電位より低くなると、寄生トランジスタ１２がオンして、寄生トランジスタ１２は短絡状態になる。そのとき、ＶＳから第１ｎウェル領域１６を通ってＧＮＤに貫通電流６１が流れる。この貫通電流６１はｐ型基板１５の大きな横方向抵抗Ｒ１と第１ｐ領域１８と第２ｐ領域１９の縦方向抵抗Ｒ３を介して表面の金属電極４２，３６を通ってＧＮＤへ流れる。そのため、貫通電流６１は抑制されて寄生トランジスタ１２が破壊することはない。また、高耐圧ＩＣチップ５は絶縁性接着剤６で電気的にアイランド２とは絶縁されているので、貫通電流６１はアイランド２へは流れない。つまり貫通電流６１によって高耐圧ＩＣチップ５は破壊することがない。また、前記の横方向抵抗Ｒ１で生じた電圧はアイランド２へ絶縁性接着剤６のキャパシタンスＣｏを介して伝達されるが、アイランド２はグランド電位（ＧＮＤ）にしっかり固定されているため、制御ＩＣチップ７のｐ型基板１５ａの電位を変動させることはない。そのため、制御ＩＣチップ７の誤動作を防止できる。   In the operation of the high voltage IC chip 5, for example, when a surge voltage is applied and the first n-well region 16 becomes lower than the potential of the p-well region 20, the parasitic transistor 12 is turned on and the parasitic transistor 12 is short-circuited. . At that time, a through current 61 flows from VS to GND through the first n-well region 16. The through current 61 flows to the GND through the metal electrodes 42 and 36 on the surface via the large lateral resistance R1 of the p-type substrate 15 and the vertical resistance R3 of the first p region 18 and the second p region 19. Therefore, the through current 61 is suppressed and the parasitic transistor 12 is not destroyed. Further, since the high voltage IC chip 5 is electrically insulated from the island 2 by the insulating adhesive 6, the through current 61 does not flow to the island 2. That is, the high voltage IC chip 5 is not destroyed by the through current 61. The voltage generated by the lateral resistance R1 is transmitted to the island 2 through the capacitance Co of the insulating adhesive 6. Since the island 2 is firmly fixed to the ground potential (GND), the control IC The potential of the p-type substrate 15a of the chip 7 is not changed. Therefore, malfunction of the control IC chip 7 can be prevented.

図４および図５は、この発明に係わる第２実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。この製造工程断面図は、図６のＸ−Ｘ線で切断した箇所に相当する工程断面図である。尚、図６はリードフレーム４の平面図であり、リード端子１とアイランド２は外枠３で接続されている。   4 and 5 are cross-sectional views of the main part manufacturing process shown in the order of the steps in the method of manufacturing the semiconductor device according to the second embodiment of the present invention. This manufacturing process cross-sectional view is a process cross-sectional view corresponding to a location cut along line XX in FIG. FIG. 6 is a plan view of the lead frame 4, and the lead terminal 1 and the island 2 are connected by an outer frame 3.

図４（ａ）において、リード端子１とアイランド２を備えたリードフレーム４を準備する。リード端子１とアイランド２は図６の外枠３で互いに接続している。リードフレーム４の材質としては銅などである。   In FIG. 4A, a lead frame 4 including lead terminals 1 and islands 2 is prepared. The lead terminal 1 and the island 2 are connected to each other by an outer frame 3 in FIG. The material of the lead frame 4 is copper or the like.

つぎに、図４（ｂ）において、高耐圧ＩＣチップ５をアイランド２に絶縁性接着剤６を介して固着する。絶縁性接着剤６としては、例えば、エポキシ樹脂ペーストもしくはＤＡＦ（ダイアタッチフィイルム）シートなどがある。   Next, in FIG. 4B, the high voltage IC chip 5 is fixed to the island 2 with an insulating adhesive 6. Examples of the insulating adhesive 6 include an epoxy resin paste or a DAF (die attach film) sheet.

つぎに、図４（ｃ）において、制御ＩＣチップ７をアイランド２に導電性接着剤８を介して固着する。導電性接着剤８としては、例えば、エポキシ樹脂にＡｇ粒子を混入したＡｇペーストもしくは半田ペーストなどである。尚、図４（ｂ）の工程と図４（ｃ）の工程を入れ替えても構わない。   Next, in FIG. 4C, the control IC chip 7 is fixed to the island 2 via the conductive adhesive 8. Examples of the conductive adhesive 8 include an Ag paste or a solder paste in which Ag particles are mixed in an epoxy resin. Note that the step of FIG. 4B and the step of FIG. 4C may be interchanged.

つぎに、図４（ｄ）において、リードフレーム４のリード端子１の表面をプラズマクリーニング９で清浄化する。このプラズマクリーニング９は酸素プラズマもしくはアルゴンプラズマを用いて行なうとよい。このクリーニング工程を付加することで、ワイヤボンディングを確実に行なうことができる。   Next, in FIG. 4D, the surface of the lead terminal 1 of the lead frame 4 is cleaned with a plasma cleaning 9. The plasma cleaning 9 is preferably performed using oxygen plasma or argon plasma. By adding this cleaning step, wire bonding can be performed reliably.

つぎに、図５（ｅ）において、リード端子１、高耐圧ＩＣチップ５、制御ＩＣチップ７をボンディングワイヤ１０（金線、アルミニウム線、銅線）で接続する。
つぎに、図５（ｆ）において、モールド樹脂である、例えば、エポキシ樹脂１１で全体を封止する。 Next, in FIG.5 (e), the lead terminal 1, the high voltage | pressure-resistant IC chip 5, and the control IC chip 7 are connected with the bonding wire 10 (a gold wire, an aluminum wire, a copper wire).
Next, in FIG. 5F, the whole is sealed with, for example, an epoxy resin 11 which is a mold resin.

つぎに、図５（ｇ）において、アイランド２とリード端子１および各リード端子１同士を外枠３から切り離し、リード端子１を折り曲げてフォーミングして、半導体装置１００が完成する。   Next, in FIG. 5G, the island 2, the lead terminal 1, and each lead terminal 1 are separated from the outer frame 3, and the lead terminal 1 is bent and formed to complete the semiconductor device 100.

１ リード端子
１ａ ＧＮＤリード端子
２ アイランド
３ 外枠
４ リードフレーム
５ 高耐圧ＩＣチップ
６ 絶縁性接着剤
７ 制御ＩＣチップ
８ 導電性接着剤
９ プラズマクリーニング
１０，１０ａ ボンディングワイヤ
１１ エポキシ樹脂
１２，１３ 寄生トランジスタ
１４ 点線
１５，１５ａ ｐ型基板
１６ 第１ｎウェル領域
１７ 第２ｎウェル領域
１８ 第１ｐ領域
１９ 第２ｐ領域
２０，４４，４５ ｐウェル領域
２１ ｎドレイン領域
２２ ｎソース領域
２３ ｐコンタクト領域
２４，２８，３０，４９，５３ ゲート電極
２５，４７ ｐドレイン領域
２６，４８ ｐソース領域
２７，３４，５０ ｎコンタクト領域
２９，５２ ｎソース領域
３１，５１ ｎドレイン領域
３２，３３，３５，５４，５５ ｐコンタクト領域
３６〜４２，５６〜６０ 金属電極
４３ ｎウェル領域
４６ ｎ領域
６１ 貫通電流
６２ 変位電流
１００，５００，６００ 半導体装置
Ｒ１、Ｒ４ 横方向抵抗
Ｒ２、Ｒ３、Ｒ５，Ｒ６ 縦方向抵抗
Ｃ 接合容量
Ｃｏ キャパシタンス原稿 DESCRIPTION OF SYMBOLS 1 Lead terminal 1a GND lead terminal 2 Island 3 Outer frame 4 Lead frame 5 High voltage IC chip 6 Insulating adhesive 7 Control IC chip 8 Conductive adhesive 9 Plasma cleaning 10, 10a Bonding wire 11 Epoxy resin 12, 13 Parasitic transistor 14 dotted line 15, 15a p-type substrate 16 first n well region 17 second n well region 18 first p region 19 second p region 20, 44, 45 p well region 21 n drain region 22 n source region 23 p contact region 24, 28, 30, 49, 53 Gate electrode 25, 47 p drain region 26, 48 p source region 27, 34, 50 n contact region 29, 52 n source region 31, 51 n drain region 32, 33, 35, 54, 55 p contact Region 36-42, 56-6 Metal electrodes 43 n-well region 46 n region 61 through current 62 displacement current 100, 500, and 600 a semiconductor device R1, R4 lateral resistance R2, R3, R5, R6 longitudinal resistance C junction capacitance Co capacitance document

Claims (8)

高い電圧で駆動する高耐圧ＩＣチップと、前記高耐圧ＩＣチップを駆動する前記電圧より低い電圧で駆動する制御ＩＣチップと、前記高耐圧ＩＣチップと前記制御ＩＣチップが共に接着剤を介して固着し、前記高耐圧ＩＣチップおよび前記制御ＩＣチップに共通の基準電位に接続される金属板と、を備える半導体装置において、
前記高耐圧ＩＣチップの裏側は絶縁性接着剤を介して前記金属板に固着され、前記制御ＩＣチップの裏側は導電性接着剤を介して前記金属板に固着され、前記高耐圧ＩＣチップおよび前記制御ＩＣチップの両者の表側に基準電位が印加される各電極パッドを備えることを特徴とする半導体装置。 A high voltage IC chip that is driven at a high voltage, a control IC chip that is driven at a voltage lower than the voltage that drives the high voltage IC chip, and the high voltage IC chip and the control IC chip are fixed together via an adhesive. And a metal plate connected to a reference potential common to the high breakdown voltage IC chip and the control IC chip,
The back side of the high voltage IC chip is fixed to the metal plate via an insulating adhesive, and the back side of the control IC chip is fixed to the metal plate via a conductive adhesive. A semiconductor device comprising each electrode pad to which a reference potential is applied on both front sides of a control IC chip. 高い電圧で駆動する高耐圧ＩＣチップと、前記高耐圧ＩＣチップを駆動する前記電圧より低い電圧で駆動する制御ＩＣチップと、前記高耐圧ＩＣチップと前記制御ＩＣチップが共に接着剤を介して固着するリードフレームのアイランドと、外部導出端子である複数のリード端子と、前記リード端子の一部を露出し全体を被覆するモールド樹脂を備える半導体装置において、
前記高耐圧ＩＣチップの裏側は絶縁性接着剤を介して前記アイランドに固着され、前記制御ＩＣチップの裏側は導電性接着剤を介して前記アイランドに固着され、前記アイランドとグランド電位に接続される前記リード端子が電気的に接続され、前記高耐圧ＩＣチップおよび前記制御ＩＣチップの両者の表側の各グランド電極パッドと前記グランド電位となる前記リード端子が電気的に接続されることを特徴とする半導体装置。 A high voltage IC chip that is driven at a high voltage, a control IC chip that is driven at a voltage lower than the voltage that drives the high voltage IC chip, and the high voltage IC chip and the control IC chip are fixed together via an adhesive. In a semiconductor device comprising a lead frame island, a plurality of lead terminals that are external lead-out terminals, and a mold resin that exposes a portion of the lead terminals and covers the whole,
The back side of the high voltage IC chip is fixed to the island via an insulating adhesive, and the back side of the control IC chip is fixed to the island via a conductive adhesive and connected to the island and a ground potential. The lead terminals are electrically connected, and the ground electrode pads on the front side of both the high-breakdown-voltage IC chip and the control IC chip are electrically connected to the lead terminals that are at the ground potential. Semiconductor device. 前記導電性接着剤が、Ａｇペーストもしくは半田ペーストであり、前記絶縁性接着剤が、エポキシ樹脂ペーストもしくはＤＡＦシートであることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the conductive adhesive is an Ag paste or a solder paste, and the insulating adhesive is an epoxy resin paste or a DAF sheet. 前記請求項２または３に記載の半導体装置の製造方法において、
リードフレームのアイランドに絶縁性接着剤を介して高耐圧ＩＣチップを固着する工程と、
リードフレームのアイランドに導電性接着剤を介して制御ＩＣチップを固着する工程と、
リードフレームのリード端子の表面をプラズマクリーニングする工程と、
前記高耐圧ＩＣチップおよび制御ＩＣチップの表面のグランド電極パッドとグランド電位にあるリード端子およびアイランドとグランド端子をボンディングワイヤで接続する工程と、
前記リード端子の一部を露出し、全体を樹脂モールドする工程と、
前記リードフレームのアイランドと各リード端子を切り離し、前記リード端子を折り曲げてフォーミングする工程と、
を含むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2 or 3,
Fixing a high voltage IC chip to the island of the lead frame via an insulating adhesive;
Fixing the control IC chip to the island of the lead frame via a conductive adhesive;
Plasma cleaning the surface of the lead frame lead terminal;
Connecting a ground electrode pad on the surface of the high voltage IC chip and the control IC chip, a lead terminal at a ground potential, and an island and a ground terminal with a bonding wire;
Exposing a part of the lead terminal and resin-molding the whole;
Separating the lead frame island and each lead terminal, bending the lead terminal and forming;
A method for manufacturing a semiconductor device, comprising: 前記プラズマクリーニングが、酸素プラズマもしくはアルゴンプラズマを用いて行なうことを特徴とする請求項４に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 4, wherein the plasma cleaning is performed using oxygen plasma or argon plasma. 前記高耐圧ＩＣチップは、
レベルシフト回路と、
前記レベルシフト回路の出力を入力する駆動回路と、を備えることを特徴とする請求項１または２に記載の半導体装置。 The high voltage IC chip is
A level shift circuit;
The semiconductor device according to claim 1, further comprising: a drive circuit that inputs an output of the level shift circuit. 前記高耐圧ＩＣチップは、
ｐ型半導体基板の表面層に該ｐ型半導体基板とｐｎ接合を形成するｎ型半導体領域と該ｎ型半導体領域内に形成された駆動回路とを備え、
前記ｐ型半導体基板は、前記共通の基準電位と電気的に接続され、前記ｎ型半導体領域は、前記駆動回路の電源と電気的に接続されることを特徴とする請求項１に記載の半導体装置。 The high voltage IC chip is
an n-type semiconductor region for forming a pn junction with the p-type semiconductor substrate on a surface layer of the p-type semiconductor substrate, and a drive circuit formed in the n-type semiconductor region ;
2. The semiconductor according to claim 1, wherein the p-type semiconductor substrate is electrically connected to the common reference potential, and the n-type semiconductor region is electrically connected to a power source of the driving circuit. apparatus. 前記高耐圧ＩＣチップは、
ｐ型半導体基板の表面層に該ｐ型半導体基板とｐｎ接合を形成するｎ型半導体領域と該ｎ型半導体領域内に形成された駆動回路とを備え、
前記ｐ型半導体基板は、前記グランド電位と電気的に接続され、前記ｎ型半導体領域は、前記駆動回路の電源と電気的に接続されることを特徴とする請求項２に記載の半導体装置。 The high voltage IC chip is
an n-type semiconductor region for forming a pn junction with the p-type semiconductor substrate on a surface layer of the p-type semiconductor substrate, and a drive circuit formed in the n-type semiconductor region ;
The semiconductor device according to claim 2, wherein the p-type semiconductor substrate is electrically connected to the ground potential, and the n-type semiconductor region is electrically connected to a power supply of the drive circuit.
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