JP6238234B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6238234B2 JP6238234B2 JP2014115133A JP2014115133A JP6238234B2 JP 6238234 B2 JP6238234 B2 JP 6238234B2 JP 2014115133 A JP2014115133 A JP 2014115133A JP 2014115133 A JP2014115133 A JP 2014115133A JP 6238234 B2 JP6238234 B2 JP 6238234B2
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Description
図1は、第1の実施形態に係る半導体装置SDの構成を示す断面図である。本実施形態に係る半導体装置SDは、基板SUBを用いて形成されている。基板SUBは、バルクの半導体(たとえばシリコン)からなるベース基板BSUBの上に、半導体(たとえばシリコン)のエピタキシャル層EPIを成長させたものである。ベース基板BSUB及びエピタキシャル層EPIは、いずれも同一の導電型(第2導電型:例えばp型)である。ベース基板BSUBの不純物濃度はエピタキシャル層EPIの不純物濃度よりも高い。そして、エピタキシャル層EPIには、エピタキシャル層EPIとは異なる導電型(第1導電型:例えばn型)である第1埋込層BINPL1が形成されている。第1埋込層BINPL1はベース基板BSUBから離れている。第1埋込層BINPL1は、エピタキシャル層EPIをエピタキシャル成長させる際に形成されているため、基板SUBの全面に形成されている。
第1トレンチDTR1においては、同一の端部(図2(b)の例では右上側の端部)に第1導電型領域INPL11が形成されている。
図8(a)は、第2の実施形態に係る半導体装置SDが有するバイポーラトランジスタBPTの断面図である。図8(b)は、図8(a)に示したバイポーラトランジスタBPTの平面図である。図8(a)は、図8(b)のB−B´断面に対応している。
図9(a)は、第3の実施形態に係る半導体装置SDが有するバイポーラトランジスタBPTの断面図である。図9(b)は、図9(a)に示したバイポーラトランジスタBPTの平面図である。図9(a)は、図9(b)のB−B´断面に対応している。本実施形態に係る半導体装置SDは、バイポーラトランジスタBPTがpnp型である点を除いて、第2の実施形態に係る半導体装置SDと同様の構成である。
図10は、第4の実施形態に係る半導体装置SDが有するダイオードDDの断面図である。図11は、図10に示したダイオードDDの平面図である。図10は、図11のC−C´断面に対応している。
図12は、第5の実施形態に係る半導体装置SDの平面図であり、第4の実施形態における図11に対応している。本実施形態に係る半導体装置SDは、以下の点を除いて第4の実施形態に係る半導体装置SDと同様である。
図15は、第6の実施形態に係る半導体装置SDの平面図であり、第4の実施形態における図11に対応している。本実施形態に係る半導体装置SDは、第1トレンチDTR1の両方の端部に第1導電型領域INPL11が形成されている点を除いて、第4の実施形態における半導体装置SDと同様の構成である。本実施形態に係る半導体装置SDの製造方法は、第1導電型領域INPL11を形成するためのイオン注入を行っているときに、基板SUBの向きを途中で180°変更する点を除いて、第4の実施形態に係る半導体装置SDの製造方法と同様である。
図16は、第7の実施形態に係る半導体装置SDが有するダイオードDDの構成を示す断面図である。図17は図16に示したダイオードDDの平面図である。図16は、図17のD−D´断面図である。
図21及び図22は、第8の実施形態に係る半導体装置SDが有するダイオードDDの断面図である。図23は、ダイオードDDの平面図である。そして、図21は図23のE−E´断面図であり、図22は図23のF−F´断面図である。本図に示すダイオードDDは、第1導電型領域INPL11および第2導電型領域INPL21が第1トレンチDTR1の同一端部側に形成されている点を除いて、第7の実施形態に係るダイオードDDと同様の構成である。
BINPL2 第2埋込層
BINSL1 埋込絶縁膜
BINSL2 埋込絶縁膜
BCON 埋込コンタクト
BINSL 埋込絶縁膜
BPT バイポーラトランジスタ
BSE ベースBSE
BSE1 p型ウェル
BSE2 p型不純物層
BSE3 n型ウェル
BSE4 n型不純物層
BSUB ベース基板
CON1 第1コンタクト
CON12 第2コンタクト
CON14 第3コンタクト
COR コレクタ
COR1 n型ウェル
COR2 n型不純物層
COR3 p型ウェル
COR4 p型不純物層
DD ダイオード
DRN1 ドレイン
DRN2 ドレイン
DRN3 ドレイン
DTR1 第1トレンチ
DTR2 第2トレンチ
DWL ディープウェル
EL1 第1素子領域
EL2 第2素子領域
EMI エミッタ
EPI エピタキシャル層
GE1 ゲート電極
GE2 ゲート電極
GE3 ゲート電極
HMSK1 絶縁膜
HINPL11 高濃度領域
HINPL12 高濃度領域
HINPL13 高濃度領域
HINPL14 高濃度領域
HNIPL21 高濃度領域
HNIPL22 高濃度領域
HINPL23 高濃度領域
INPL21 第2導電型領域
INSL1 層間絶縁膜
INSL2 絶縁膜
INPL11 第1導電型領域
LWL11 n型ウェルL
LWL21 低濃度p型ウェル
NOF11 オフセット領域
PR1 レジストパターン
SD 半導体装置
SDTR 素子分離トレンチ
STI 埋込絶縁膜STI
SOU1 ソース
SOU2 ソース
SOU3 ソース
SUB 基板
TR1 トランジスタ
TR2 トランジスタ
TR3 トランジスタ
WL11 n型ウェル
WL12 n型ウェル
WL13 n型ウェル
WL21 p型ウェル
WL23 p型ウェル
Claims (13)
- 基板と、
前記基板に形成され、平面視において多角形の各辺に沿って形成された素子分離トレンチと、
前記基板に形成され、前記素子分離トレンチのいずれの辺とも異なる方向に延びている第1トレンチと、
前記基板のうち前記第1トレンチの端部に位置する部分に形成された第1の第1導電型領域と、
を備え、
前記基板は第2導電型であり、
前記第1トレンチは、前記素子分離トレンチで囲まれた領域の内側に位置しており、
さらに、前記基板に埋め込まれた第1導電型の第1埋込層を備え、
前記第1トレンチの底面は、前記第1埋込層に達するか、または前記第1埋込層よりも下に位置しており、
前記第1の第1導電型領域は前記第1埋込層に接続している半導体装置。 - 請求項1に記載の半導体装置において、
前記基板のうち前記素子分離トレンチの内側に位置する領域に形成されたトランジスタを備える半導体装置。 - 請求項2に記載の半導体装置において、
前記基板のうち前記トランジスタのドレイン領域とゲート電極の間の領域に埋め込まれた埋込絶縁膜を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記基板のうち前記素子分離トレンチの内側に位置する領域に形成され、前記基板よりも不純物濃度が高い第1の第2導電型領域と、
前記第1の第1導電型領域に電気的に接続する第1コンタクトと、
前記第1の第2導電型領域に電気的に接続する第2コンタクトと、
を備える半導体装置。 - 請求項4に記載の半導体装置において、
複数の前記第1トレンチが、前記素子分離トレンチの少なくとも一部に沿って配置されており、
前記複数の第1トレンチ毎に前記第1の第1導電型領域が形成されている半導体装置。 - 請求項5に記載の半導体装置において、
前記多角形は矩形であり、
前記複数の第1トレンチは、前記矩形のうちたがいに対向する第1辺及び第2辺に沿って配置されており、
前記第1辺に沿った前記第1トレンチは、第1の方向に延在しており、
前記第2辺に沿った前記第1トレンチは、第1の方向とは異なる第2の方向に延在しており、
前記第1の第1導電型領域は、前記第1トレンチの2つの端部のうち前記素子分離トレンチに近いほうの端部に形成されている半導体装置。 - 請求項6に記載の半導体装置において、
前記第2の方向は、前記第1の方向と直交する半導体装置。 - 請求項5に記載の半導体装置において、
前記第1の第1導電型領域は、前記第1トレンチの2つの端部のそれぞれに形成されている半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の第1導電型領域は、前記基板のうち前記第1トレンチの一方の端部に位置する部分に形成されており、
前記第1埋込層の上に形成され、前記第1埋込層に接する第2導電型の第2埋込層と、
前記基板のうち前記第1トレンチの他方の端部に位置する部分に形成され、前記第2埋込層に接続している第2の第2導電型領域と、
前記第1の第1導電型領域に電気的に接続する第1コンタクトと、
前記第2の第2導電型領域に電気的に接続する第3コンタクトと、
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記第1埋込層の上に形成され、前記第1埋込層に接する第2導電型の第2埋込層と、
前記基板のうち前記第1トレンチの前記端部に位置する部分に形成された第2の第2導電型領域と、
を備え、
前記第1トレンチが延在する方向において、前記第1の第1導電型領域と前記第2の第2導電型領域は並んでおり、
前記第2の第2導電型領域は、前記第2埋込層に接続しており、
さらに、
前記第1の第1導電型領域に電気的に接続する第1コンタクトと、
前記第2の第2導電型領域に電気的に接続する第3コンタクトと、
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記多角形は矩形であり、
前記第1トレンチは、前記素子分離トレンチの各辺に対して30°以上60°以下の角度で延在している半導体装置。 - 第2導電型の半導体層を有する基板と、
前記基板に形成され、平面視において、第1辺と、前記第1辺の反対側の第2辺と、前記第1辺と前記第2辺の間の第3辺と、前記第3辺の反対側の第4辺と、を有する素子分離トレンチと、
前記基板に形成され、平面視において前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺によって囲まれた領域の内側で前記素子分離トレンチの前記第1辺に沿って並んでいる複数の第1トレンチと、
前記基板に形成され、平面視において前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺によって囲まれた領域の内側で前記素子分離トレンチの前記第2辺に沿って並んでいる複数の第2トレンチと、
前記基板の前記半導体層に形成された複数の第1の第1導電型領域と、
前記基板の前記半導体層に形成された複数の第2の第1導電型領域と、
を備え、
平面視において、前記複数の第1トレンチのそれぞれは、第1端部と、前記第1端部の反対側の第2端部と、を有し、かつ前記第1端部及び前記第2端部の一方から他方に向かう方向に長手方向を有し、
平面視において、前記複数の第1トレンチのそれぞれは、前記第1端部の方が前記第2端部よりも前記素子分離トレンチの前記第1辺の近くに位置するように、前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺とは異なる第1方向に前記第1端部及び前記第2端部の一方から他方に向けて延びており、
平面視において、前記複数の第2トレンチのそれぞれは、第3端部と、前記第3端部の反対側の第4端部と、を有し、かつ前記第3端部及び前記第4端部の一方から他方に向かう方向に長手方向を有し、
平面視において、前記複数の第2トレンチのそれぞれは、前記第3端部の方が前記第4端部よりも前記素子分離トレンチの前記第2辺の近くに位置するように、前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺とは異なり、かつ前記第1方向とは異なる第2方向に前記第3端部及び前記第4端部の一方から他方にかけて延びており、
平面視において、前記複数の第1の第1導電型領域のそれぞれは、互いに離間しており、前記複数の第1トレンチのうちの複数の前記第1端部のそれぞれに接しており、
平面視において、前記複数の第2の第1導電型領域のそれぞれは、互いに離間しており、前記複数の第2トレンチのうちの複数の前記第3端部のそれぞれに接している半導体装置。 - 第2導電型の半導体層を有する基板と、
前記基板に形成され、平面視において、第1辺と、前記第1辺の反対側の第2辺と、前記第1辺と前記第2辺の間の第3辺と、前記第3辺の反対側の第4辺と、を有する素子分離トレンチと、
前記基板に形成され、平面視において前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺によって囲まれた領域の内側で前記第1辺に沿って並んでいる複数のトレンチと、
前記基板の前記半導体層に形成された複数の第1導電型領域と、
前記基板の前記半導体層に形成され、前記半導体層よりも高い不純物濃度を有する複数の第2導電型領域と、
を備え、
平面視において、前記複数のトレンチのそれぞれは、第1端部と、前記第1端部の反対側の第2端部と、を有し、かつ前記第1端部及び前記第2端部の一方から他方に向かう方向に長手方向を有し、
平面視において、前記複数のトレンチのそれぞれは、前記素子分離トレンチの前記第1辺、前記第2辺、前記第3辺及び前記第4辺とは異なる方向に前記第1端部及び前記第2端部の一方から他方に向けて延びており、
平面視において、前記複数の第1導電型領域のそれぞれは、互いに離間しており、前記複数のトレンチのうちの複数の前記第1端部のそれぞれに接しており、
平面視において、前記複数の第2導電型領域のそれぞれは、互いに離間しており、前記複数のトレンチのうちの複数の前記第2端部のそれぞれに接している半導体装置。
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