JP6195986B2 - Method for manufacturing metal oxide semiconductor film and method for manufacturing thin film transistor - Google Patents
Method for manufacturing metal oxide semiconductor film and method for manufacturing thin film transistor Download PDFInfo
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- JP6195986B2 JP6195986B2 JP2016523545A JP2016523545A JP6195986B2 JP 6195986 B2 JP6195986 B2 JP 6195986B2 JP 2016523545 A JP2016523545 A JP 2016523545A JP 2016523545 A JP2016523545 A JP 2016523545A JP 6195986 B2 JP6195986 B2 JP 6195986B2
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- metal oxide
- film
- oxide semiconductor
- semiconductor film
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- 239000004065 semiconductor Substances 0.000 title claims description 105
- 238000000034 method Methods 0.000 title claims description 78
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 69
- 150000004706 metal oxides Chemical class 0.000 title claims description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 239000010409 thin film Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims description 123
- 238000000576 coating method Methods 0.000 claims description 47
- 239000011248 coating agent Substances 0.000 claims description 37
- 229910001960 metal nitrate Inorganic materials 0.000 claims description 31
- 238000006243 chemical reaction Methods 0.000 claims description 30
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- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 22
- 239000001301 oxygen Substances 0.000 claims description 22
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical group OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 21
- 239000012298 atmosphere Substances 0.000 claims description 20
- 238000009835 boiling Methods 0.000 claims description 15
- XURCIPRUUASYLR-UHFFFAOYSA-N Omeprazole sulfide Chemical compound N=1C2=CC(OC)=CC=C2NC=1SCC1=NC=C(C)C(OC)=C1C XURCIPRUUASYLR-UHFFFAOYSA-N 0.000 claims description 11
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 10
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- 238000004381 surface treatment Methods 0.000 claims description 7
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical group COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 64
- 229910052751 metal Inorganic materials 0.000 description 27
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- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910052738 indium Inorganic materials 0.000 description 9
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- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- WYURNTSHIVDZCO-UHFFFAOYSA-N Tetrahydrofuran Chemical compound C1CCOC1 WYURNTSHIVDZCO-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
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- 229910052750 molybdenum Inorganic materials 0.000 description 2
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- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- NNWNNQTUZYVQRK-UHFFFAOYSA-N 5-bromo-1h-pyrrolo[2,3-c]pyridine-2-carboxylic acid Chemical compound BrC1=NC=C2NC(C(=O)O)=CC2=C1 NNWNNQTUZYVQRK-UHFFFAOYSA-N 0.000 description 1
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- VZCYOOQTPOCHFL-OWOJBTEDSA-N Fumaric acid Natural products OC(=O)\C=C\C(O)=O VZCYOOQTPOCHFL-OWOJBTEDSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 150000004703 alkoxides Chemical class 0.000 description 1
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- 150000008378 aryl ethers Chemical class 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 150000001649 bromium compounds Chemical class 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
-
- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
- C01B13/00—Oxygen; Ozone; Oxides or hydroxides in general
- C01B13/14—Methods for preparing oxides or hydroxides in general
- C01B13/34—Methods for preparing oxides or hydroxides in general by oxidation or hydrolysis of sprayed or atomised solutions
-
- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
- C01G15/00—Compounds of gallium, indium or thallium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Description
本発明は、金属酸化物半導体膜の製造方法及び薄膜トランジスタの製造方法に関する。 The present invention relates to the production how the manufacturing method and the thin film transistor of the metal oxide semiconductor film.
金属酸化物半導体膜は真空成膜法による製造において実用化がなされ、現在注目を集めている。
一方、簡便、低温、大気圧下で高い半導体特性を有する金属酸化物半導体膜を形成することを目的とした、液相プロセスによる金属酸化物半導体膜の作製に関する研究開発が盛んに行われている。
特に液相プロセスの中でも、必要な場所に必要な膜を形成でき、形成後にパターン化が不要であることから、インクジェット法が注目を集めている。A metal oxide semiconductor film has been put into practical use in the production by a vacuum film forming method and is currently attracting attention.
On the other hand, research and development relating to the production of metal oxide semiconductor films by liquid phase processes has been actively conducted for the purpose of forming metal oxide semiconductor films having high semiconductor characteristics at simple, low temperature and atmospheric pressure. .
In particular, the inkjet method is attracting attention because a necessary film can be formed at a necessary place in a liquid phase process and patterning is not necessary after the formation.
例えば、特開２０１０−２８３００２号公報には、金属塩を含む溶液をインクジェット法で塗布して金属酸化物半導体を形成する手法が開示されている。硝酸塩は安価で且つ低温で緻密な金属酸化物膜を形成可能であるため溶液プロセスに好適に用いることができる。 For example, Japanese Patent Application Laid-Open No. 2010-283002 discloses a method of forming a metal oxide semiconductor by applying a solution containing a metal salt by an inkjet method. Since nitrate is inexpensive and can form a dense metal oxide film at low temperature, it can be suitably used in a solution process.
特開２０１３−２１２８９号公報には、金属塩を含む溶液をインクジェット法により基板に塗布し、乾燥させた後に焼成を行うことで金属酸化物膜を製造する方法が開示されている。 Japanese Patent Application Laid-Open No. 2013-21289 discloses a method of manufacturing a metal oxide film by applying a solution containing a metal salt to a substrate by an ink-jet method, drying the solution, and then baking.
また、特開２０１０−１８２８５２号公報及び特開２０１０−１７１２３７号公報には、金属酸化物半導体前駆体の溶液または分散液を基板上に塗布して金属酸化物半導体前駆体膜を形成した後、ＵＶ（紫外線）オゾン法等によって金属酸化物半導体膜に変換する方法が開示されている。 In addition, in Japanese Patent Application Laid-Open Nos. 2010-182852 and 2010-171237, after a metal oxide semiconductor precursor solution or dispersion is applied on a substrate to form a metal oxide semiconductor precursor film, A method of converting into a metal oxide semiconductor film by a UV (ultraviolet) ozone method or the like is disclosed.
一方、インクジェット法により膜を形成した場合、塗布膜の乾燥速度の違いにより膜の中心部が凹んで端部が盛り上る形状（凹形状）となる、いわゆるコーヒーステイン現象が生じ易い。例えば、Appl. Mater. Interfaces 2013, 5, 3916-3920には、銀ナノ粒子インクをインクジェット法で塗布して銀電極を形成する場合、インクジェット塗布後の乾燥時に低湿度ではコーヒーステイン現象により塗布膜は凹形状となり、高湿度では凸形状となることが報告されている。 On the other hand, when the film is formed by the ink jet method, a so-called coffee stain phenomenon is easily generated in which the center part of the film is recessed and the end part is raised (concave shape) due to the difference in the drying speed of the coating film. For example, in Appl. Mater. Interfaces 2013, 5, 3916-3920, when a silver nanoparticle ink is applied by an ink jet method to form a silver electrode, a coating film is formed due to a coffee stain phenomenon at low humidity during drying after ink jet application. Has been reported to be concave and convex at high humidity.
薄膜トランジスタの半導体層として、金属塩を含む塗布液をインクジェット法により塗布した後、乾燥、加熱等の工程を経て金属酸化物半導体膜を形成する場合、コーヒーステイン現象によって厚みむらが大きくなり易く、厚みむらは電気特性（移動度や電気伝導度）の低下の要因となる。 As a semiconductor layer of a thin film transistor, when a metal oxide semiconductor film is formed through steps such as drying and heating after applying a coating solution containing a metal salt by an inkjet method, the thickness unevenness tends to increase due to the coffee stain phenomenon. Unevenness causes a decrease in electrical characteristics (mobility and electrical conductivity).
例えば、Appl. Mater. Interfaces 2013, 5, 3916-3920に記載されている方法を応用し、インクジェット法による塗布後、乾燥時の雰囲気（湿度）を制御することも考えられるが、乾燥時の湿度の制御によって厚みむらを制御することは難しい。 For example, the method described in Appl. Mater. Interfaces 2013, 5, 3916-3920 may be applied to control the atmosphere (humidity) during drying after application by the ink jet method. It is difficult to control the thickness unevenness by controlling.
また、特開２０１０−２８３００２号公報、特開２０１３−２１２８９号公報、特開２０１０−１８２８５２号公報又は特開２０１０−１７１２３７号公報に開示されている方法では、インクジェット法により塗布膜を形成した後、大気中の加熱やＵＶ照射によって金属酸化物膜に転化させるが、これらの方法で半導体層を形成して薄膜トランジスタを作製しても高い移動度を有する薄膜トランジスタが得られない。 In the method disclosed in JP2010-283002A, JP2013-21289A, JP2010-182852A, or JP2010-171237A, after a coating film is formed by an inkjet method. Although it is converted into a metal oxide film by heating in the atmosphere or UV irradiation, a thin film transistor having high mobility cannot be obtained even if a semiconductor layer is formed by these methods to form a thin film transistor.
本発明は、厚みむらが小さく、電気特性に優れた金属酸化物半導体膜を簡便に製造することができる金属酸化物半導体膜の製造方法、及び電気特性に優れた薄膜トランジスタの製造方法を提供することを目的とする。 The present invention has a small thickness unevenness, a method of manufacturing a metal oxide semiconductor film can be manufactured simply excellent metal oxide semiconductor film in electrical characteristics, and a manufacturing how excellent thin film transistor electrical characteristics The purpose is to provide.
上記目的を達成するため、以下の発明が提供される。
＜１＞ 金属硝酸塩及び溶媒を含む溶液を、溶媒の沸点以上の温度に加熱した状態の基板上にインクジェット法により付与して塗布膜を形成する塗布工程と、
塗布膜に対し、酸素濃度が８００００ｐｐｍ以下の雰囲気下で紫外線照射を行うことにより膜厚が１０ｎｍ以下の金属酸化物半導体膜に転化させる転化工程と、
を含む金属酸化物半導体膜の製造方法。
＜２＞ 金属硝酸塩が、硝酸インジウムを含む＜１＞に記載の金属酸化物半導体膜の製造方法。
＜３＞ 溶媒が、メトキシエタノールである＜１＞又は＜２＞に記載の金属酸化物半導体膜の製造方法。
＜４＞ 溶媒が、メタノールである＜１＞又は＜２＞に記載の金属酸化物半導体膜の製造方法。
＜５＞ 紫外線が、波長３００ｎｍ以下の光を含む＜１＞〜＜４＞のいずれか１つに記載の金属酸化物半導体膜の製造方法。
＜６＞ 転化工程において、基板を加熱した状態で紫外線照射を行う＜１＞〜＜５＞のいずれか１つに記載の金属酸化物半導体膜の製造方法。
＜７＞ 塗布工程の前に、基板の塗布膜を形成する側の面に対して表面処理を行う工程を含む＜１＞〜＜６＞のいずれか１つに記載の金属酸化物半導体膜の製造方法。
＜８＞ 表面処理として、紫外線オゾン処理、アルゴンプラズマ処理、又は窒素プラズマ処理を行う＜７＞に記載の金属酸化物半導体膜の製造方法。
＜９＞ ＜１＞〜＜８＞のいずれか１つに記載の金属酸化物半導体膜の製造方法により金属酸化物半導体膜を形成して酸化物半導体層を作製する工程を含む薄膜トランジスタの製造方法。
In order to achieve the above object, the following invention is provided.
<1> A coating step in which a solution containing a metal nitrate and a solvent is applied by an inkjet method onto a substrate heated to a temperature equal to or higher than the boiling point of the solvent to form a coating film;
A conversion step of converting the coating film into a metal oxide semiconductor film having a thickness of 10 nm or less by performing ultraviolet irradiation in an atmosphere having an oxygen concentration of 80000 ppm or less;
The manufacturing method of the metal oxide semiconductor film containing this.
<2> The method for producing a metal oxide semiconductor film according to <1>, wherein the metal nitrate contains indium nitrate.
<3> Solvent is methoxyethanol <1> A process for producing a metal oxide semiconductor film according to <2>.
< 4 > The method for producing a metal oxide semiconductor film according to <1> or < 2>, wherein the solvent is methanol.
< 5 > The method for producing a metal oxide semiconductor film according to any one of <1> to < 4 >, wherein the ultraviolet rays include light having a wavelength of 300 nm or less.
< 6 > The method for producing a metal oxide semiconductor film according to any one of <1> to < 5 >, wherein in the conversion step, ultraviolet irradiation is performed while the substrate is heated.
< 7 > The metal oxide semiconductor film according to any one of <1> to < 6 >, including a step of performing a surface treatment on the surface of the substrate on which the coating film is formed before the coating step. Production method.
<8> as the surface treatment, ultraviolet ozone treatment, producing how the metal oxide semiconductor film according to an argon plasma treatment, or perform the nitrogen plasma treatment <7>.
< 9 > A method for producing a thin film transistor including a step of forming an oxide semiconductor layer by forming a metal oxide semiconductor film by the method for producing a metal oxide semiconductor film according to any one of <1> to < 8 >. Law.
本発明によれば、厚みむらが小さく、電気特性に優れた金属酸化物半導体膜を簡便に製造することができる金属酸化物半導体膜の製造方法、及び電気特性に優れた薄膜トランジスタの製造方法が提供される。 According to the present invention, a small thickness unevenness, a method of manufacturing a metal oxide semiconductor film which can be easily manufactured excellent metal oxide semiconductor film in electrical properties, and the manufacturing side of excellent thin film transistor electrical characteristics Law is provided.
以下、添付の図面を参照しながら、本発明について具体的に説明する。
なお、図中、同一又は対応する機能を有する部材（構成要素）には同じ符号を付して適宜説明を省略する。また、本明細書において「〜」の記号により数値範囲を示す場合、下限値及び上限値として記載されている数値が含まれる。Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.
In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals and description thereof is omitted as appropriate. Further, in the present specification, when a numerical range is indicated by the symbol “to”, numerical values described as the lower limit value and the upper limit value are included.
＜金属酸化物膜の製造方法＞
本開示の金属酸化物膜の製造方法は、金属硝酸塩及び溶媒を含む溶液を、加熱した状態の基板上にインクジェット法により付与して塗布膜を形成する塗布工程と、塗布膜に対し、酸素濃度が８００００ｐｐｍ以下の雰囲気下で紫外線照射を行うことにより金属酸化物膜に転化させる転化工程と、を含んで構成されている。<Method for producing metal oxide film>
The method for producing a metal oxide film according to the present disclosure includes a coating step of forming a coating film by applying a solution containing a metal nitrate and a solvent on a heated substrate by an inkjet method, and an oxygen concentration with respect to the coating film. Is converted to a metal oxide film by performing ultraviolet irradiation in an atmosphere of 80000 ppm or less.
（塗布工程）
金属硝酸塩及び溶媒を含む溶液（金属硝酸塩溶液）を、加熱した状態の基板上にインクジェット法により付与して塗布膜を形成する。(Coating process)
A solution containing a metal nitrate and a solvent (metal nitrate solution) is applied on a heated substrate by an inkjet method to form a coating film.
−金属硝酸塩溶液−
本開示で用いる金属硝酸塩溶液は、例えば、金属硝酸塩等の溶質を、所定量準備し、所定の濃度になるよう溶媒を加えて、攪拌、溶解させて得られる。攪拌を行う時間は溶質が十分に溶解されれば特に制限はない。また、金属硝酸塩は水和物であってもよい。-Metal nitrate solution-
The metal nitrate solution used in the present disclosure is obtained, for example, by preparing a predetermined amount of a solute such as metal nitrate, adding a solvent so as to have a predetermined concentration, stirring and dissolving. The stirring time is not particularly limited as long as the solute is sufficiently dissolved. The metal nitrate may be a hydrate.
金属硝酸塩溶液は、他の金属含有化合物を含んでいてもよい。金属含有化合物としては金属硝酸塩以外の金属塩、金属ハロゲン化物、有機金属化合物を挙げることができる。
金属硝酸塩以外の金属塩としては、硫酸塩、燐酸塩、炭酸塩、酢酸塩、蓚酸塩等が挙げられ、金属ハロゲン化物としては、塩化物、ヨウ化物、臭化物等が挙げられ、有機金属化合物としては、金属アルコキシド、有機酸塩、金属β−ジケトネート等が挙げられる。The metal nitrate solution may contain other metal-containing compounds. Examples of the metal-containing compound include metal salts other than metal nitrates, metal halides, and organometallic compounds.
Examples of metal salts other than metal nitrates include sulfates, phosphates, carbonates, acetates, and oxalates. Examples of metal halides include chlorides, iodides, bromides, and the like. Examples thereof include metal alkoxides, organic acid salts, and metal β-diketonates.
金属硝酸塩溶液は少なくとも硝酸インジウムを含むことが好ましい。硝酸インジウムを用いることで、インジウム含有酸化物膜を容易に形成することができ、高い電気伝導性が得られる。また、金属酸化物前駆体膜を金属酸化物膜に転化する工程において紫外線を照射する際、硝酸インジウムが紫外光によって効率よく分解され、容易にインジウム含有酸化物膜を形成することができる。 The metal nitrate solution preferably contains at least indium nitrate. By using indium nitrate, an indium-containing oxide film can be easily formed, and high electrical conductivity can be obtained. In addition, in the process of converting the metal oxide precursor film into the metal oxide film, indium nitrate is efficiently decomposed by the ultraviolet light when irradiated with ultraviolet light, and an indium-containing oxide film can be easily formed.
金属硝酸塩溶液は、インジウム以外の金属元素として、亜鉛、錫、ガリウム、及びアルミニウムから選ばれる１つ以上の金属元素を含む化合物（金属含有化合物）を含むことが好ましい。インジウム以外の上記金属元素を適量含むことにより、薄膜トランジスタの半導体層として酸化物半導体膜を形成した場合に、得られる酸化物半導体膜の閾値電圧を所望の値に制御することができ、且つ膜の電気的安定性の向上を図ることができる。
インジウムとインジウム以外の金属元素を含む酸化物半導体又は酸化物導電体としては、Ｉｎ−Ｇａ−Ｚｎ−Ｏ、Ｉｎ−Ｚｎ−Ｏ、Ｉｎ−Ｇａ−Ｏ、Ｉｎ−Ｓｎ−Ｏ、Ｉｎ−Ｓｎ−Ｚｎ−Ｏ等が挙げられる。The metal nitrate solution preferably contains a compound (metal-containing compound) containing one or more metal elements selected from zinc, tin, gallium, and aluminum as a metal element other than indium. By including an appropriate amount of the above metal element other than indium, when an oxide semiconductor film is formed as a semiconductor layer of a thin film transistor, the threshold voltage of the obtained oxide semiconductor film can be controlled to a desired value, and The electrical stability can be improved.
As an oxide semiconductor or an oxide conductor containing indium and a metal element other than indium, In—Ga—Zn—O, In—Zn—O, In—Ga—O, In—Sn—O, and In—Sn— Zn-O etc. are mentioned.
溶液中の金属硝酸塩の濃度は、溶液の粘度、目標とする膜厚、電気特性等に応じて選択すればよいが、溶液中のインジウムの含有量は、溶液中に含まれる金属成分の５０ａｔｏｍ％以上であることが好ましい。上記濃度範囲のインジウムを含む溶液を用いることで、膜中の金属成分の５０ａｔｏｍ％以上がインジウムとなる金属酸化物膜が得られ、電気特性の優れた金属酸化物膜を製造することができる。 The concentration of the metal nitrate in the solution may be selected according to the viscosity of the solution, the target film thickness, the electrical properties, etc., but the indium content in the solution is 50 atom% of the metal component contained in the solution. The above is preferable. By using a solution containing indium in the above concentration range, a metal oxide film in which 50 atom% or more of the metal components in the film is indium can be obtained, and a metal oxide film having excellent electrical characteristics can be manufactured.
溶液中の金属成分の濃度（複数の金属が含まれる場合は各金属の含有モル分率の総和）は、粘度や得たい膜厚に応じて任意に選択することができるが、金属酸化物膜の平坦性及び生産性の観点から、溶液中の金属成分の濃度が０．０１ｍｏｌ／Ｌ以上１．０ｍｏｌ／Ｌ以下であることが好ましく、０．０１ｍｏｌ／Ｌ以上０．５ｍｏｌ／Ｌ以下であることがより好ましい。 The concentration of the metal component in the solution (the sum of the mole fractions of each metal when multiple metals are included) can be arbitrarily selected depending on the viscosity and the desired film thickness, but the metal oxide film From the viewpoint of flatness and productivity, the concentration of the metal component in the solution is preferably 0.01 mol / L or more and 1.0 mol / L or less, preferably 0.01 mol / L or more and 0.5 mol / L or less. It is more preferable.
金属硝酸塩溶液に用いる溶媒は、用いる金属硝酸塩、さらに必要に応じて添加される他の金属含有化合物が溶解する溶媒であれば特に制限されず、水、アルコール溶媒（メタノール、エタノール、プロパノール、エチレングリコール等）、アミド溶媒（Ｎ，Ｎ−ジメチルホルムアミド等）、ケトン溶媒（アセトン、Ｎ−メチルピロリドン、スルホラン、Ｎ，Ｎ−ジメチルイミダゾリジノン等）、エーテル溶媒（テトラヒドロフラン、メトキシエタノール等）、ニトリル溶媒（アセトニトリル等）、その他上記以外のヘテロ原子含有溶媒等が挙げられる。 The solvent used in the metal nitrate solution is not particularly limited as long as it is a solvent in which the metal nitrate to be used and other metal-containing compounds to be added as required are dissolved. Water, alcohol solvents (methanol, ethanol, propanol, ethylene glycol) Etc.), amide solvents (N, N-dimethylformamide etc.), ketone solvents (acetone, N-methylpyrrolidone, sulfolane, N, N-dimethylimidazolidinone etc.), ether solvents (tetrahydrofuran, methoxyethanol etc.), nitrile solvents (Acetonitrile, etc.) and other heteroatom-containing solvents other than the above.
特に溶解性、塗れ性、沸点の観点からメタノール、メトキシエタノールを好適に用いることできる。 In particular, methanol and methoxyethanol can be suitably used from the viewpoints of solubility, paintability, and boiling point.
−基板−
本開示において金属酸化物膜を形成する基板の形状、構造、大きさ等については特に制限はなく、目的に応じて適宜選択することができる。
例えば基板の構造は単層構造であってもよいし、積層構造であってもよい。-Board-
In the present disclosure, the shape, structure, size, and the like of the substrate on which the metal oxide film is formed are not particularly limited and can be appropriately selected according to the purpose.
For example, the structure of the substrate may be a single layer structure or a laminated structure.
基板を構成する材料としては、ガラスやＹＳＺ（Yttria−Stabilized Zirconia；イットリア安定化ジルコニア）等の無機材料、樹脂、樹脂複合材料等からなる基板を用いることができる。中でも軽量である点、可撓性を有する点から樹脂あるいは樹脂複合材料からなる基板が好ましい。具体的には、ポリブチレンテレフタレート、ポリエチレンテレフタレート、ポリエチレンナフタレート、ポリブチレンナフタレート、ポリスチレン、ポリカーボネート、ポリスルホン、ポリエーテルスルホン、ポリアリレート、アリルジグリコールカーボネート、ポリアミド、ポリイミド、ポリアミドイミド、ポリエーテルイミド、ポリベンズアゾール、ポリフェニレンサルファイド、ポリシクロオレフィン、ノルボルネン樹脂、ポリクロロトリフルオロエチレン等のフッ素樹脂、液晶ポリマー、アクリル樹脂、エポキシ樹脂、シリコーン樹脂、アイオノマー樹脂、シアネート樹脂、架橋フマル酸ジエステル、環状ポリオレフィン、芳香族エーテル、マレイミドーオレフィン、セルロース、エピスルフィド化合物等の合成樹脂からなる基板、既述の合成樹脂等と酸化珪素粒子との複合プラスチック材料からなる基板、既述の合成樹脂等と金属ナノ粒子、無機酸化物ナノ粒子もしくは無機窒化物ナノ粒子等との複合プラスチック材料からなる基板、既述の合成樹脂等とカーボン繊維もしくはカーボンナノチューブとの複合プラスチック材料からなる基板、既述の合成樹脂等とガラスフレーク、ガラスファイバーもしくはガラスビーズとの複合プラスチック材料からなる基板、既述の合成樹脂等と粘土鉱物もしくは雲母派生結晶構造を有する粒子との複合プラスチック材料からなる基板、薄いガラスと既述のいずれかの合成樹脂との間に少なくとも１つの接合界面を有する積層プラスチック基板、無機層と有機層（既述の合成樹脂）を交互に積層することで、少なくとも１つの接合界面を有するバリア性能を有する複合材料からなる基板、ステンレス基板またはステンレスと異種金属とを積層した金属多層基板、アルミニウム基板または表面に酸化処理（例えば陽極酸化処理）を施すことで表面の絶縁性を向上させた酸化皮膜付きのアルミニウム基板、酸化膜付きシリコン基板等を用いることができる。 As a material constituting the substrate, a substrate made of an inorganic material such as glass or YSZ (Yttria-Stabilized Zirconia), a resin, a resin composite material, or the like can be used. Among these, a substrate made of a resin or a resin composite material is preferable in terms of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, Substrates made of synthetic resins such as aromatic ethers, maleimide-olefins, cellulose, episulfide compounds, A substrate composed of a composite plastic material of the above-mentioned synthetic resin and the like and silicon oxide particles, a substrate composed of a composite plastic material of the above-described synthetic resin and the like and metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, A substrate made of a composite plastic material of the above-described synthetic resin and the like and carbon fiber or carbon nanotube, a substrate made of a composite plastic material of the above-described synthetic resin and the glass flake, glass fiber or glass bead, the above-mentioned synthetic resin Etc. and a substrate made of a composite plastic material of clay mineral or particles having a mica-derived crystal structure, a laminated plastic substrate having at least one bonding interface between a thin glass and any of the aforementioned synthetic resins, an inorganic layer, and By alternately laminating organic layers (the aforementioned synthetic resins), at least one bonding interface Improve surface insulation by applying oxidation treatment (for example, anodization treatment) to a substrate made of a composite material having barrier performance, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate or the surface. An aluminum substrate with an oxide film, a silicon substrate with an oxide film, or the like can be used.
樹脂基板としては、耐熱性、寸法安定性、耐溶剤性、電気絶縁性、加工性、低通気性、および低吸湿性等に優れていることが好ましい。樹脂基板は、水分や酸素の透過を防止するためのガスバリア層や、樹脂基板の平坦性や下部電極との密着性を向上するためのアンダーコート層等を備えていてもよい。 The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.
また、基板上に、下部電極や、絶縁膜を備えていてもよく、その場合には基板上の下部電極や絶縁膜上に本開示の金属酸化物膜が形成される。 Further, a lower electrode or an insulating film may be provided on the substrate. In that case, the metal oxide film of the present disclosure is formed on the lower electrode or the insulating film on the substrate.
−表面処理−
基板を加熱した状態でインクジェット法により金属硝酸塩溶液を塗布するが、塗布工程の前に、基板の塗布膜を形成する側の面に対して表面処理を行う工程を含んでもよい。例えば、薄膜トランジスタを製造する場合、ゲート絶縁膜の形成後から室内環境下に長時間放置すると、絶縁膜の表面に水分、カーボン、有機成分等の汚染によりトランジスタ特性に悪影響（動作安定性）を与える可能性がある。そこで、金属硝酸塩溶液を基板に塗布する前処理として、基板に対して水分や汚れを除去するための表面処理を行うことが好ましい。基板の表面処理としては、紫外線（ＵＶ）オゾン処理、アルゴンプラズマ処理、窒素プラズマ処理等が挙げられる。
ＵＶオゾン処理としては、例えば、ＵＶオゾン処理装置（Jelight-company-Inc製 Model144AX-100）を用い、下記の条件及び波長にて１〜３分程度行う。
・条件：大気圧、空気中
・波長：２５４ｎｍ（３０ｍＷ／ｃｍ２）、１８５ｎｍ（３．３ｍＷ／ｃｍ２）-Surface treatment-
The metal nitrate solution is applied by an ink jet method while the substrate is heated, but may include a step of performing a surface treatment on the surface of the substrate on which the coating film is formed before the applying step. For example, when a thin film transistor is manufactured, if it is left in an indoor environment for a long time after the formation of a gate insulating film, the surface of the insulating film is adversely affected (operational stability) due to contamination with moisture, carbon, organic components, etc. there is a possibility. Therefore, it is preferable to perform a surface treatment for removing moisture and dirt on the substrate as a pretreatment for applying the metal nitrate solution to the substrate. Examples of the substrate surface treatment include ultraviolet (UV) ozone treatment, argon plasma treatment, and nitrogen plasma treatment.
As the UV ozone treatment, for example, a UV ozone treatment apparatus (Model 144AX-100 manufactured by Jelight-company-Inc) is used and is performed for about 1 to 3 minutes under the following conditions and wavelengths.
-Conditions: atmospheric pressure, in air-Wavelength: 254 nm (30 mW / cm 2 ), 185 nm (3.3 mW / cm 2 )
−インクジェット法での塗布−
基板に対し、必要に応じてＵＶオゾン処理を行った後、基板を加熱した状態でインクジェット法により金属硝酸塩溶液を塗布する。-Application by inkjet method-
After the substrate is subjected to UV ozone treatment as necessary, a metal nitrate solution is applied by an inkjet method while the substrate is heated.
基板の加熱温度は、基板の耐熱性、塗布する金属硝酸塩溶液に含まれる溶媒、目標とする厚みむら等に応じて選択するが、金属硝酸塩溶液に含まれる溶媒の沸点以上にすることが好ましい。半導体膜によって構成される活性層は特に厚みむらが電気特性に悪影響し易いが、溶媒の沸点以上に加熱した基板上にインクジェット法で溶液を吐出し、着弾と略同時に乾燥を行うことにより、プロセス時間の短縮と塗布膜の厚みむらの抑制を図ることができ、次の転化工程で電気特性が向上した半導体膜を形成することができる。
なお、本発明は活性層に限らず、活性層以外の導電性を有する膜の形成にも好適である。例えば、図３に示すボトムゲート型のＴＦＴの構成は、基板１２上に、ゲート電極２２、ゲート絶縁膜２０、活性層１４、及びソース・ドレイン電極１６，１８が積層された構成を有し、さらに、ＴＦＴ上にチャネル保護層、層間絶縁膜等が形成される。そのため、例えば、インクジェットによってゲート電極２２を形成する場合、コーヒーステイン現象によってゲート電極２２の厚みらが大きい場合は、次に形成されるゲート絶縁膜２０のカバレッジやコーヒーステイン形状による絶縁特性の低下、ショートなどが生じる可能性が高くなる。しかし、本開示によりゲート電極２２を形成することで厚みむらが小さくなり、絶縁特性の低下やショートなどの発生を抑制することができる。また、他の構造のＴＦＴにおけるソース・ドレイン電極やゲート電極の形成に本開示を適用することで厚みむらが抑制され、上層への影響が抑制されるため、同様の効果が得られる。The heating temperature of the substrate is selected according to the heat resistance of the substrate, the solvent contained in the metal nitrate solution to be applied, the target thickness unevenness, and the like, but is preferably equal to or higher than the boiling point of the solvent contained in the metal nitrate solution. The active layer composed of a semiconductor film is particularly susceptible to adverse effects on electrical properties, but the process is performed by discharging the solution onto the substrate heated above the boiling point of the solvent by the ink jet method and drying almost simultaneously with landing. Time can be shortened and uneven thickness of the coating film can be suppressed, and a semiconductor film with improved electrical characteristics can be formed in the next conversion step.
The present invention is not limited to the active layer, and is suitable for forming a conductive film other than the active layer. For example, the configuration of the bottom gate TFT shown in FIG. 3 has a configuration in which a gate electrode 22, a gate insulating film 20, an active layer 14, and source / drain electrodes 16 and 18 are stacked on a substrate 12. Further, a channel protective layer, an interlayer insulating film, and the like are formed on the TFT. Therefore, for example, when the gate electrode 22 is formed by inkjet, when the thickness of the gate electrode 22 is large due to the coffee stain phenomenon, the insulation characteristics are deteriorated due to the coverage of the next formed gate insulating film 20 or the coffee stain shape. There is a high possibility that a short circuit will occur. However, by forming the gate electrode 22 according to the present disclosure, the thickness unevenness can be reduced, and the deterioration of the insulating characteristics and the occurrence of a short circuit can be suppressed. Further, by applying the present disclosure to the formation of source / drain electrodes and gate electrodes in TFTs having other structures, thickness unevenness is suppressed and influence on the upper layer is suppressed, so that the same effect can be obtained.
基板の加熱温度は、例えば金属硝酸塩溶液に含まれる溶媒がメタノール（沸点：６４．７℃）の場合には約６５℃以上、メトキシエタノール（沸点：１２４℃）の場合には約１２５℃以上が好ましく、且つそれぞれ基板の耐熱温度以下、例えば樹脂基板を用いる場合は軟化点以下にすればよい。
なお、基板の表面温度が高過ぎると金属硝酸塩溶液の液滴が基板上に吐出されたときに形状が乱れる可能性があり、また、加熱に要するエネルギーコストも上昇するため、基板の表面温度は、溶媒の沸点＋２０℃以下であることが好ましく、溶媒の沸点＋１０℃以下であることがより好ましい。なお、基板の温度は、熱電対付きＳｉウエハで基板の表面温度を測定する。The heating temperature of the substrate is, for example, about 65 ° C. or more when the solvent contained in the metal nitrate solution is methanol (boiling point: 64.7 ° C.), and about 125 ° C. or more when methoxyethanol (boiling point: 124 ° C.) is used. It is preferable that the temperature is lower than the heat-resistant temperature of the substrate, for example, when the resin substrate is used, the temperature is lower than the softening point.
If the surface temperature of the substrate is too high, the shape of the metal nitrate solution droplets may be disturbed when ejected onto the substrate, and the energy cost required for heating also increases. The boiling point of the solvent is preferably 20 ° C. or lower, more preferably the boiling point of the solvent + 10 ° C. or lower. The substrate temperature is measured by using a Si wafer with a thermocouple.
基板の加熱時間には制約はなく、基板の熱伝導を考慮すればよい。また、基板の加熱方法には制約はなく、基板を加熱されたステージ上に配置してもよいし、ステージとは別にヒーターを設置してよいし、ランプ加熱を行ってもよい。加熱時間の短縮の観点から基板が直接加熱部に接している方が好ましい。 There is no restriction on the heating time of the substrate, and the heat conduction of the substrate may be taken into consideration. Moreover, there is no restriction | limiting in the heating method of a board | substrate, A board | substrate may be arrange | positioned on the heated stage, a heater may be installed separately from a stage, and lamp heating may be performed. From the viewpoint of shortening the heating time, it is preferable that the substrate is in direct contact with the heating portion.
また、塗布工程における雰囲気は特に限定されないが、水分や酸素の溶液以外の影響を排除する観点から、不活性雰囲気（窒素、アルゴン等）であることが好ましい。 The atmosphere in the coating step is not particularly limited, but is preferably an inert atmosphere (nitrogen, argon, etc.) from the viewpoint of eliminating influences other than water and oxygen solutions.
基板の表面を目標とする温度に加熱したまま、インクジェット法にて金属硝酸塩溶液を塗布する。基板を好ましくは溶媒の沸点以上に加熱しておくことで、基板上に形成された塗布液中の溶媒は素早く揮発し、転化後に形成される半導体膜の形状が決まるとともに厚みむらが抑制される。 While the surface of the substrate is heated to a target temperature, a metal nitrate solution is applied by an inkjet method. By heating the substrate preferably above the boiling point of the solvent, the solvent in the coating solution formed on the substrate quickly volatilizes, and the shape of the semiconductor film formed after conversion is determined and uneven thickness is suppressed. .
インクジェット法によればフォトリソグラフィープロセスを行う必要はなく、必要な箇所に塗布膜を形成することが可能である。
また、インクジェット法によれば、フレキシブル基板を用いた場合のプロセス中における熱要因によるパターンアライメントのずれにも対応可能であり、予め形成位置を確認することにより高い精度で塗布膜を形成することができる。
また、本発明では、基板を加熱した状態でインクジェット法により溶液を塗布するため、金属硝酸塩溶液の液滴の吐出と乾燥がほぼ同時に行われ、塗布後、別途、乾燥工程を行う必要がない。
また、インクジェット法によってパターニングを行った後、基板全体の乾燥工程を行うと、溶剤が少しずつ揮発して、形状制御が困難になる可能性がある。また、塗布前と塗布後のパターン精度が悪化する可能性もある。
また、インクジェットによってパターニングを行った後、乾燥工程を行わずに加熱下でＵＶ照射を行うと、膜が破損するおそれがある。
一方、本発明では、基板を加熱した状態でインクジェット法によって塗布するため、最初に塗布した部分と最後に塗布した部分で寸法（特に厚み）の均一性が高いパターンを形成することができる。According to the ink jet method, it is not necessary to perform a photolithography process, and a coating film can be formed at a necessary portion.
In addition, according to the ink jet method, it is possible to cope with a pattern alignment shift due to a thermal factor in the process when a flexible substrate is used, and it is possible to form a coating film with high accuracy by confirming a formation position in advance. it can.
In the present invention, since the solution is applied by the ink jet method while the substrate is heated, the droplets of the metal nitrate solution are discharged and dried almost simultaneously, and it is not necessary to perform a separate drying step after the application.
Further, when the entire substrate is dried after patterning by the ink jet method, the solvent may be volatilized little by little, which may make shape control difficult. Moreover, the pattern accuracy before and after application may deteriorate.
Further, if UV irradiation is performed under heating without performing a drying step after patterning by inkjet, the film may be damaged.
On the other hand, in this invention, since it apply | coats by the inkjet method in the state which heated the board | substrate, the pattern with high uniformity of a dimension (especially thickness) can be formed in the part applied initially and the part applied last.
（転化工程）
基板を加熱した状態でインクジェット法により金属硝酸塩溶液を塗布して塗布膜を形成した後、塗布膜に対し、酸素濃度が８００００ｐｐｍ以下の雰囲気下（以下、「低酸素濃度雰囲気下」という場合がある。）で紫外線照射を行うことにより金属酸化物膜に転化させる。(Conversion process)
After a metal nitrate solution is applied by an inkjet method while the substrate is heated to form a coating film, the coating film is subjected to an atmosphere having an oxygen concentration of 80000 ppm or less (hereinafter referred to as “low oxygen concentration atmosphere”). .) Is converted into a metal oxide film by irradiating with ultraviolet rays.
塗布膜に対し、低酸素濃度雰囲気下で紫外線照射することでより低温で金属酸化物膜への転化を行うことができ、また、電気特性に優れた導体膜又は半導体膜を形成することができる。 The coating film can be converted into a metal oxide film at a lower temperature by irradiating with ultraviolet light in a low oxygen concentration atmosphere, and a conductor film or a semiconductor film having excellent electrical characteristics can be formed. .
紫外線の光源としては、ＵＶランプやレーザーが挙げられ、大面積に均一に、安価な設備で紫外線照射を行う観点からＵＶランプが好ましい。
ＵＶランプとしては、例えばエキシマランプ、重水素ランプ、低圧水銀ランプ、高圧水銀ランプ、超高圧水銀ランプ、メタルハライドランプ、ヘリウムランプ、カーボンアークランプ、カドミウムランプ、無電極放電ランプ等が挙げられ、特に低圧水銀ランプを用いると容易に前駆体膜から酸化物膜への転化が行えることから好ましい。波長２６６ｎｍのレーザー光でもよい。Examples of the ultraviolet light source include a UV lamp and a laser, and a UV lamp is preferable from the viewpoint of uniformly irradiating ultraviolet rays with a cheap facility with a large area.
Examples of UV lamps include excimer lamps, deuterium lamps, low pressure mercury lamps, high pressure mercury lamps, ultrahigh pressure mercury lamps, metal halide lamps, helium lamps, carbon arc lamps, cadmium lamps, electrodeless discharge lamps, etc. Use of a mercury lamp is preferable because conversion from a precursor film to an oxide film can be easily performed. Laser light having a wavelength of 266 nm may be used.
転化工程において、金属酸化物前駆体膜の膜面には波長３００ｎｍ以下の光を含む紫外光を１０ｍＷ／ｃｍ２以上の照度で照射することが好ましい。３００ｎｍ以下の波長範囲の紫外光を１０ｍＷ／ｃｍ２以上の照度で照射することで、より短い時間で金属酸化物前駆体膜から金属酸化物膜への転化を行うことができる。In the conversion step, it is preferable that the film surface of the metal oxide precursor film is irradiated with ultraviolet light including light having a wavelength of 300 nm or less at an illuminance of 10 mW / cm 2 or more. By irradiating ultraviolet light in a wavelength range of 300 nm or less with an illuminance of 10 mW / cm 2 or more, conversion from the metal oxide precursor film to the metal oxide film can be performed in a shorter time.
転化工程における紫外線照射は、酸素濃度が８００００ｐｐｍ（８％）以下の低酸素濃度雰囲気下で行う。
基板上の塗布膜に対し、酸素濃度が８００００ｐｐｍ以下の低酸素濃度雰囲気下でＵＶ照射を行うことで酸化物半導体のキャリア密度を制御し易く、高い電子伝達特性の金属酸化物膜が得られる。電子伝達特性を高める観点から上記紫外線照射を行う雰囲気中の酸素濃度は３００００ｐｐｍ以下（３％以下）であることが好ましい。The ultraviolet irradiation in the conversion step is performed in a low oxygen concentration atmosphere having an oxygen concentration of 80000 ppm (8%) or less.
By performing UV irradiation on the coating film on the substrate in a low oxygen concentration atmosphere having an oxygen concentration of 80000 ppm or less, the carrier density of the oxide semiconductor can be easily controlled, and a metal oxide film having high electron transfer characteristics can be obtained. From the viewpoint of enhancing the electron transfer characteristics, the oxygen concentration in the atmosphere in which the ultraviolet irradiation is performed is preferably 30000 ppm or less (3% or less).
なお、紫外線照射時の雰囲気中の酸素濃度を８００００ｐｐｍ以下に調整する手段としては、例えば、基板上の金属酸化物前駆体膜に対して加熱及び紫外線照射を行う処理室内に供給する窒素ガス等の不活性ガスの流速を調整する方法、処理室内に供給するガス中の酸素濃度を調整する方法、事前に処理室内を真空引きし、そこに所望の酸素濃度のガスを充填する方法等が挙げられる。 In addition, as a means for adjusting the oxygen concentration in the atmosphere at the time of ultraviolet irradiation to 80000 ppm or less, for example, nitrogen gas supplied to the processing chamber for heating and ultraviolet irradiation of the metal oxide precursor film on the substrate or the like Examples include a method for adjusting the flow rate of the inert gas, a method for adjusting the oxygen concentration in the gas supplied to the processing chamber, and a method for evacuating the processing chamber in advance and filling the gas with a desired oxygen concentration therein. .
転化工程において基板上の塗布膜に対して低酸素濃度雰囲気下でＵＶ照射する際、基板を加熱した状態で紫外線照射を行ってもよい。ＵＶ照射と基板の加熱を行えば、より短時間で金属酸化物膜に転化し、処理時間の短縮が可能である。
転化工程で基板を加熱してＵＶ照射を行う場合、基板の最高到達温度が１２０℃以上に加熱されていることが好ましい。１２０℃以上であれば緻密な金属酸化物膜を容易に得られる。
一方、転化工程における基板温度を２００℃以下に保持すれば、熱エネルギーの増大を抑制して製造コストを低く抑えることができ、また、耐熱性の低い樹脂基板への適用が容易となる。When UV irradiation is performed in a low oxygen concentration atmosphere on the coating film on the substrate in the conversion step, ultraviolet irradiation may be performed while the substrate is heated. If UV irradiation and substrate heating are performed, the metal oxide film is converted in a shorter time, and the processing time can be shortened.
When UV irradiation is performed by heating the substrate in the conversion step, it is preferable that the highest temperature reached by the substrate is 120 ° C. or higher. When the temperature is 120 ° C. or higher, a dense metal oxide film can be easily obtained.
On the other hand, if the substrate temperature in the conversion step is maintained at 200 ° C. or lower, an increase in thermal energy can be suppressed and the manufacturing cost can be reduced, and application to a resin substrate with low heat resistance is facilitated.
転化工程における基板に対する加熱手段は特に限定されず、ホットプレート加熱、電気炉加熱、赤外線加熱、マイクロ波加熱等から選択すればよい。
紫外線処理時の基板温度は、用いる紫外線ランプからの輻射熱を用いてもよく、ヒーター等によって基板の温度を制御してもよい。紫外線ランプからの輻射熱を用いる際には、ランプ−基板間距離やランプ出力を調整することで制御することができる。The heating means for the substrate in the conversion step is not particularly limited, and may be selected from hot plate heating, electric furnace heating, infrared heating, microwave heating, and the like.
The substrate temperature during the ultraviolet treatment may be radiant heat from the ultraviolet lamp to be used, or the substrate temperature may be controlled by a heater or the like. When radiant heat from an ultraviolet lamp is used, it can be controlled by adjusting the lamp-substrate distance and the lamp output.
紫外線照射時間は紫外線の照度にもよるが、生産性の観点から、５秒以上１２０分以下であることが好ましい。
また、本開示によって製造される金属酸化物膜の膜厚は特に限定されず用途に応じて選択すればよいが、本開示により薄膜トランジスタの半導体層を形成する場合、膜厚は５０ｎｍ以下が好ましく、より好ましくは約１０ｎｍ程度である。Although the ultraviolet irradiation time depends on the illuminance of the ultraviolet rays, it is preferably 5 seconds or longer and 120 minutes or shorter from the viewpoint of productivity.
Further, the film thickness of the metal oxide film produced according to the present disclosure is not particularly limited and may be selected according to the application. However, when the semiconductor layer of the thin film transistor is formed according to the present disclosure, the film thickness is preferably 50 nm or less. More preferably, it is about 10 nm.
以上の工程を経て、導体又は半導体特性を有する金属酸化物膜を容易に製造することができる。
本開示の金属酸化物膜の製造方法は、２００℃以下の低温プロセスで導体又は半導体特性を有する金属酸化物膜を簡便に得ることができる。また、大掛かりな真空装置を用いる必要がない点、耐熱性の低い安価な樹脂基板を用いることができる点、原料が安価である点等からデバイスの作製コストを大幅に低減可能となる。
また、本開示の金属酸化物膜の製造方法は、耐熱性の低い樹脂基板にも適用できることからフレキシブルディスプレイ等のフレキシブル電子デバイスを安価に作製することが可能となる。Through the above steps, a metal oxide film having conductor or semiconductor characteristics can be easily produced.
The manufacturing method of the metal oxide film of this indication can obtain easily the metal oxide film which has a conductor or a semiconductor characteristic with a low-temperature process of 200 degrees C or less. In addition, the device manufacturing cost can be greatly reduced because it is not necessary to use a large vacuum apparatus, an inexpensive resin substrate with low heat resistance can be used, and the raw material is inexpensive.
Moreover, since the manufacturing method of the metal oxide film of this indication is applicable also to a resin substrate with low heat resistance, it becomes possible to produce flexible electronic devices, such as a flexible display, at low cost.
また、本開示の金属酸化物膜の製造方法を用いることで厚みむらが小さく、電気特性に優れた導電膜又は半導体膜を形成することができ、例えば、プロセス適性に優れ且つ電子移動度の高い電気特性を示す半導体素子を安価に作製することができる。 Further, by using the metal oxide film manufacturing method of the present disclosure, it is possible to form a conductive film or a semiconductor film with small thickness unevenness and excellent electrical characteristics, for example, excellent process suitability and high electron mobility. A semiconductor element exhibiting electrical characteristics can be manufactured at low cost.
＜薄膜トランジスタ＞
本開示では、厚みむらが小さく、導電性又は半導体性を示す金属酸化物膜を製造することができることから、本開示の金属酸化物膜の製造方法は、薄膜トランジスタ（ＴＦＴ）の電極（ソース電極、ドレイン電極、若しくはゲート電極）又は酸化物半導体層（活性層）の形成に好適に用いることができる。<Thin film transistor>
In the present disclosure, a metal oxide film having small thickness unevenness and conductivity or semiconductivity can be manufactured. Therefore, a method for manufacturing a metal oxide film of the present disclosure includes a thin film transistor (TFT) electrode (source electrode, It can be suitably used for forming a drain electrode or a gate electrode) or an oxide semiconductor layer (active layer).
以下、本開示の金属酸化物膜の製造方法をＴＦＴの半導体層（酸化物半導体膜）の形成に適用する形態について主に説明するが、本発明はＴＦＴの半導体層の形成に限定されるものではない。 Hereinafter, although the form which applies the manufacturing method of the metal oxide film of this indication to formation of the semiconductor layer (oxide semiconductor film) of TFT is mainly demonstrated, this invention is limited to formation of the semiconductor layer of TFT. is not.
本開示に係るＴＦＴの素子構造は特に限定されず、ゲート電極の位置に基づいた、いわゆる逆スタガ構造（ボトムゲート型とも呼ばれる）及びスタガ構造（トップゲート型とも呼ばれる）のいずれの態様であってもよい。また、半導体層とソース電極及びドレイン電極（適宜、「ソース・ドレイン電極」という。）との接触部分に基づき、いわゆるトップコンタクト型、ボトムコンタクト型のいずれの態様であってもよい。
トップゲート型とは、ＴＦＴが形成されている基板を最下層としたときに、ゲート絶縁膜の上側にゲート電極が配置され、ゲート絶縁膜の下側に半導体層が形成された形態であり、ボトムゲート型とは、ゲート絶縁膜の下側にゲート電極が配置され、ゲート絶縁膜の上側に半導体層が形成された形態である。また、ボトムコンタクト型とは、ソース・ドレイン電極が半導体層よりも先に形成されて半導体層の下面がソース・ドレイン電極に接触する形態であり、トップコンタクト型とは、半導体層がソース・ドレイン電極よりも先に形成されて半導体層の上面がソース・ドレイン電極に接触する形態である。The element structure of the TFT according to the present disclosure is not particularly limited, and may be any of a so-called reverse stagger structure (also referred to as a bottom gate type) and a stagger structure (also referred to as a top gate type) based on the position of the gate electrode. Also good. Further, based on the contact portion between the semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be employed.
The top gate type is a form in which a gate electrode is disposed on the upper side of the gate insulating film and a semiconductor layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer. The bottom gate type is a form in which a gate electrode is disposed below a gate insulating film and a semiconductor layer is formed above the gate insulating film. The bottom contact type is a mode in which the source / drain electrodes are formed before the semiconductor layer, and the lower surface of the semiconductor layer is in contact with the source / drain electrodes. The top contact type is the type in which the semiconductor layer is source / drain. In this embodiment, the upper surface of the semiconductor layer is in contact with the source / drain electrodes.
図１は、トップゲート構造でトップコンタクト型の本開示に係るＴＦＴの一例を示す模式図である。図１に示すＴＦＴ１０では、基板１２の一方の主面上に半導体層１４として上述の酸化物半導体膜が積層されている。そして、半導体層１４上にソース電極１６及びドレイン電極１８が互いに離間して設置され、更にゲート絶縁膜２０と、ゲート電極２２とが順に積層されている。 FIG. 1 is a schematic diagram illustrating an example of a top contact type TFT according to the present disclosure having a top gate structure. In the TFT 10 shown in FIG. 1, the above-described oxide semiconductor film is stacked as the semiconductor layer 14 on one main surface of the substrate 12. A source electrode 16 and a drain electrode 18 are disposed on the semiconductor layer 14 so as to be separated from each other, and a gate insulating film 20 and a gate electrode 22 are sequentially stacked.
図２は、トップゲート構造でボトムコンタクト型の本開示に係るＴＦＴの一例を示す模式図である。図２に示すＴＦＴ３０では、基板１２の一方の主面上にソース電極１６及びドレイン電極１８が互いに離間して設置されている。そして、半導体層１４として上述の酸化物半導体膜と、ゲート絶縁膜２０と、ゲート電極２２と、が順に積層されている。 FIG. 2 is a schematic diagram illustrating an example of a TFT according to the present disclosure having a top gate structure and a bottom contact type. In the TFT 30 shown in FIG. 2, the source electrode 16 and the drain electrode 18 are disposed on one main surface of the substrate 12 so as to be separated from each other. Then, the above-described oxide semiconductor film, the gate insulating film 20, and the gate electrode 22 are sequentially stacked as the semiconductor layer 14.
図３は、ボトムゲート構造でトップコンタクト型の本開示に係るＴＦＴの一例を示す模式図である。図３に示すＴＦＴ４０では、基板１２の一方の主面上にゲート電極２２と、ゲート絶縁膜２０と、半導体層１４として上述の酸化物半導体膜と、が順に積層されている。そして、半導体層１４の表面上にソース電極１６及びドレイン電極１８が互いに離間して設置されている。 FIG. 3 is a schematic diagram showing an example of a top contact type TFT according to the present disclosure having a bottom gate structure. In the TFT 40 shown in FIG. 3, the gate electrode 22, the gate insulating film 20, and the above-described oxide semiconductor film as the semiconductor layer 14 are sequentially stacked on one main surface of the substrate 12. A source electrode 16 and a drain electrode 18 are disposed on the surface of the semiconductor layer 14 so as to be separated from each other.
図４は、ボトムゲート構造でボトムコンタクト型の本開示に係るＴＦＴの一例を示す模式図である。図４に示すＴＦＴ５０では、基板１２の一方の主面上にゲート電極２２と、ゲート絶縁膜２０と、が順に積層されている。そして、ゲート絶縁膜２０の表面上にソース電極１６及びドレイン電極１８が互いに離間して設置され、更に、半導体層１４として上述の酸化物半導体膜が積層されている。 FIG. 4 is a schematic diagram illustrating an example of a bottom contact type TFT according to the present disclosure having a bottom gate structure. In the TFT 50 shown in FIG. 4, the gate electrode 22 and the gate insulating film 20 are sequentially stacked on one main surface of the substrate 12. Then, the source electrode 16 and the drain electrode 18 are provided on the surface of the gate insulating film 20 so as to be separated from each other, and the above-described oxide semiconductor film is stacked as the semiconductor layer 14.
以下の実施形態としては図１に示すトップゲート型の薄膜トランジスタ１０について主に説明するが、本開示に係る薄膜トランジスタはトップゲート型に限定されることなく、ボトムゲート型の薄膜トランジスタであってもよい。 In the following embodiment, the top gate type thin film transistor 10 shown in FIG. 1 will be mainly described. However, the thin film transistor according to the present disclosure is not limited to the top gate type, and may be a bottom gate type thin film transistor.
（基板）
ＴＦＴを形成する基板の形状、構造、大きさ等については特に制限はなく、例えば、前述した基板から目的に応じて適宜選択することができる。
また、本開示で用いる基板の厚みに特に制限はないが、５０μｍ以上５００μｍ以下であることが好ましい。
基板の厚みが５０μｍ以上であると、基板自体の平坦性がより向上する。また、基板の厚みが５００μｍ以下であると、基板自体の可撓性がより向上し、可撓性デバイス用基板としての使用がより容易になる。また、例えば、可撓性デバイスの作製プロセスにおいて、ガラス基板に仮固着したフレキシブル基板上に薄膜トランジスタを形成した後、ガラス基板からフレキシブル基板を剥離する形態であってもよい。(substrate)
The shape, structure, size, etc. of the substrate on which the TFT is formed are not particularly limited, and can be appropriately selected from the above-described substrates according to the purpose.
Moreover, there is no restriction | limiting in particular in the thickness of the board | substrate used by this indication, However, It is preferable that they are 50 micrometers or more and 500 micrometers or less.
When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. Further, when the thickness of the substrate is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a flexible device substrate becomes easier. For example, in the manufacturing process of a flexible device, after forming a thin-film transistor on the flexible substrate temporarily fixed to the glass substrate, the form which peels a flexible substrate from a glass substrate may be sufficient.
（半導体層）
本実施形態の薄膜トランジスタ１０を製造する場合、基板１２のＴＦＴを形成する側の面に必要に応じてＵＶオゾン処理を行った後、基板１２を加熱した状態でインクジェット法により金属硝酸塩溶液を半導体層の形状に塗布して塗布膜を形成し、次いで、酸素濃度が８００００ｐｐｍ以下の雰囲気中で紫外線照射を行って塗布膜を金属酸化物半導体膜に転化させる。(Semiconductor layer)
When the thin film transistor 10 of the present embodiment is manufactured, the surface of the substrate 12 on the side where the TFT is formed is subjected to UV ozone treatment as necessary, and then the metal nitrate solution is applied to the semiconductor layer by the inkjet method while the substrate 12 is heated. Then, the coating film is formed into a metal oxide semiconductor film by irradiation with ultraviolet rays in an atmosphere having an oxygen concentration of 80000 ppm or less.
半導体層１４の厚みは、平坦性及び膜形成に要する時間の観点から５ｎｍ以上５０ｎｍ以下であることが好ましい。 The thickness of the semiconductor layer 14 is preferably 5 nm or more and 50 nm or less from the viewpoint of flatness and time required for film formation.
（保護層）
半導体層１４上にはソース・ドレイン電極１６，１８のエッチング時に半導体層１４を保護するための保護層（不図示）を形成することが好ましい。保護層の成膜方法に特に限定はなく、金属酸化物半導体膜に続けて成膜すればよい。
保護層としては絶縁体が好ましく、保護層を構成する材料は無機材料であってもよく、樹脂のような有機材料であってもよい。なお、保護層はソース電極１６及びドレイン電極１８（適宜「ソース・ドレイン電極」と記す）の形成後に除去しても構わない。(Protective layer)
A protective layer (not shown) for protecting the semiconductor layer 14 is preferably formed on the semiconductor layer 14 when the source / drain electrodes 16 and 18 are etched. There is no particular limitation on the method for forming the protective layer, and the protective layer may be formed after the metal oxide semiconductor film.
The protective layer is preferably an insulator, and the material constituting the protective layer may be an inorganic material or an organic material such as a resin. The protective layer may be removed after the source electrode 16 and the drain electrode 18 (referred to as “source / drain electrodes” as appropriate) are formed.
（ソース・ドレイン電極）
金属酸化物半導体膜で形成された半導体層１４上にソース・ドレイン電極１６，１８を形成する。ソース・ドレイン電極１６，１８はそれぞれ電極として機能する高い導電性を有する材料、例えば、Ａｌ，Ｍｏ，Ｃｒ，Ｔａ，Ｔｉ，Ａｇ，Ａｕ等の金属、Ａｌ−Ｎｄ、Ａｇ合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）、Ｉｎ−Ｇａ−Ｚｎ−Ｏ等の金属酸化物導電膜等を用いて形成することができる。(Source / drain electrodes)
Source / drain electrodes 16 and 18 are formed on a semiconductor layer 14 formed of a metal oxide semiconductor film. The source / drain electrodes 16 and 18 each have a high electrical conductivity functioning as an electrode, for example, metals such as Al, Mo, Cr, Ta, Ti, Ag, Au, Al—Nd, Ag alloy, tin oxide, oxidation A metal oxide conductive film such as zinc, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), or In—Ga—Zn—O can be used.
ソース・ドレイン電極１６，１８を形成する場合、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ（化学気相蒸着）、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜すればよい。 When the source / drain electrodes 16 and 18 are formed, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD (chemical vapor deposition), or a plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with a material to be used from among chemical methods such as the above.
ソース・ドレイン電極１６，１８の膜厚は、成膜性、エッチング又はリフトオフ法によるパターンニング性、導電性等を考慮すると、１０ｎｍ以上１０００ｎｍ以下とすることが好ましく、５０ｎｍ以上１００ｎｍ以下とすることがより好ましい。 The film thickness of the source / drain electrodes 16 and 18 is preferably 10 nm or more and 1000 nm or less, preferably 50 nm or more and 100 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like. More preferred.
ソース・ドレイン電極１６，１８は、導電膜を形成した後、例えば、エッチング又はリフトオフ法により所定の形状にパターンニングして形成してもよく、インクジェット法等により直接パターン形成してもよい。この際、ソース・ドレイン電極１６，１８及びこれらの電極に接続する配線（図示しない）を同時にパターンニングすることが好ましい。 The source / drain electrodes 16 and 18 may be formed by patterning into a predetermined shape by, for example, etching or a lift-off method after forming a conductive film, or may be directly formed by an inkjet method or the like. At this time, it is preferable to pattern the source / drain electrodes 16 and 18 and wiring (not shown) connected to these electrodes simultaneously.
（ゲート絶縁膜）
ソース・ドレイン電極１６，１８及び配線（図示しない）を形成した後、ゲート絶縁膜２０を形成する。ゲート絶縁膜２０は高い絶縁性を有する材料が好ましく、例えばＳｉＯ２、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、ＨｆＯ２等の絶縁膜、又はこれらの化合物を２種以上含む絶縁膜としてもよく、単層構造であっても積層構造であってもよい。
ゲート絶縁膜２０の形成は、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜すればよい。ゲート絶縁膜２０は、ゲート絶縁特性を有していれば、有機絶縁膜でも無機絶縁膜でもよい。(Gate insulation film)
After the source / drain electrodes 16 and 18 and the wiring (not shown) are formed, the gate insulating film 20 is formed. The gate insulating film 20 is preferably made of a material having high insulating properties. For example, an insulating film such as SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 , or a compound thereof is used. The insulating film may include two or more types, and may have a single layer structure or a stacked structure.
The gate insulating film 20 can be formed from a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used. The gate insulating film 20 may be an organic insulating film or an inorganic insulating film as long as it has gate insulating characteristics.
尚、ゲート絶縁膜２０はリーク電流の低下及び電圧耐性の向上のための厚みを有する必要がある一方、ゲート絶縁膜２０の厚みが大きすぎると駆動電圧の上昇を招いてしまう。ゲート絶縁膜２０は材質にもよるが、ゲート絶縁膜２０の厚みは１０ｎｍ〜１０μｍが好ましく、５０ｎｍ〜１０００ｎｍがより好ましく、１００ｎｍ〜４００ｎｍが特に好ましい。 The gate insulating film 20 needs to have a thickness for reducing leakage current and improving voltage resistance. On the other hand, if the thickness of the gate insulating film 20 is too large, the driving voltage is increased. Although the gate insulating film 20 depends on the material, the thickness of the gate insulating film 20 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.
（ゲート電極）
ゲート絶縁膜２０を形成した後、ゲート電極２２を形成する。ゲート電極２２は高い導電性を有する材料、例えば、Ａｌ，Ｃｕ，Ｍｏ，Ｃｒ，Ｔａ，Ｔｉ，Ａｇ，Ａｕ等の金属、Ａｌ−Ｎｄ、Ａｇ合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）、Ｉｎ−Ｇａ−Ｚｎ−Ｏ等の金属酸化物導電膜等を用いて形成することができる。ゲート電極２２としてはこれらの導電膜を単層構造又は２層以上の積層構造として用いることができる。(Gate electrode)
After forming the gate insulating film 20, a gate electrode 22 is formed. The gate electrode 22 is made of a material having high conductivity, for example, metal such as Al, Cu, Mo, Cr, Ta, Ti, Ag, Au, Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium oxide. A metal oxide conductive film such as tin (ITO), indium zinc oxide (IZO), or In—Ga—Zn—O can be used. As the gate electrode 22, these conductive films can be used as a single layer structure or a stacked structure of two or more layers.
ゲート電極２２は、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。
ゲート電極２２を形成するための金属膜の膜厚は、成膜性、エッチングやリフトオフ法によるパターンニング性、導電性等を考慮すると、１０ｎｍ以上１０００ｎｍ以下とすることが好ましく、５０ｎｍ以上２００ｎｍ以下とすることがより好ましい。
成膜後、エッチング又はリフトオフ法により所定の形状にパターンニングすることにより、ゲート電極２２を形成してもよく、インクジェット法、印刷法等により直接パターン形成してもよい。この際、ゲート電極２２及びゲート配線（図示しない）を同時にパターンニングすることが好ましい。The gate electrode 22 is made of a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of the suitability of the above.
The film thickness of the metal film for forming the gate electrode 22 is preferably 10 nm or more and 1000 nm or less, preferably 50 nm or more and 200 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like. More preferably.
After the film formation, the gate electrode 22 may be formed by patterning into a predetermined shape by an etching or lift-off method, or the pattern may be formed directly by an inkjet method, a printing method, or the like. At this time, it is preferable to pattern the gate electrode 22 and the gate wiring (not shown) at the same time.
以上で説明した本実施形態の薄膜トランジスタ１０の用途には特に限定はないが、高い輸送特性を有する薄膜トランジスタを低温で作製できることから、各種電子デバイス、特にフレキシブルな電子デバイスの作製にも適用することができる。具体的には、液晶表示装置、有機ＥＬ（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ）表示装置、無機ＥＬ表示装置等の表示装置における駆動素子、耐熱性の低い樹脂基板を用いたフレキシブルディスプレイの作製に好適である。
更に本開示により製造される薄膜トランジスタは、Ｘ線センサ、イメージセンサ等の各種センサ、ＭＥＭＳ（Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍ）等、種々の電子デバイスにおける駆動素子（駆動回路）として好適に用いられる。The use of the thin film transistor 10 of the present embodiment described above is not particularly limited, but since a thin film transistor having high transport characteristics can be produced at a low temperature, it can be applied to production of various electronic devices, particularly flexible electronic devices. it can. Specifically, it is suitable for manufacturing a flexible display using a driving element in a display device such as a liquid crystal display device, an organic EL (Electro Luminescence) display device, and an inorganic EL display device, and a resin substrate having low heat resistance.
Furthermore, the thin film transistor manufactured according to the present disclosure is suitably used as a driving element (driving circuit) in various electronic devices such as various sensors such as an X-ray sensor and an image sensor, and a MEMS (Micro Electro Mechanical System).
＜液晶表示装置＞
本発明の一実施形態である液晶表示装置について、図５に一部分の概略断面図を示し、図６に電気配線の概略構成図を示す。<Liquid crystal display device>
FIG. 5 shows a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the present invention, and FIG. 6 shows a schematic configuration diagram of electrical wiring.
図５に示すように、本実施形態の液晶表示装置１００は、図１に示したトップゲート構造でトップコンタクト型のＴＦＴ１０と、ＴＦＴ１０のパッシベーション層１０２で保護されたゲート電極２２上に画素下部電極１０４および対向上部電極１０６で挟まれた液晶層１０８と、各画素に対応させて異なる色を発色させるためのＲ（赤）Ｇ（緑）Ｂ（青）のカラーフィルタ１１０とを備え、ＴＦＴ１０の基板１２側およびＲＧＢカラーフィルタ１１０上にそれぞれ偏光板１１２ａ、１１２ｂを備えた構成である。 As shown in FIG. 5, the liquid crystal display device 100 according to the present embodiment includes a top contact type TFT 10 having the top gate structure shown in FIG. 1 and a pixel lower electrode on the gate electrode 22 protected by the passivation layer 102 of the TFT 10. 104 and a liquid crystal layer 108 sandwiched between the counter upper electrode 106 and an R (red) G (green) B (blue) color filter 110 for developing different colors corresponding to each pixel. In this configuration, polarizing plates 112a and 112b are provided on the substrate 12 side and the RGB color filter 110, respectively.
また、図６に示すように、本実施形態の液晶表示装置１００は、互いに平行な複数のゲート配線１１２と、ゲート配線１１２と交差する、互いに平行なデータ配線１１４とを備えている。ここでゲート配線１１２とデータ配線１１４は電気的に絶縁されている。ゲート配線１１２とデータ配線１１４との交差部付近に、ＴＦＴ１０が備えられている。 As shown in FIG. 6, the liquid crystal display device 100 according to the present embodiment includes a plurality of gate lines 112 that are parallel to each other and data lines 114 that are parallel to each other and intersect the gate lines 112. Here, the gate wiring 112 and the data wiring 114 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 112 and the data wiring 114.
ＴＦＴ１０のゲート電極２２は、ゲート配線１１２に接続されており、ＴＦＴ１０のソース電極１６はデータ配線１１４に接続されている。また、ＴＦＴ１０のドレイン電極１８はゲート絶縁膜２０に設けられたコンタクトホール１１６を介して（コンタクトホール１１６に導電体が埋め込まれて）画素下部電極１０４に接続されている。画素下部電極１０４は、接地された対向上部電極１０６とともにキャパシタ１１８を構成している。 The gate electrode 22 of the TFT 10 is connected to the gate wiring 112, and the source electrode 16 of the TFT 10 is connected to the data wiring 114. The drain electrode 18 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 provided in the gate insulating film 20 (a conductor is embedded in the contact hole 116). The pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.
＜有機ＥＬ表示装置＞
本発明の一実施形態に係るアクティブマトリックス方式の有機ＥＬ表示装置について、図７に一部分の概略断面図を示し、図８に電気配線の概略構成図を示す。<Organic EL display device>
FIG. 7 shows a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the present invention, and FIG. 8 shows a schematic configuration diagram of electrical wiring.
本実施形態のアクティブマトリックス方式の有機ＥＬ表示装置２００は、図１に示したトップゲート構造のＴＦＴ１０が、パッシベーション層２０２を備えた基板１２上に、駆動用ＴＦＴ１０ａおよびスイッチング用ＴＦＴ１０ｂとして備えられ、ＴＦＴ１０ａ，１０ｂ上に下部電極２０８および上部電極２１０に挟まれた有機発光層２１２からなる有機ＥＬ発光素子２１４を備え、上面もパッシベーション層２１６により保護された構成となっている。 The active-matrix organic EL display device 200 of the present embodiment includes the TFT 10 having the top gate structure shown in FIG. 1 as a driving TFT 10a and a switching TFT 10b on a substrate 12 having a passivation layer 202. , 10b is provided with an organic EL light emitting element 214 composed of an organic light emitting layer 212 sandwiched between a lower electrode 208 and an upper electrode 210, and the upper surface is also protected by a passivation layer 216.
また、図８に示すように、本実施形態の有機ＥＬ表示装置２００は、互いに平行な複数のゲート配線２２０と、ゲート配線２２０と交差する、互いに平行なデータ配線２２２および駆動配線２２４とを備えている。ここで、ゲート配線２２０とデータ配線２２２、駆動配線２２４とは電気的に絶縁されている。スイッチング用ＴＦＴ１０ｂのゲート電極２２は、ゲート配線２２０に接続されており、スイッチング用ＴＦＴ１０ｂのソース電極１６はデータ配線２２２に接続されている。また、スイッチング用ＴＦＴ１０ｂのドレイン電極１８は駆動用ＴＦＴ１０ａのゲート電極２２に接続されるとともに、キャパシタ２２６を用いることで駆動用ＴＦＴ１０ａをオン状態に保つ。駆動用ＴＦＴ１０ａのソース電極１６は駆動配線２２４に接続され、ドレイン電極１８は有機ＥＬ発光素子２１４に接続される。 As shown in FIG. 8, the organic EL display device 200 of this embodiment includes a plurality of gate wirings 220 that are parallel to each other, and data wirings 222 and driving wirings 224 that are parallel to each other and intersect the gate wirings 220. ing. Here, the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated. The gate electrode 22 of the switching TFT 10 b is connected to the gate wiring 220, and the source electrode 16 of the switching TFT 10 b is connected to the data wiring 222. The drain electrode 18 of the switching TFT 10b is connected to the gate electrode 22 of the driving TFT 10a, and the driving TFT 10a is kept on by using the capacitor 226. The source electrode 16 of the driving TFT 10 a is connected to the driving wiring 224, and the drain electrode 18 is connected to the organic EL light emitting element 214.
なお、図７に示した有機ＥＬ表示装置において、上部電極２１０を透明電極としてトップエミッション型としてもよいし、下部電極２０８およびＴＦＴの各電極を透明電極とすることによりボトムエミッション型としてもよい。 In the organic EL display device shown in FIG. 7, the upper electrode 210 may be a top emission type using a transparent electrode, or the lower electrode 208 and each electrode of a TFT may be a bottom emission type using a transparent electrode.
＜Ｘ線センサ＞
本発明の一実施形態であるＸ線センサについて、図９に一部分の概略断面図を示し、図１０に電気配線の概略構成図を示す。<X-ray sensor>
FIG. 9 shows a partial schematic cross-sectional view of an X-ray sensor according to an embodiment of the present invention, and FIG. 10 shows a schematic configuration diagram of electrical wiring.
本実施形態のＸ線センサ３００は基板１２上に形成されたＴＦＴ１０およびキャパシタ３１０と、キャパシタ３１０上に形成された電荷収集用電極３０２と、Ｘ線変換層３０４と、上部電極３０６とを備えて構成される。ＴＦＴ１０上にはパッシベーション膜３０８が設けられている。 The X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed. A passivation film 308 is provided on the TFT 10.
キャパシタ３１０は、キャパシタ用下部電極３１２とキャパシタ用上部電極３１４とで絶縁膜３１６を挟んだ構造となっている。キャパシタ用上部電極３１４は絶縁膜３１６に設けられたコンタクトホール３１８を介し、ＴＦＴ１０のソース電極１６およびドレイン電極１８のいずれか一方（図９においてはドレイン電極１８）と接続されている。 The capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314. The capacitor upper electrode 314 is connected to one of the source electrode 16 and the drain electrode 18 (the drain electrode 18 in FIG. 9) of the TFT 10 through a contact hole 318 provided in the insulating film 316.
電荷収集用電極３０２は、キャパシタ３１０におけるキャパシタ用上部電極３１４上に設けられており、キャパシタ用上部電極３１４に接している。
Ｘ線変換層３０４はアモルファスセレンからなる層であり、ＴＦＴ１０およびキャパシタ３１０を覆って設けられている。
上部電極３０６はＸ線変換層３０４上に設けられており、Ｘ線変換層３０４に接している。The charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
The X-ray conversion layer 304 is a layer made of amorphous selenium, and is provided so as to cover the TFT 10 and the capacitor 310.
The upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.
図１０に示すように、本実施形態のＸ線センサ３００は、互いに平行な複数のゲート配線３２０と、ゲート配線３２０と交差する、互いに平行な複数のデータ配線３２２とを備えている。ここでゲート配線３２０とデータ配線３２２は電気的に絶縁されている。ゲート配線３２０とデータ配線３２２との交差部付近に、ＴＦＴ１０が備えられている。 As shown in FIG. 10, the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that intersect with the gate wirings 320 and are parallel to each other. Here, the gate wiring 320 and the data wiring 322 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.
ＴＦＴ１０のゲート電極２２は、ゲート配線３２０に接続されており、ＴＦＴ１０のソース電極１６はデータ配線３２２に接続されている。また、ＴＦＴ１０のドレイン電極１８は電荷収集用電極３０２に接続されており、さらに電荷収集用電極３０２は、キャパシタ３１０に接続されている。 The gate electrode 22 of the TFT 10 is connected to the gate wiring 320, and the source electrode 16 of the TFT 10 is connected to the data wiring 322. The drain electrode 18 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.
本実施形態のＸ線センサ３００において、Ｘ線は図９中、上部電極３０６側から入射してＸ線変換層３０４で電子−正孔対を生成する。Ｘ線変換層３０４に上部電極３０６によって高電界を印加しておくことにより、生成した電荷はキャパシタ３１０に蓄積され、ＴＦＴ１０を順次走査することによって読み出される。 In the X-ray sensor 300 of this embodiment, X-rays enter from the upper electrode 306 side in FIG. 9 and generate electron-hole pairs in the X-ray conversion layer 304. By applying a high electric field to the X-ray conversion layer 304 by the upper electrode 306, the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.
なお、上記実施形態の液晶表示装置１００、有機ＥＬ表示装置２００、及びＸ線センサ３００においては、トップゲート構造のＴＦＴを備えているが、トップゲート構造のＴＦＴに限定されず、図２〜図４に示す構造のＴＦＴであってもよい。 Note that the liquid crystal display device 100, the organic EL display device 200, and the X-ray sensor 300 of the above embodiment include a top gate TFT, but are not limited to the top gate TFT. A TFT having the structure shown in FIG.
以下に実施例を説明するが、本発明は以下の実施例により何ら限定されない。
なお、本件の効果を示すために、簡便な構成にて効果を確認した。また、本実施例においては、「実施例１、２、８」を「参考例１、２、８」と読み替えるものとする。
Examples will be described below, but the present invention is not limited to the following examples.
In addition, in order to show the effect of this case, the effect was confirmed with the simple structure. In the present embodiment, “Examples 1, 2, 8” are read as “Reference Examples 1, 2, 8”.
＜実施例１＞
（金属硝酸塩溶液）
硝酸インジウム（Ｉｎ（ＮＯ３）３・ｘＨ２Ｏ、純度：４Ｎ、高純度化学研究所社製）を２−メトキシエタノール（試薬特級、沸点：１２４℃、和光純薬工業社製）中に溶解させ、硝酸インジウム濃度０．５ｍｏｌ／Ｌの溶液を調製した。
基板は熱酸化膜（膜厚１００ｎｍ）付ｐ型Ｓｉ基板を用いた。ゲート電極はｐ型Ｓｉ、ゲート絶縁膜は熱酸化膜Ｓｉである。<Example 1>
(Metal nitrate solution)
Indium nitrate (In (NO 3 ) 3 xH 2 O, purity: 4N, manufactured by High Purity Chemical Laboratory Co., Ltd.) is dissolved in 2-methoxyethanol (special grade reagent, boiling point: 124 ° C., manufactured by Wako Pure Chemical Industries, Ltd.) To prepare a solution having an indium nitrate concentration of 0.5 mol / L.
The substrate was a p-type Si substrate with a thermal oxide film (film thickness 100 nm). The gate electrode is p-type Si, and the gate insulating film is a thermal oxide film Si.
硝酸インジウム溶液をインクジェットで吐出する前に、ＵＶオゾン処理装置（Jelight-company-Inc製 Model144AX-100）を用い、基板に対し、ＵＶオゾン処理を約３分行った。 Before discharging the indium nitrate solution by inkjet, the substrate was subjected to UV ozone treatment for about 3 minutes using a UV ozone treatment apparatus (Model 144AX-100 manufactured by Jelight-company-Inc).
（塗布工程）
インクジェット装置は、富士フイルム社製 マテリアルプリンターＤＭＰ−２８３１を用いた。このインクジェット装置はインクカートリッジとステージを独立に温度調整が可能であり、インクカートリッジは室温２５℃とした。一方、ステージ上の基板をより高温で加熱できるように基板ステージ上にシリコンラバーヒーターを取り付け６０度以上に加熱可能な機構を設けた。温度校正には熱電対付きＳｉウエハで行い、正確な基板表面温度になるように調整した。(Coating process)
As the ink jet apparatus, a material printer DMP-2831 manufactured by FUJIFILM Corporation was used. In this ink jet apparatus, the temperature of the ink cartridge and the stage can be adjusted independently, and the temperature of the ink cartridge is set to 25 ° C. On the other hand, a silicon rubber heater was attached on the substrate stage so that the substrate on the stage could be heated at a higher temperature, and a mechanism capable of heating to 60 degrees or more was provided. The temperature calibration was performed on a Si wafer with a thermocouple, and the temperature was adjusted so that the substrate surface temperature was accurate.
６０℃に設定したステージ上に基板を配置し、５分間加熱した後、インクジェット（「ＩＪ」と略記する場合がある。）によって基板上に長さ約３ｍｍのライン状の塗布膜を形成した。 The substrate was placed on a stage set at 60 ° C., heated for 5 minutes, and then a line-shaped coating film having a length of about 3 mm was formed on the substrate by inkjet (sometimes abbreviated as “IJ”).
（転化工程）
次に、インクジェットで形成した塗布膜に対し、酸素濃度を制御した雰囲気下で紫外線照射を行った。
ＵＶ照射装置としてはオーク製作所社製 ＶＵＥ−３４００−Ｆを使用した。このＵＶ照射装置は基板加熱機構（最大３００℃）、ガス（Ｎ２、Ｏ２）導入ポート、ＵＶ照射機構（低圧水銀ランプ：ピーク波長２５４ｎｍ）を備えている。
転化工程での条件を下記に示す。
基板加熱温度：１５０℃（温度校正済み：熱電対付きＴＣウエハ）
ピーク波長 ：２５４ｎｍ
照射パワー ：２０ｍＷ／ｃｍ２（オーク製作所社製 ＵＶ−Ｍ１０で計測）
照射時間 ：３０分
雰囲気 ：Ｎ２、１ａｔｍ（１０１３．２５ｈＰａ）(Conversion process)
Next, the coating film formed by inkjet was irradiated with ultraviolet rays in an atmosphere in which the oxygen concentration was controlled.
As a UV irradiation device, VUE-3400-F manufactured by Oak Manufacturing Co., Ltd. was used. This UV irradiation apparatus includes a substrate heating mechanism (maximum 300 ° C.), a gas (N 2 , O 2 ) introduction port, and a UV irradiation mechanism (low pressure mercury lamp: peak wavelength 254 nm).
The conditions in the conversion process are shown below.
Substrate heating temperature: 150 ° C (temperature calibrated: TC wafer with thermocouple)
Peak wavelength: 254 nm
Irradiation power: 20 mW / cm 2 (measured with UV-M10 manufactured by Oak Manufacturing Co., Ltd.)
Irradiation time: 30 min Atmosphere: N 2, 1atm (1013.25hPa)
サンプルをＵＶ照射装置内のステージ上にセットする前に、予めステージを１５０℃に加熱し、ステージ温度が１５０℃に到達した後、サンプルをステージ上に配置した。 Prior to setting the sample on the stage in the UV irradiation apparatus, the stage was heated to 150 ° C. in advance, and after the stage temperature reached 150 ° C., the sample was placed on the stage.
次に、Ｎ２導入ポートから１０Ｌ／ｍｉｎの量で約５分間フローした後、ＵＶ照射を開始した。なお、ＵＶ照射中もＮ２フローを継続した。ＵＶ照射設定時間の３０分経過後、装置内からサンプルを取り出した。Next, after flowing from the N 2 introduction port at an amount of 10 L / min for about 5 minutes, UV irradiation was started. Note that the N 2 flow was continued during UV irradiation. After 30 minutes of UV irradiation set time, a sample was taken out from the apparatus.
次に半導体膜上にソース・ドレイン電極を形成した。ここでは簡便にＴＦＴを作製し、且つ、フォトリソ等で半導体膜への影響を排除するため、ソース・ドレイン電極用の１ｍｍ角の２つの孔（距離０．２ｍｍ）を有するメタルマスクを用い、下記条件によりＴｉを約５０ｎｍの厚みにスパッタ成膜してソース・ドレイン電極を形成した。 Next, source / drain electrodes were formed on the semiconductor film. Here, a metal mask having two 1 mm square holes (distance 0.2 mm) for the source and drain electrodes is used in order to easily manufacture a TFT and eliminate the influence on the semiconductor film by photolithography or the like. Depending on conditions, Ti was sputtered to a thickness of about 50 nm to form source / drain electrodes.
装置 ：アルバック社製 ＭＰＳ−６０００Ｃ
到達真空度：２×１０−５Ｐａ
成膜圧力 ：０．２５Ｐａ
投入電力 ：ＤＣ１００Ｗ
成膜時間 ：８分Apparatus: MPS-6000C manufactured by ULVAC
Ultimate vacuum: 2 × 10 −5 Pa
Deposition pressure: 0.25 Pa
Input power: DC100W
Deposition time: 8 minutes
Ｔｉ成膜によりソース・ドレイン電極を形成することで、ボトムゲート型の簡易型ＴＦＴを完成させた。 A source / drain electrode was formed by Ti film formation, thereby completing a bottom-gate type simplified TFT.
＜実施例２〜４＞
塗布工程における基板表面温度を表１に示すように変更したこと以外は実施例１と同様にしてＴＦＴを作製した。<Examples 2 to 4>
A TFT was produced in the same manner as in Example 1 except that the substrate surface temperature in the coating process was changed as shown in Table 1.
＜比較例１＞
基板を加熱しないこと以外は実施例１と同様にして塗布工程を行った後、ホットプレートにより６０℃で１分間乾燥を行った。乾燥後、実施例１と同様にして転化工程を行った。<Comparative Example 1>
A coating process was performed in the same manner as in Example 1 except that the substrate was not heated, and then dried at 60 ° C. for 1 minute using a hot plate. After drying, the conversion step was performed in the same manner as in Example 1.
＜比較例２＞
基板を加熱しないこと以外は実施例１と同様にして塗布工程を行い、乾燥を行わずに転化工程を行った。転化工程において、サンプルの塗布膜にクラックが生じたため、以後の評価を行なう事が出来なかった（表１で「ＮＧ」と記載）。比較例２における塗布膜のクラックは、インクジェットで形成した塗布膜が十分に乾燥できていない状態での加熱及びＵＶ照射によって生じたと推定される。<Comparative example 2>
The coating process was performed in the same manner as in Example 1 except that the substrate was not heated, and the conversion process was performed without drying. In the conversion process, cracks were generated in the coating film of the sample, so that the subsequent evaluation could not be performed (described as “NG” in Table 1). It is estimated that the crack of the coating film in the comparative example 2 was generated by heating and UV irradiation in a state where the coating film formed by inkjet was not sufficiently dried.
［評価］
（電気特性）
上記実施例及び比較例で作製したＴＦＴについて、半導体パラメータ・アナライザー４１５６Ｃ（アジレントテクノロジー社製）を用い、トランジスタ特性（Ｖｇ−Ｉｄ特性）の測定を行った。
Ｖｇ−Ｉｄ特性の測定は、ドレイン電圧（Ｖｄ）を＋１Ｖに固定し、ゲート電圧（Ｖｇ）を−１５Ｖ〜＋１５Ｖの範囲内で変化させ、各ゲート電圧におけるドレイン電流（Ｉｄ）を測定することにより行い、ＴＦＴとして重要特性である移動度で算出した。トランジスタ特性を図１１に、図１１から算出した移動度を表１に示した。
図１１、表１より、比較例１に比べて実施例１〜４はトランジスタ特性を示す移動度が上昇しており、特性向上が確認できた。[Evaluation]
(Electrical characteristics)
The TFT prepared in the above Examples and Comparative Examples, using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies), were measured transistor characteristics (V g -I d characteristics).
Measurement of V g -I d characteristics, the drain voltage (V d) is fixed to + 1V, the gate voltage (V g) is changed within the range of -15V~ + 15V, the drain current at gate voltages (I d) Was measured, and the mobility, which is an important characteristic of the TFT, was calculated. The transistor characteristics are shown in FIG. 11 and the mobility calculated from FIG. 11 is shown in Table 1.
From FIG. 11 and Table 1, the mobility which shows a transistor characteristic has increased compared with the comparative example 1, and the characteristic improvement was able to be confirmed.
（膜厚）
作製したＴＦＴにおける半導体層の膜厚について透過型電子顕微鏡（日立Ｈ−９０００ＮＡＲ）により観察して測定した。図１２に比較例１で作製したＴＦＴの顕微鏡写真を示す。同程度の濃度で見える場合には同程度の厚みと考えてよい。図１２では、半導体層の両縁部と中心部とでは濃度が異なり、両縁部の方が色が濃く、中心部において下層の熱酸化膜（黒色）が透けて見える。これは半導体層の膜厚の違いによるもので、両縁部に比べて中心部の方が薄くなっていることがわかる。(Film thickness)
The thickness of the semiconductor layer in the fabricated TFT was measured by observation with a transmission electron microscope (Hitachi H-9000NAR). FIG. 12 shows a photomicrograph of the TFT produced in Comparative Example 1. If it can be seen at a similar density, it may be considered as a comparable thickness. In FIG. 12, the concentration is different between both edges and the center of the semiconductor layer, and both edges are darker, and the lower thermal oxide film (black) can be seen through the center. This is due to the difference in the film thickness of the semiconductor layer, and it can be seen that the central part is thinner than both edges.
実際に膜厚を確認するために、透過型電子顕微鏡（日立Ｈ−９０００ＮＡＲ）により図１２中の半導体層の縁部（Ａ箇所）、中央部（Ｂ箇所）の各断面観測を行った。Ａ箇所は図１３、Ｂ箇所は図１４に示す。
半導体層のＡ箇所の膜厚は約３０ｎｍ、Ｂ箇所の膜厚は約２ｎｍであった。また、Ａ箇所の半導体部には、欠陥と推定される箇所（半導体層の中の色が薄い箇所）が観測された。In order to actually confirm the film thickness, each cross-sectional observation of the edge (A location) and the central portion (B location) of the semiconductor layer in FIG. 12 was performed with a transmission electron microscope (Hitachi H-9000NAR). The A part is shown in FIG. 13 and the B part is shown in FIG.
The film thickness at the A location of the semiconductor layer was about 30 nm, and the film thickness at the B location was about 2 nm. In addition, in the semiconductor portion at the location A, a location presumed to be a defect (a location where the color in the semiconductor layer is light) was observed.
このように比較例１の半導体層は膜厚違い（厚みむら）が大きく生じていた。また、縁部（Ａ箇所）にはトランジスタ特性低下を招くと考えられる欠陥が存在し、欠陥の箇所は熱酸化膜界面ではなく、熱酸化膜界面から約１０ｎｍ程度の位置に存在している。これは半導体膜への転化プロセスおいて不純物等が抜けきらないためと考える。つまり、半導体膜の厚みむらを小さく、且つ１０ｎｍ以下程度（転化後）に収めることが欠陥を減らす要因になると推定できる。 Thus, the semiconductor layer of Comparative Example 1 has a large difference in film thickness (thickness unevenness). Further, a defect that is considered to cause deterioration in transistor characteristics is present at the edge (A portion), and the defect portion is not at the thermal oxide film interface but at a position of about 10 nm from the thermal oxide film interface. This is considered because impurities or the like cannot be completely removed in the conversion process to the semiconductor film. That is, it can be estimated that reducing the thickness unevenness of the semiconductor film and keeping it within about 10 nm (after conversion) is a factor for reducing defects.
実施例１〜４における半導体層についても同様に膜厚を確認し、結果を表１に示す。 The film thicknesses of the semiconductor layers in Examples 1 to 4 were similarly confirmed, and the results are shown in Table 1.
表１に示すように、比較例１に比べて実施例１〜４の方が、Ａ箇所、Ｂ箇所の膜厚差（厚みむら）が小さくなり、特に塗布工程での基板表面温度を溶媒の沸点（１２４℃）以上とした実施例３、４においてはその差が１ｎｍ以下となっていた。 As shown in Table 1, compared with Comparative Example 1, in Examples 1 to 4, the difference in film thickness (thickness unevenness) at the A and B locations is reduced, and the substrate surface temperature in the coating process is reduced by the solvent. In Examples 3 and 4 having a boiling point (124 ° C.) or higher, the difference was 1 nm or less.
また、基板を加熱した状態でインクジェットにより塗布した実施例１〜４のＴＦＴでは高い移動度が得られ、半導体層（金属酸化物膜）のＡ箇所、Ｂ箇所における膜厚の差が小さかった。特に基板表面温度を溶媒の沸点よりも高くした実施例３、４ではより高い移動度が得られた。 In addition, high mobility was obtained in the TFTs of Examples 1 to 4 applied by inkjet while the substrate was heated, and the difference in film thickness at the A and B locations of the semiconductor layer (metal oxide film) was small. In particular, in Examples 3 and 4 where the substrate surface temperature was higher than the boiling point of the solvent, higher mobility was obtained.
＜実施例５＞
硝酸インジウム（Ｉｎ（ＮＯ３）３・ｘＨ２Ｏ、純度：４Ｎ、高純度化学研究所社製）をメタノール（試薬特級、沸点：６４．７℃、和光純薬工業社製）中に溶解させ、硝酸インジウム濃度０．５ｍｏｌ／Ｌの溶液を調製した。
基板表面温度を６５℃に調整した熱酸化膜付きＳｉ基板に対し、上記硝酸インジウム溶液を用い、実施例１と同様にしてインクジェットによって塗布膜を形成した。<Example 5>
Indium nitrate (In (NO 3 ) 3 xH 2 O, purity: 4N, manufactured by High Purity Chemical Laboratory Co., Ltd.) is dissolved in methanol (special grade reagent, boiling point: 64.7 ° C., manufactured by Wako Pure Chemical Industries, Ltd.). A solution having an indium nitrate concentration of 0.5 mol / L was prepared.
A coating film was formed by inkjet in the same manner as in Example 1 using the indium nitrate solution on a Si substrate with a thermal oxide film whose substrate surface temperature was adjusted to 65 ° C.
塗布膜を形成した後、実施例１と同様にして窒素雰囲気下（酸素濃度：５０ｐｐｍ以下）での紫外線照射、ソース・ドレイン電極の形成を行い、ボトムゲート型ＴＦＴを作製した。
作製したＴＦＴについて、実施例１と同様にして、移動度の測定及び半導体層の膜厚測定を行った。After forming the coating film, the bottom gate type TFT was produced by performing ultraviolet irradiation under nitrogen atmosphere (oxygen concentration: 50 ppm or less) and forming source / drain electrodes in the same manner as in Example 1.
About the produced TFT, it carried out similarly to Example 1, and measured the mobility and the film thickness of the semiconductor layer.
＜実施例６〜８、比較例３＞
塗布工程における基板表面温度を表２に示すように変更したこと以外は実施例５と同様にしてＴＦＴを作製し、評価を行った。
結果を表２にまとめて示す。<Examples 6 to 8, Comparative Example 3>
A TFT was produced and evaluated in the same manner as in Example 5 except that the substrate surface temperature in the coating process was changed as shown in Table 2.
The results are summarized in Table 2.
溶媒をメタノールに変更した場合も基板を加熱した状態でインクジェットにより塗布した実施例５〜８のＴＦＴでは高い移動度が得られ、半導体層のＡ箇所、Ｂ箇所における膜厚の差が比較例３よりも小さかった。特に基板表面温度を溶媒の沸点（６４．７℃）よりも高くした実施例５〜７ではより高い移動度が得られた。 Even when the solvent was changed to methanol, high mobility was obtained in the TFTs of Examples 5 to 8 applied by inkjet while the substrate was heated, and the difference in film thickness at the A and B locations of the semiconductor layer was Comparative Example 3. Was smaller than. In particular, in Examples 5 to 7 in which the substrate surface temperature was higher than the boiling point of the solvent (64.7 ° C.), higher mobility was obtained.
＜実施例９、１０、比較例４、５＞
実施例４の転化工程におけるＵＶ照射時の雰囲気中の酸素濃度を下記表３に示すように変更したこと以外は実施例４と同様にしてＴＦＴを作製し、移動度について評価を行った。実施例４とともに結果を表３に示す。<Examples 9 and 10, Comparative Examples 4 and 5>
A TFT was produced in the same manner as in Example 4 except that the oxygen concentration in the atmosphere during UV irradiation in the conversion step of Example 4 was changed as shown in Table 3 below, and the mobility was evaluated. The results are shown in Table 3 together with Example 4.
転化工程におけるＵＶ照射時の雰囲気中酸素濃度が８００００ｐｐｍ以下であれば高い移動度が得られたが、１１００００ｐｐｍの比較例４では移動度が低く、２０００００ｐｐｍの比較例５ではＴＦＴ特性を示さなかった。 High mobility was obtained when the oxygen concentration in the atmosphere during UV irradiation in the conversion step was 80000 ppm or less, but the mobility was low in Comparative Example 4 at 110000 ppm, and TFT characteristics were not exhibited in Comparative Example 5 at 200000 ppm.
日本特許出願２０１４−１１３３１９の開示はその全体が参照により本明細書に取り込まれる。
本明細書に記載された全ての文献、特許、特許出願、および技術規格は、個々の文献、特許、特許出願、および技術規格が参照により取り込まれることが具体的かつ個々に記された場合と同程度に、本明細書中に参照により取り込まれる。The entire disclosure of Japanese Patent Application No. 2014-113319 is incorporated herein by reference.
All documents, patents, patent applications, and technical standards mentioned in this specification are specifically and individually described as individual documents, patents, patent applications, and technical standards are incorporated by reference. To the same extent, it is incorporated herein by reference.
Claims (9)
前記塗布膜に対し、酸素濃度が８００００ｐｐｍ以下の雰囲気下で紫外線照射を行うことにより膜厚が１０ｎｍ以下の金属酸化物半導体膜に転化させる転化工程と、
を含む金属酸化物半導体膜の製造方法。 A coating step of forming a coating film by applying a solution containing a metal nitrate and a solvent on a substrate heated to a temperature equal to or higher than the boiling point of the solvent by an inkjet method;
A conversion step of converting the coating film into a metal oxide semiconductor film having a thickness of 10 nm or less by performing ultraviolet irradiation in an atmosphere having an oxygen concentration of 80000 ppm or less;
The manufacturing method of the metal oxide semiconductor film containing this.
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