JP6065501B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6065501B2 JP6065501B2 JP2012216843A JP2012216843A JP6065501B2 JP 6065501 B2 JP6065501 B2 JP 6065501B2 JP 2012216843 A JP2012216843 A JP 2012216843A JP 2012216843 A JP2012216843 A JP 2012216843A JP 6065501 B2 JP6065501 B2 JP 6065501B2
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- JP
- Japan
- Prior art keywords
- inductor
- frame
- semiconductor device
- lead frame
- divided
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Dc-Dc Converters (AREA)
Description
図3(a)〜(d)は、本実施形態に係る半導体装置10の製造工程を説明する説明図である。以下、半導体装置10の製造方法について、図3を参照しつつ説明する。なお、以下の製造手順は一例であり、手順を適宜入れ替えてもよい。
12 インダクタ
12i 内周側
12m 本体
14 樹脂体
18 MIC(IC素子)
P 軸(中心軸)
RM リードフレーム
Claims (3)
- リードフレームと、
前記リードフレームの主面側に搭載されたIC素子と、
前記リードフレームの裏面側に搭載されたインダクタと、
前記リードフレーム、前記IC素子、および前記インダクタを樹脂封止する樹脂体と、
を備えたSIP型の半導体装置であって、
前記インダクタが強磁性体の八角柱状コアまたは円柱状コアであり、
前記インダクタの軸に対応する位置に前記IC素子が配置され、
前記IC素子がスイッチング素子であり、
前記スイッチング素子が搭載される前記リードフレームのタブ部が、GNDまたは+Vcc電源電圧に接続されており、
前記リードフレームは、正面側から見て、中央側分割フレームと、前記中央側分割フレームの左右両側にそれぞれ位置する左側分割フレームおよび右側分割フレームとに3分割されて相互に非連続とされており、
前記左側分割フレームおよび前記右側分割フレームの一方では、基板が配置されているとともに前記基板上には基板上チップコンデンサが実装されており、
前記中央側分割フレームには前記IC素子が搭載され、
前記左側分割フレームと前記中央側分割フレームとに跨って実装された第1チップコンデンサが設けられ、
前記右側分割フレームと前記中央側分割フレームとに跨って実装された第2チップコンデンサが設けられ、
前記インダクタの実装面の両サイド側に電気接続面が形成されており、一方のサイド側の前記電気接続面が前記左側分割フレームの裏面側に面接触で直接に実装され、他方のサイド側の前記電気接続面が前記右側分割フレームの裏面側に面接触で直接に実装されていることを特徴とする半導体装置。 - 前記インダクタの中心軸方向から見て、前記インダクタの本体の内周側に前記IC素子を配置したことを特徴とする請求項1記載の半導体装置。
- 前記リードフレームは前記IC素子よりも電気伝導度が大きいことを特徴とする請求項1または2記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012216843A JP6065501B2 (ja) | 2012-09-28 | 2012-09-28 | 半導体装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2012216843A JP6065501B2 (ja) | 2012-09-28 | 2012-09-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2014072350A JP2014072350A (ja) | 2014-04-21 |
JP6065501B2 true JP6065501B2 (ja) | 2017-01-25 |
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JP2012216843A Active JP6065501B2 (ja) | 2012-09-28 | 2012-09-28 | 半導体装置 |
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JP (1) | JP6065501B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPWO2015019519A1 (ja) * | 2013-08-07 | 2017-03-02 | パナソニックIpマネジメント株式会社 | Dc−dcコンバータモジュール |
JP6720733B2 (ja) * | 2016-07-01 | 2020-07-08 | 株式会社デンソー | Dc−dcコンバータ用半導体モジュール及びパワーコントロールユニット |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0322925Y2 (ja) * | 1984-09-28 | 1991-05-20 | ||
JP2004095751A (ja) * | 2002-08-30 | 2004-03-25 | Toko Inc | 電子回路モジュール |
JP4936103B2 (ja) * | 2005-12-26 | 2012-05-23 | 日立金属株式会社 | Dc−dcコンバータ |
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2012
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