JP6038280B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6038280B2 JP6038280B2 JP2015504118A JP2015504118A JP6038280B2 JP 6038280 B2 JP6038280 B2 JP 6038280B2 JP 2015504118 A JP2015504118 A JP 2015504118A JP 2015504118 A JP2015504118 A JP 2015504118A JP 6038280 B2 JP6038280 B2 JP 6038280B2
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Description
はじめに半導体装置200の構成の概要について説明する。図1は、本実施の形態に係る半導体装置200の構造を示す断面図である。また、図2は本実施の形態の半導体素子101の金属膜105のパターンについて示す平面図である。なお図2において、図を見やすくするために、金属膜105の開口部にハッチングを付している。
図10は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図10において、図を見やすくするために、金属膜105の開口部にハッチングを付している。また、図11(A)および(B)のそれぞれは、図10中の線XIA−XIAおよびXIB−XIBに沿う構造について示す概略部分断面図である。
図12は、本実施の形態に係る半導体素子上の金属膜105のパターンについて示す平面図である。図12において、図を見やすくするために、金属膜105の開口部にハッチングを付している。図13(A)および(B)のそれぞれは、図12中の線XIIIA−XIIIAおよびXIIIB−XIIIBに沿う構造について示す概略部分断面図である。
図14は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図14において、図を見やすくするために、金属膜105上の被覆膜1101にハッチングを付している。図15は、図14中の線XV−XVに沿う構造について示す概略部分断面図である。
図16は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図16において、図を見やすくするために、被覆膜1301にハッチングを付している。図17は、図16中の線XVII−XVIIに沿う構造について示す概略部分断面図である。
本明細書は、以下の(i)〜(ix)の開示を含む。
(i) 半導体素子(101)と、
前記半導体素子の表面に設けられた電極(103)と、
前記電極の表面に半田接合後の半田形状を制御する形で設けられた第1の金属膜(105a)と、
前記第1の金属膜の外周に沿って堀状に前記電極を露出する開口(TR)を形成する露出部を形成するように前記電極の前記第1の金属膜以外の領域を覆う形状で配置された第2の金属膜(105b1)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備えたことを特徴とする半導体装置(200)。
(ii) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に半田接合後の半田形状を制御する形で設けられた第1の金属膜(105a)と、
前記第1の金属膜の周辺の前記電極が露出した露出部に、前記第1の金属膜より小さい形状で離散的に複数個配置された第2の金属膜(105b2)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備えたことを特徴とする半導体装置(200)。
(iii) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に設けられた第1の金属膜(105)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備え、
前記第1の金属膜は、前記外部電極と半田接合するための半田接合領域(105a)と、
前記半田接合領域以外の領域に、半田進展を阻害する細線幅(WD)となるように前記電極を露出させた露出部(IL)を有することを特徴とする半導体装置(200)。
(iv) 前記露出部上に半田接合時の半田形状を制御する形で設けられた被覆膜(1301)と、
を備えたことを特徴とする、上記(i)〜(iii)のいずれか1項に記載の半導体装置(200)。
(v) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に設けられた金属膜(105)と、
前記金属膜上に半田接合時の半田形状を制御する形で設けられた被覆膜(1101)と、
を備えたことを特徴とする半導体装置(200)。
(vi) 前記被覆膜が、厚さが2〜20μmのポリイミドで形成されていることを特徴とする、上記(iv)または(v)に記載の半導体装置。
(vii) 前記電極がアルミを95%以上含む材料からなっていることを特徴とする、上記(i)〜(vi)のいずれか1項に記載の半導体装置。
(viii) 上記(i)〜(vii)のいずれか1項に記載の半導体装置の製造方法であって、
前記第1の金属膜の形成工程で、ウエハ(100)面内全領域中で半導体装置として使用しない無効領域(IR)上にも前記第1の金属膜と同等の金属膜を形成することを特徴とする半導体装置の製造方法。
(ix) 前記無効領域上の金属膜に開口を形成し、前記開口がダイシングライン(DL)上にあることを特徴とする、上記(viii)に記載の半導体装置の製造方法。
Claims (14)
- 半導体素子と、
前記半導体素子の表面に設けられた素子電極と、
前記素子電極上に設けられ、内側領域と前記内側領域の周りに位置する外側領域とを有する金属膜とを備え、前記金属膜には前記内側領域および前記外側領域の間で前記素子電極を露出する開口が設けられており、前記素子電極は前記金属膜の半田濡れ性よりも低い半田濡れ性を有し、さらに
前記金属膜の前記内側領域に半田接合された外部電極を備えた、
半導体装置。 - 前記金属膜の前記内側領域および前記外側領域は前記開口によって分離されている、請求項1に記載の半導体装置。
- 前記開口は、前記金属膜の前記内側領域および前記外側領域の間に堀状に設けられている、請求項2に記載の半導体装置。
- 前記金属膜の前記外側領域は、離散的に配置された複数の部分を有する、請求項2に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域は互いに一の寸法以下でのみつながっており、前記一の寸法は、溶融した半田が前記金属膜の前記内側領域上に配置された場合に前記内側領域から前記外側領域への半田の広がりが阻害される程度に小さい、請求項1に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域は同じ材料で形成されている、請求項1〜5のいずれか1項に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域は同じ材料で形成されている、請求項1〜5のいずれか1項に記載の半導体装置。
- 前記金属膜は、少なくとも部分的に、前記素子電極の硬度よりも高い硬度を有する、請求項1〜5のいずれか1項に記載の半導体装置。
- 前記金属膜は1μm以上の厚さを有する、請求項1〜5のいずれか1項に記載の半導体装置。
- 半導体素子と、
前記半導体素子の表面に設けられた素子電極と、
前記素子電極上に設けられた金属膜と、
前記金属膜上に部分的に設けられ、前記金属膜を内側領域と前記内側領域を囲む外側領域とに区分し、前記金属膜の半田濡れ性よりも低い半田濡れ性を有する被覆膜と、
前記金属膜の前記内側領域に半田接合された外部電極とを備え、
前記金属膜には前記内側領域および前記外側領域の間で前記素子電極を露出する開口が設けられており、前記被覆膜は前記開口に配置されている、
半導体装置。 - 前記被覆膜は、厚さ2μm以上20μm以下を有するポリイミド膜を含む、請求項10に記載の半導体装置。
- 前記素子電極は、アルミニウムを95%以上含む材料から作られている、請求項10に記載の半導体装置。
- 請求項1〜5および10のいずれか1項に記載の半導体装置の製造方法であって、
前記素子電極が設けられた前記半導体素子が配置された有効領域と、前記有効領域の外側の無効領域と、を有する主面が設けられた基板を形成する工程と、
前記素子電極上に前記金属膜を形成する工程とを備え、前記金属膜は前記無効領域上に位置する部分を含み、さらに
前記金属膜が形成された後に、前記無効領域におけるダイシングラインに沿ったダイシングによって、前記半導体素子を切り出す工程と、
前記金属膜の前記内側領域に前記外部電極を半田接合する工程とを備えた、
半導体装置の製造方法。 - 前記金属膜を形成する工程は、前記ダイシングライン上において前記金属膜に開口を形成する工程を含む、請求項13に記載の半導体装置の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013046905 | 2013-03-08 | ||
JP2013046905 | 2013-03-08 | ||
PCT/JP2013/077115 WO2014136303A1 (ja) | 2013-03-08 | 2013-10-04 | 半導体装置および半導体装置の製造方法 |
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US11557531B2 (en) | 2018-09-26 | 2023-01-17 | Mitsubishi Electric Corporation | Semiconductor device with metal film, power conversion device with the semiconductor device, and method of manufacturing the semiconductor device |
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JP6766881B2 (ja) | 2016-11-08 | 2020-10-14 | 三菱電機株式会社 | 半導体装置 |
US10950558B2 (en) * | 2017-03-27 | 2021-03-16 | Mitsubishi Electric Corporation | Semiconductor device, power converter, and method for manufacturing semiconductor device |
US11127603B2 (en) * | 2017-09-04 | 2021-09-21 | Mitsubishi Electric Corporation | Semiconductor module and power conversion device |
DE102018125300A1 (de) * | 2018-10-12 | 2020-04-16 | Osram Opto Semiconductors Gmbh | Elektronisches Bauteil und Verfahren zum Aufbringen von zumindest einem Lötpad auf ein elektronisches Bauteil |
JP7472435B2 (ja) | 2019-05-13 | 2024-04-23 | 富士電機株式会社 | 半導体モジュールの製造方法 |
JP2022144711A (ja) * | 2021-03-19 | 2022-10-03 | 三菱電機株式会社 | 半導体装置の製造方法 |
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DE102008042777A1 (de) | 2008-10-13 | 2010-04-15 | Robert Bosch Gmbh | Selektiver Lötstop |
JP2010232230A (ja) * | 2009-03-25 | 2010-10-14 | Casio Computer Co Ltd | 半導体装置およびその製造方法 |
JP2010272711A (ja) | 2009-05-22 | 2010-12-02 | Mitsubishi Electric Corp | 半導体デバイスとその製造方法 |
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JP2004228461A (ja) * | 2003-01-27 | 2004-08-12 | Mitsubishi Electric Corp | 半導体装置 |
JP2006210519A (ja) * | 2005-01-26 | 2006-08-10 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2010123686A (ja) * | 2008-11-18 | 2010-06-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2011082323A (ja) * | 2009-10-07 | 2011-04-21 | Renesas Electronics Corp | 半導体装置の製造方法 |
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US11557531B2 (en) | 2018-09-26 | 2023-01-17 | Mitsubishi Electric Corporation | Semiconductor device with metal film, power conversion device with the semiconductor device, and method of manufacturing the semiconductor device |
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US10157865B2 (en) | 2018-12-18 |
JPWO2014136303A1 (ja) | 2017-02-09 |
CN105009266A (zh) | 2015-10-28 |
US20160005703A1 (en) | 2016-01-07 |
DE112013006790B8 (de) | 2022-08-18 |
CN105009266B (zh) | 2018-05-08 |
WO2014136303A1 (ja) | 2014-09-12 |
DE112013006790B4 (de) | 2022-05-25 |
DE112013006790T5 (de) | 2015-12-17 |
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