JP5997426B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
[構造説明]
図1および図2を参照しながら、本実施の形態の半導体装置(DMOSFET)の構成について説明する。図1は、本実施の形態の半導体装置の要部平面図であり、図2は、本実施の形態の半導体装置の要部断面図である。図2は、例えば、図1のA−A”断面に対応する。
次いで、図3〜図19を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図3〜図19は、本実施の形態の半導体装置の製造工程を示す要部断面図または要部平面図である。
実施の形態1においては、9つのセル領域(図1)について説明したが、この領域は、セルアレイ領域の内部に位置するものである。本実施の形態においては、セルアレイ領域の端部における各パターン(102、105、103等)のレイアウトの一例について説明する。
図20は、本実施の形態の応用例1の半導体装置の要部平面図である。図中のAEは、セルアレイ領域を示し、図20は、セルアレイ領域の端部における各パターンのレイアウトを示す。
図21は、本実施の形態の応用例2の半導体装置の要部平面図である。図中のAEは、セルアレイ領域を示し、図21は、セルアレイ領域の端部における各パターンのレイアウトを示す。
図22は、本実施の形態の応用例3の半導体装置の要部平面図である。図中のAEは、セルアレイ領域を示し、図22は、セルアレイ領域の端部における各パターンのレイアウトを示す。
実施の形態1においては、上記電界緩和領域104に、第2p+層(引出部、コンタクト部)105を形成し、第1p+層109と電気的に接続したが、第2p+層(引出部、コンタクト部)105をn+ソース層102中に設けてもよい。
実施の形態1においては、n+ソース層(ソース領域)102およびセル領域を正方形(正四角形)状とした(図1参照)が、これらの領域は、かかる形状に制限されるものではなく、他の形状としてもよい。
図25は、本実施の形態の応用例Aの半導体装置の要部平面図である。この応用例Aにおいては、n+ソース層(ソース領域)102の平面形状を長方形状(四角形状)としている。ここでは、Y方向に延在する辺が長辺であり、X方向に延在する辺が短辺となっている。このn+ソース層(ソース領域)102の外周には、pボディ層(p型ボディ領域)103が配置されている。
図26は、本実施の形態の応用例Bの半導体装置の要部平面図である。この応用例Bにおいては、n+ソース層(ソース領域)102の平面形状を正三角形状としている。このn+ソース層(ソース領域)102の外周には、pボディ層(p型ボディ領域)103が配置されている。
実施の形態1においては、層間絶縁膜IL2の上部に、ソース電極(ソース配線、配線)124を配置したが、このソース電極124上にさらに層間絶縁膜を設けゲート配線127を形成してもよい。図27は、本実施の形態の半導体装置の要部断面図である。
103 pボディ層
104 電界緩和領域
105 第2p+層
105a 第2p+層
105b 第2p+層
106 SiC基板
107 n−ドリフト層
108 フォトレジスト膜
108a 露出領域
109 第1p+層
110 フォトレジスト膜
110a 開口部
112 フォトレジスト膜
113 フォトレジスト膜
114 フォトレジスト膜
115 ゲート絶縁膜
116 ゲート電極
117 フォトレジスト膜
121 ドレイン電極
122 窒化チタン
123 フォトレジスト膜
124 ソース電極
124s 金属シリサイド
127 ゲート配線
202 n+ソース層
203 pボディ層
205 p+層
206 SiC基板
207 n−ドリフト層
216 ゲート電極
221 裏面電極
224a 導電性膜
224b 導電性膜
AE セルアレイ領域
C 寄生容量
I サージ電流
IL1 絶縁膜
IL2 層間絶縁膜
IL3 層間絶縁膜
R 抵抗
Claims (18)
- 基板の第1面側の上部に配置された、第1導電型の第1ソース領域と第2ソース領域と、
前記第1ソース領域および前記第2ソース領域を囲む第2導電型の第1半導体領域であって、チャネル領域を有する第1半導体領域と、
前記第1半導体領域を囲む前記第1導電型の第2半導体領域と、
前記チャネル領域の上部にゲート絶縁膜を介して配置されたゲート電極と、
前記第1半導体領域中に配置された前記第2導電型の埋込み半導体領域であって、前記第1半導体領域より前記第2導電型の不純物の濃度が高い埋込み半導体領域と、
前記第1ソース領域と前記第2ソース領域との間に配置された前記第2導電型の第3半導体領域と、を有し、
前記第1導電型の第1ソース領域は第1セル領域に配置され、
前記第1導電型の第2ソース領域は第2セル領域に配置され、
前記第1セル領域と前記第2セル領域とは、平面視において、前記第3半導体領域の両側に対角に配置され、
前記第3半導体領域の下部に接するよう前記埋込み半導体領域が配置され、前記埋込み半導体領域は、前記第1ソース領域および前記第2ソース領域の下方に延在することを特徴とする半導体装置。 - 前記第1ソース領域の底部は、前記埋込み半導体領域の上部より浅く、前記第1ソース領域の底部と前記埋込み半導体領域の上部との間には、前記第1半導体領域が介在することを特徴とする請求項1記載の半導体装置。
- 前記第3半導体領域は、前記第1半導体領域より前記第2導電型の不純物の濃度が高いことを特徴とする請求項1記載の半導体装置。
- 前記第1ソース領域内に配置された第4半導体領域を有し、
前記第4半導体領域の下部に接するよう前記埋込み半導体領域が配置されることを特徴とする請求項1記載の半導体装置。 - 前記第1ソース領域および前記第3半導体領域は、第1配線に接続されていることを特徴とする請求項1記載の半導体装置。
- 前記第2半導体領域は、前記基板の第2面側に配置されたドレイン電極と接続されていることを特徴とする請求項1記載の半導体装置。
- 基板の第1面側の上部に配置された第2導電型の第1半導体領域と、
前記基板の第1面側の上部に配置され、平面視において、前記第1半導体領域の周囲であって、前記第1半導体領域の両側の対角の位置に、離間して配置された第1導電型の第1ソース領域と前記第1導電型の第2ソース領域と、
前記第1導電型の第1ソース領域および前記第1導電型の第2ソース領域を囲む前記第2導電型の第2半導体領域と、
前記第2半導体領域の上部にゲート絶縁膜を介して配置されたゲート電極と、
前記第2半導体領域中に配置された前記第2導電型の埋込み半導体領域であって、前記第1半導体領域の下部から前記第1ソース領域および前記第2ソース領域の下方に延在し、前記第2半導体領域より前記第2導電型の不純物の濃度が高い埋込み半導体領域と、
を有することを特徴とする半導体装置。 - 前記第1半導体領域は、前記第2半導体領域より前記第2導電型の不純物の濃度が高いことを特徴とする請求項7記載の半導体装置。
- 前記第1ソース領域、前記第2ソース領域および前記第1半導体領域は、第1配線に接続されていることを特徴とする請求項7記載の半導体装置。
- 前記第2半導体領域に接する前記第1導電型の第3半導体領域を有し、
前記第3半導体領域は、前記基板の第2面側に配置されたドレイン電極と接続されていることを特徴とする請求項7記載の半導体装置。 - 前記第1ソース領域および前記第2ソース領域のそれぞれの平面形状は、四角形であることを特徴とする請求項7記載の半導体装置。
- 前記第1ソース領域および前記第2ソース領域のそれぞれの平面形状は、三角形であることを特徴とする請求項7記載の半導体装置。
- 前記第1ソース領域および前記第2ソース領域のそれぞれの平面形状は、多角形であることを特徴とする請求項7記載の半導体装置。
- (a)第1面側に、第1導電型の第1半導体領域を有する基板を準備する工程と、
(b)前記第1半導体領域中に第2導電型の第2半導体領域を形成する工程と、
(c)前記第2半導体領域中に前記第2導電型の埋め込み半導体領域を形成する工程と、
(d)前記第2半導体領域中であって、前記埋め込み半導体領域の上方に、前記第1導電型の第1ソース領域と第2ソース領域を形成する工程と、
(e)前記(c)工程の前、若しくは後に、
前記第2半導体領域中であって、前記第1ソース領域と前記第2ソース領域との間であり、かつ、前記埋め込み半導体領域上に、前記埋め込み半導体領域まで到達する前記第2導電型の第3半導体領域を形成する工程を有し、
前記第1ソース領域と前記第2ソース領域とは、前記第3半導体領域の両側の対角の位置に配置される、ことを特徴とする半導体装置の製造方法。 - 前記埋め込み半導体領域および前記第3半導体領域の前記第2導電型の不純物濃度は、前記第2半導体領域の前記第2導電型の不純物濃度より高いことを特徴とする請求項14記載の半導体装置の製造方法。
- (f)前記第2半導体領域上にゲート絶縁膜を介してゲート電極を形成する工程を有することを特徴とする請求項14記載の半導体装置の製造方法。
- (g)前記基板の第2面側に、前記第1半導体領域と電気的に接続されるドレイン電極を形成する工程を有することを特徴とする請求項14記載の半導体装置の製造方法。
- (h)前記第1ソース領域、前記第2ソース領域および第3半導体領域と電気的に接続されるソース電極を形成する工程を有することを特徴とする請求項14記載の半導体装置の製造方法。
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