JP5997197B2 - Wiring board - Google Patents

Wiring board Download PDF

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JP5997197B2
JP5997197B2 JP2014067353A JP2014067353A JP5997197B2 JP 5997197 B2 JP5997197 B2 JP 5997197B2 JP 2014067353 A JP2014067353 A JP 2014067353A JP 2014067353 A JP2014067353 A JP 2014067353A JP 5997197 B2 JP5997197 B2 JP 5997197B2
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semiconductor element
element connection
connection pad
diameter
conductor
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JP2015179794A (en
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誠司 服部
誠司 服部
馨 荒木
馨 荒木
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

本発明は、電極ピッチの異なる複数の半導体素子等を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a plurality of semiconductor elements having different electrode pitches.

近年、携帯電話や音楽プレーヤーなどに代表される電子機器の高機能化が進む中で、それらに使用される配線基板には、様々な機能を持つ複数の半導体素子が搭載されるものがある。その一例として、演算処理用の大型の半導体素子とメモリー用の小型の半導体素子とを同一面に搭載した配線基板が挙げられる。   In recent years, as electronic devices typified by mobile phones and music players have become highly functional, some of the wiring boards used for them are equipped with a plurality of semiconductor elements having various functions. As an example, there is a wiring board in which a large semiconductor element for arithmetic processing and a small semiconductor element for memory are mounted on the same surface.

図５に、このような複数の半導体素子が搭載される従来の配線基板Ｂを示す。配線基板Ｂは、絶縁基板２１と、配線導体２２と、絶縁層２３と、ソルダーレジスト層２４とを備えている。配線基板Ｂの上面中央部には、演算処理用等の大型の第１半導体素子Ｓ１を搭載するための第１搭載部２１ａが形成されている。また、配線基板Ｂの上面外周部には、メモリー用等の小型の第２半導体素子Ｓ２を搭載するための第２搭載部２１ｂが形成されている。   FIG. 5 shows a conventional wiring board B on which such a plurality of semiconductor elements are mounted. The wiring board B includes an insulating substrate 21, a wiring conductor 22, an insulating layer 23, and a solder resist layer 24. A first mounting portion 21a for mounting a large first semiconductor element S1 for arithmetic processing or the like is formed at the center of the upper surface of the wiring board B. A second mounting portion 21b for mounting a small second semiconductor element S2 for memory or the like is formed on the outer peripheral portion of the upper surface of the wiring board B.

絶縁基板２１は、例えばガラス−エポキシ樹脂から成る。絶縁基板２１には、その上面から下面にかけて貫通する複数のスルーホール２５が形成されている。絶縁基板２１表面およびスルーホール２５内には、配線導体２２が被着されている。絶縁基板２１上面の配線導体２２は、配線基板Ｂ上面側における下層導体２６を形成している。絶縁基板２１下面の配線導体２２は、外部の電気回路基板に接続する外部接続パッド２７を形成している。   The insulating substrate 21 is made of, for example, glass-epoxy resin. The insulating substrate 21 is formed with a plurality of through holes 25 penetrating from the upper surface to the lower surface. A wiring conductor 22 is deposited on the surface of the insulating substrate 21 and in the through hole 25. The wiring conductor 22 on the upper surface of the insulating substrate 21 forms a lower layer conductor 26 on the upper surface side of the wiring substrate B. The wiring conductor 22 on the lower surface of the insulating substrate 21 forms an external connection pad 27 connected to an external electric circuit board.

絶縁層２３は、絶縁基板２１の上面に積層されている。絶縁層２３には複数のビアホール２８が形成されている。絶縁層２３の上面およびビアホール２８内には、配線導体２２が被着されている。絶縁層２３の上面に被着された配線導体２２は、配線基板Ｂ上面側における上層導体２９を形成している。またビアホール２８内に被着された配線導体２２は、上層導体２９と下層導体２６とを接続する第１および第２ビア導体３０ａ、３０ｂを形成している。   The insulating layer 23 is stacked on the upper surface of the insulating substrate 21. A plurality of via holes 28 are formed in the insulating layer 23. A wiring conductor 22 is deposited on the upper surface of the insulating layer 23 and in the via hole 28. The wiring conductor 22 deposited on the upper surface of the insulating layer 23 forms an upper layer conductor 29 on the upper surface side of the wiring board B. The wiring conductor 22 deposited in the via hole 28 forms first and second via conductors 30 a and 30 b that connect the upper layer conductor 29 and the lower layer conductor 26.

第１搭載部２１ａには、第１半導体素子Ｓ１の電極Ｔ１と接続される第１半導体素子接続パッド３１ａが電極Ｔ１と対応する配列で形成されている。第１半導体素子接続パッド３１ａは、その直下に形成された第１ビア導体３０ａにより下層導体２６に接続されている。また、第２搭載部２１ｂには、第２半導体素子Ｓ２の電極Ｔ２と接続される第２半導体素子接続パッド３１ｂが電極Ｔ２と対応する配列で形成されている。第２半導体素子接続パッド３１ｂは、その直下に形成された第２ビア導体３０ｂにより下層導体２６に接続されている。なお、第１半導体素子Ｓ１の電極Ｔ１は、比較的大きな第１電極ピッチＰ１で配置されており、第２半導体素子Ｓ２は、第１電極ピッチＰ１より小さい第２電極ピッチＰ２で配置されている。第１ビア導体３０ａおよび第２ビア導体３０ｂは同じ直径である。   In the first mounting portion 21a, first semiconductor element connection pads 31a connected to the electrode T1 of the first semiconductor element S1 are formed in an array corresponding to the electrode T1. The first semiconductor element connection pad 31a is connected to the lower layer conductor 26 by a first via conductor 30a formed immediately below the first semiconductor element connection pad 31a. In the second mounting portion 21b, second semiconductor element connection pads 31b connected to the electrode T2 of the second semiconductor element S2 are formed in an array corresponding to the electrode T2. The second semiconductor element connection pad 31b is connected to the lower layer conductor 26 by a second via conductor 30b formed immediately below the second semiconductor element connection pad 31b. The electrodes T1 of the first semiconductor element S1 are arranged with a relatively large first electrode pitch P1, and the second semiconductor element S2 is arranged with a second electrode pitch P2 smaller than the first electrode pitch P1. . The first via conductor 30a and the second via conductor 30b have the same diameter.

ソルダーレジスト層２４は、絶縁層２３の上面および絶縁基板２１の下面に被着されている。上面側のソルダーレジスト層２４は、第１および第２半導体素子接続パッド３１ａ、３１ｂを露出する第１開口部２４ａおよび第２開口部２４ｂを有している。そして、下面側のソルダーレジスト層２４は、外部接続パッド２７を露出する第３開口部２４ｃを有している。   The solder resist layer 24 is attached to the upper surface of the insulating layer 23 and the lower surface of the insulating substrate 21. The solder resist layer 24 on the upper surface side has a first opening 24a and a second opening 24b that expose the first and second semiconductor element connection pads 31a and 31b. The solder resist layer 24 on the lower surface side has a third opening 24 c that exposes the external connection pad 27.

そして、第１および第２半導体素子Ｓ１、Ｓ２の電極Ｔ１、Ｔ２を、それぞれ対応する第１および第２半導体素子接続パッド３１ａ、３１ｂに半田を介して接続するとともに、外部接続パッド２７を外部の電気回路基板の配線導体に半田を介して接続することにより、第１および第２半導体素子Ｓ１、Ｓ２が外部の電気回路基板に電気的に接続されて稼働する。   The electrodes T1 and T2 of the first and second semiconductor elements S1 and S2 are connected to the corresponding first and second semiconductor element connection pads 31a and 31b via solder, respectively, and the external connection pad 27 is connected to the outside. By connecting to the wiring conductor of the electric circuit board via solder, the first and second semiconductor elements S1, S2 are electrically connected to the external electric circuit board and operate.

ところが、上述のように電子機器の高機能化に伴い第１半導体素子Ｓ１が大型化してくると、第１半導体素子Ｓ１を配線基板Ｂに半田で接続するときや、第１半導体素子Ｓ１が稼働するときの熱履歴により、第１半導体素子Ｓ１と配線基板Ｂとの間に大きな熱伸縮差が生じるようになる。その結果、第１半導体素子Ｓ１の電極Ｔ１とこれに接続された第１半導体素子接続パッド３１ａとの間に大きな熱応力が発生し、その熱応力が第１ビア導体３０ａと下層導体２６との接続部に集中して作用することにより、第１ビア導体３０ａと下層導体２６との接合面にクラックが発生してしまい、第１半導体素子Ｓ１を安定的に稼働させることができない場合がある。   However, as described above, when the size of the first semiconductor element S1 is increased with the enhancement of functionality of the electronic device, the first semiconductor element S1 is activated when the first semiconductor element S1 is connected to the wiring board B by soldering. Due to the thermal history at the time, a large thermal expansion / contraction difference occurs between the first semiconductor element S1 and the wiring board B. As a result, a large thermal stress is generated between the electrode T1 of the first semiconductor element S1 and the first semiconductor element connection pad 31a connected thereto, and the thermal stress is generated between the first via conductor 30a and the lower conductor 26. By acting on the connecting portion in a concentrated manner, a crack is generated in the joint surface between the first via conductor 30a and the lower layer conductor 26, and the first semiconductor element S1 may not be stably operated.

特開２００３−３２４１８０号公報JP 2003-324180 A

本発明は、ビア導体と下層導体との接合強度を向上させることで、半導体素子と配線基板との熱伸縮差により生じる応力でビア導体と下層導体との間にクラックが発生することを抑制する。これにより、半導体素子を安定的に稼働させることが可能な配線基板を提供することを課題とする。   The present invention suppresses the occurrence of cracks between the via conductor and the lower layer conductor due to the stress caused by the difference in thermal expansion and contraction between the semiconductor element and the wiring board by improving the bonding strength between the via conductor and the lower layer conductor. . Accordingly, an object is to provide a wiring board capable of stably operating a semiconductor element.

本発明の配線基板は、下面に下層導体を有する絶縁層と、絶縁層上に形成されており第１電極ピッチを有する第１半導体素子を搭載する第１搭載部と、絶縁層上に形成されており第１電極ピッチより小さい第２電極ピッチを有するとともに第１半導体素子の対角線長さより小さい対角線長さを有する第２半導体素子を搭載する第２搭載部と、第１搭載部に第１電極ピッチと同ピッチで形成された第１半導体素子接続パッドと、第２搭載部に第２電極ピッチと同ピッチで形成された第２半導体素子接続パッドと、第１半導体素子接続パッド下の絶縁層に形成された第１ビアホールと、第２半導体素子接続パッド下の絶縁層に形成された第２ビアホールと、第１半導体素子接続パッドと一体的に形成されており第１ビアホールを充填して下層導体と電気的に接続された第１ビア導体と、第２半導体素子接続パッドと一体的に形成されており第２ビアホールを充填して下層導体と電気的に接続された第２ビア導体と、を具備して成る配線基板であって、第１ビア導体の径が、第２ビア導体の径よりも大きいことを特徴とするものである。   The wiring board of the present invention is formed on an insulating layer having a lower conductor on the lower surface, a first mounting portion on the insulating layer for mounting the first semiconductor element having the first electrode pitch, and on the insulating layer. A second mounting portion for mounting a second semiconductor element having a second electrode pitch smaller than the first electrode pitch and having a diagonal length smaller than the diagonal length of the first semiconductor element, and the first electrode on the first mounting portion. A first semiconductor element connection pad formed at the same pitch as the pitch; a second semiconductor element connection pad formed at the same pitch as the second electrode pitch on the second mounting portion; and an insulating layer under the first semiconductor element connection pad The first via hole formed in the first semiconductor device, the second via hole formed in the insulating layer under the second semiconductor element connection pad, and the first via hole are formed integrally with the first semiconductor element connection pad to fill the lower layer conductor A first via conductor electrically connected; and a second via conductor formed integrally with the second semiconductor element connection pad and filling the second via hole and electrically connected to the lower conductor. In the wiring board, the diameter of the first via conductor is larger than the diameter of the second via conductor.

本発明の別の配線基板は、下面に下層導体を有する絶縁層と、絶縁層上に形成されており第１電極ピッチを有する第１半導体素子を搭載する第１搭載部と、絶縁層上に形成されており第１電極ピッチより小さい第２電極ピッチを有するとともに第１半導体素子の対角線長さより小さい対角線長さを有する第２半導体素子を搭載する第２搭載部と、第１搭載部に第１電極ピッチと同ピッチで形成された第１半導体素子接続パッドと、第２搭載部に第２電極ピッチと同ピッチで形成された第２半導体素子接続パッドと、第１半導体素子接続パッド下の絶縁層に形成された第１ビアホールと、第２半導体素子接続パッド下の絶縁層に形成された第２ビアホールと、第１半導体素子接続パッドと一体的に形成されており第１ビアホールを充填して下層導体と電気的に接続された第１ビア導体と、第２半導体素子接続パッドと一体的に形成されており第２ビアホールを充填して下層導体と電気的に接続された第２ビア導体と、を具備して成る配線基板であって、第１搭載部において、外周部に配設された第１半導体素子接続パッドと一体的に形成された第１ビア導体の径が、中央部に配設された第１半導体素子接続パッドと一体的に形成された第１ビア導体の径、および第２ビア導体の径よりも大きいことを特徴とするものである。   Another wiring board according to the present invention includes an insulating layer having a lower layer conductor on a lower surface, a first mounting portion that is formed on the insulating layer and mounts a first semiconductor element having a first electrode pitch, and an insulating layer. A second mounting portion for mounting a second semiconductor element formed and having a second electrode pitch smaller than the first electrode pitch and having a diagonal length smaller than the diagonal length of the first semiconductor element; A first semiconductor element connection pad formed at the same pitch as the one electrode pitch; a second semiconductor element connection pad formed at the same pitch as the second electrode pitch on the second mounting portion; The first via hole formed in the insulating layer, the second via hole formed in the insulating layer under the second semiconductor element connection pad, and the first semiconductor element connection pad are integrally formed to fill the first via hole. Lower layer A first via conductor electrically connected to the body, a second via conductor formed integrally with the second semiconductor element connection pad and filling the second via hole and electrically connected to the lower conductor; In the first mounting portion, the diameter of the first via conductor formed integrally with the first semiconductor element connection pad disposed in the outer peripheral portion is disposed in the central portion. The diameter of the first via conductor formed integrally with the formed first semiconductor element connection pad and the diameter of the second via conductor are larger.

本発明の配線基板によれば、第１半導体素子の電極が接続される第１半導体素子接続パッドと一体的に形成された第１ビア導体は、第２半導体素子の電極が接続される第２半導体素子接続パッドと一体的に形成された第２ビア導体よりも大きな径を有している。したがって、第１ビア導体と下層導体との接続面を大きくすることで第１ビア導体と下層導体との接合強度を向上させることができる。これにより、第２半導体素子の対角線長さよりも大きな対角線長さを有する第１半導体素子と配線基板との熱伸縮の差に起因して発生する応力により第１ビア導体と下層導体との間にクラックが発生することを抑制して、半導体素子を安定的に稼働させることが可能な配線基板を提供することができる。なお、第１半導体素子の電極ピッチは第２半導体素子の電極ピッチよりも大きいことから、第１ビア導体の径を大きなものとしたとしても、第１ビア導体同士の間に十分な絶縁間隔を設けることができる。さらに、第２半導体素子は対角線長さが短いことから、第２半導体素子と配線基板との熱伸縮差に起因する大きな応力が発生することはなく、したがって第２ビア導体の径が小さいままであっても第２ビア導体と下層導体との間にクラックが発生することはない。   According to the wiring board of the present invention, the first via conductor formed integrally with the first semiconductor element connection pad to which the electrode of the first semiconductor element is connected is connected to the second via of which the electrode of the second semiconductor element is connected. It has a larger diameter than the second via conductor formed integrally with the semiconductor element connection pad. Therefore, it is possible to improve the bonding strength between the first via conductor and the lower layer conductor by increasing the connection surface between the first via conductor and the lower layer conductor. As a result, a stress generated due to a difference in thermal expansion and contraction between the first semiconductor element having a diagonal length larger than the diagonal length of the second semiconductor element and the wiring board causes a gap between the first via conductor and the lower layer conductor. It is possible to provide a wiring board capable of suppressing the occurrence of cracks and stably operating the semiconductor element. In addition, since the electrode pitch of the first semiconductor element is larger than the electrode pitch of the second semiconductor element, even if the diameter of the first via conductor is made large, a sufficient insulation interval is provided between the first via conductors. Can be provided. Further, since the diagonal length of the second semiconductor element is short, no large stress is generated due to the thermal expansion / contraction difference between the second semiconductor element and the wiring board, and therefore the diameter of the second via conductor remains small. Even if it exists, a crack does not generate | occur | produce between a 2nd via conductor and a lower layer conductor.

本発明の別の配線基板によれば、第１搭載部において、外周部に配設された第１半導体素子接続パッドと一体的に形成された第１ビア導体の径が、中央部に配設された第１半導体素子接続パッドと一体的に形成された第１ビア導体の径、および第２ビア導体の径よりも大きな径を有している。したがって、第１搭載部の外周部に配設された第１半導体素子接続パッドと一体的に形成された第１ビア導体と下層導体との接続面を大きくすることで第１ビア導体と下層導体との接合強度を向上させることができる。このため、第２半導体素子の対角線長さよりも大きな対角線長さを有する第１半導体素子と配線基板との熱伸縮の差に起因して発生する応力が特に集中する第１搭載部の外周部の第１半導体素子接続パッドに接続された第１ビア導体と下層導体との間にクラックが生じることを抑制できる。これにより、半導体素子を安定的に稼働させることが可能な配線基板を提供することができる。なお、第１半導体素子の電極ピッチは第２半導体素子の電極ピッチよりも大きいことから、第１ビア導体の径を大きなものとしたとしても、第１ビア導体同士の間に十分な絶縁間隔を設けることができる。さらに、第２半導体素子は対角線長さが短いことから、第２半導体素子と配線基板との熱伸縮差に起因する大きな応力が発生することはなく、したがって第２ビア導体の径が小さいままであっても第２ビア導体と下層導体との間にクラックが発生することはない。   According to another wiring board of the present invention, in the first mounting portion, the diameter of the first via conductor formed integrally with the first semiconductor element connection pad disposed in the outer peripheral portion is disposed in the central portion. The first via conductor formed integrally with the formed first semiconductor element connection pad has a diameter larger than the diameter of the second via conductor. Therefore, the first via conductor and the lower conductor are enlarged by increasing the connection surface between the first via conductor and the lower conductor formed integrally with the first semiconductor element connection pad disposed on the outer peripheral portion of the first mounting portion. The joint strength can be improved. For this reason, the stress on the outer peripheral portion of the first mounting portion where stress generated due to the difference in thermal expansion and contraction between the first semiconductor element having a diagonal length larger than the diagonal length of the second semiconductor element and the wiring substrate is particularly concentrated It can suppress that a crack arises between the 1st via conductor connected to the 1st semiconductor element connection pad, and a lower layer conductor. Thereby, the wiring board which can operate a semiconductor element stably can be provided. In addition, since the electrode pitch of the first semiconductor element is larger than the electrode pitch of the second semiconductor element, even if the diameter of the first via conductor is made large, a sufficient insulation interval is provided between the first via conductors. Can be provided. Further, since the diagonal length of the second semiconductor element is short, no large stress is generated due to the thermal expansion / contraction difference between the second semiconductor element and the wiring board, and therefore the diameter of the second via conductor remains small. Even if it exists, a crack does not generate | occur | produce between a 2nd via conductor and a lower layer conductor.

図１は、本発明の配線基板の実施の形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、本発明の配線基板の別の実施の形態の一例を示す概略断面図である。FIG. 2 is a schematic sectional view showing an example of another embodiment of the wiring board of the present invention. 図３は、本発明の配線基板のさらに別の実施の形態の一例を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing an example of still another embodiment of the wiring board of the present invention. 図４は、本発明の配線基板の異なる実施の形態の一例を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing an example of a different embodiment of the wiring board of the present invention. 図５は、従来の配線基板の実施の形態の一例を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing an example of an embodiment of a conventional wiring board.

次に、本発明の配線基板の実施形態の一例を、図１を基に説明する。
図１に示すように本例の配線基板Ａは、絶縁基板１と、配線導体２と、絶縁層３と、ソルダーレジスト層４とを備えている。配線基板Ａの上面中央部には、演算処理用等の大型の第１半導体素子Ｓ１を搭載するための第１搭載部１ａが形成されている。また、配線基板Ａの上面外周部には、メモリー用等の小型の第２半導体素子Ｓ２を搭載するための第２搭載部１ｂが形成されている。 Next, an example of an embodiment of the wiring board of the present invention will be described with reference to FIG.
As shown in FIG. 1, the wiring board A of this example includes an insulating substrate 1, a wiring conductor 2, an insulating layer 3, and a solder resist layer 4. In the center of the upper surface of the wiring board A, a first mounting portion 1a for mounting a large first semiconductor element S1 for arithmetic processing or the like is formed. Further, a second mounting portion 1b for mounting a small second semiconductor element S2 for memory or the like is formed on the outer peripheral portion of the upper surface of the wiring board A.

絶縁基板１は、例えばガラス−エポキシ樹脂から成る。絶縁基板１には、その上面から下面にかけて貫通する複数のスルーホール５が形成されている。絶縁基板１表面およびスルーホール５内には、配線導体２の一部が被着されている。絶縁基板１上面の配線導体２は、配線基板Ａ上面側における下層導体６を形成している。絶縁基板１下面の配線導体２は、外部の電気回路基板に接続する外部接続パッド７を形成している。   The insulating substrate 1 is made of, for example, glass-epoxy resin. The insulating substrate 1 is formed with a plurality of through holes 5 penetrating from the upper surface to the lower surface. A part of the wiring conductor 2 is deposited on the surface of the insulating substrate 1 and in the through hole 5. The wiring conductor 2 on the upper surface of the insulating substrate 1 forms a lower layer conductor 6 on the upper surface side of the wiring substrate A. The wiring conductor 2 on the lower surface of the insulating substrate 1 forms an external connection pad 7 connected to an external electric circuit board.

絶縁基板１は、例えば次のように形成される。まず、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料を、圧力下で熱硬化して絶縁板を形成する。次に、ドリル加工やブラスト加工、あるいはレーザー加工によりスルーホール５を形成することで絶縁基板１が形成される。   The insulating substrate 1 is formed as follows, for example. First, an electrically insulating material obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is thermoset under pressure to form an insulating plate. Next, the insulating substrate 1 is formed by forming the through hole 5 by drilling, blasting, or laser processing.

絶縁層３は、絶縁基板１の上面に積層されている。第１搭載部１ａにおける絶縁層３には、複数の第１ビアホール８ａが形成されている。また、第２搭載部１ｂにおける絶縁層３には、複数の第２ビアホール８ｂが形成されている。絶縁層３は、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る電気絶縁シートを、真空状態で絶縁基板１上にラミーネートした後で熱硬化することで形成される。第１および第２ビアホール８ａ、８ｂは、例えばレーザー加工で形成される。なお、レーザー加工後は、デスミア処理を行うことが好ましい。なお、第１ビアホール８ａおよび第２ビアホール８ｂは、下層導体６を底面として形成されている。   The insulating layer 3 is laminated on the upper surface of the insulating substrate 1. A plurality of first via holes 8a are formed in the insulating layer 3 in the first mounting portion 1a. A plurality of second via holes 8b are formed in the insulating layer 3 in the second mounting portion 1b. The insulating layer 3 is formed by laminating an electrically insulating sheet made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin on the insulating substrate 1 in a vacuum state and then thermosetting it. The first and second via holes 8a and 8b are formed by, for example, laser processing. In addition, it is preferable to perform a desmear process after laser processing. The first via hole 8a and the second via hole 8b are formed with the lower layer conductor 6 as a bottom surface.

絶縁層３の上面ならびに第１および第２ビアホール８ａ、８ｂ内には、配線導体２の一部が被着されている。絶縁層３の上面に被着された配線導体２は、配線基板Ａ上面側における上層導体９を形成している。また、第１および第２ビアホール８ａ、８ｂ内に被着された配線導体２は、上層導体９と一体的に形成された第１ビア導体１０ａおよび第２ビア導体１０ｂを形成している。第１ビア導体１０ａおよび第２ビア導体１０ｂは、それぞれ第１ビアホール８ａおよび第２ビアホール８ｂ内を充填しており、上層導体９と下層導体６とを接続している。これらの上層導体９および第１ビア導体１０ａ、第２ビア導体１０ｂは、銅めっき等の良導電性材料から成り、例えば周知のセミアディティブ法により形成される。   A part of the wiring conductor 2 is deposited on the upper surface of the insulating layer 3 and in the first and second via holes 8a and 8b. The wiring conductor 2 deposited on the upper surface of the insulating layer 3 forms an upper layer conductor 9 on the upper surface side of the wiring board A. The wiring conductor 2 deposited in the first and second via holes 8a and 8b forms a first via conductor 10a and a second via conductor 10b formed integrally with the upper layer conductor 9. The first via conductor 10 a and the second via conductor 10 b fill the first via hole 8 a and the second via hole 8 b, respectively, and connect the upper layer conductor 9 and the lower layer conductor 6. These upper layer conductor 9, first via conductor 10a, and second via conductor 10b are made of a highly conductive material such as copper plating, and are formed by, for example, a known semi-additive method.

上層導体９の一部は、第１搭載部１ａにおいて、第１半導体素子Ｓ１の電極Ｔ１と接続される第１半導体素子接続パッド１１ａを形成している。第１半導体素子接続パッド１１ａは第１半導体素子Ｓ１の電極Ｔ１と対応する配列で形成されている。第１半導体素子接続パッド１１ａは、その直下に形成された第１ビア導体１０ａにより下層導体６に接続されている。また、上層導体９の別の一部は、第２搭載部１ｂにおいて、第２半導体素子Ｓ２の電極Ｔ２と接続される第２半導体素子接続パッド１１ｂを形成している。第２半導体素子接続パッド１１ｂは第２半導体素子Ｓ２の電極Ｔ２と対応する配列で形成されている。第２半導体素子接続パッド１１ｂは、その直下に形成された第２ビア導体１０ｂにより下層導体６に接続されている。なお、第１半導体素子Ｓ１の電極Ｔ１は、比較的大きな第１電極ピッチＰ１で配置されており、第２半導体素子Ｓ２は、第１電極ピッチＰ１より小さい第２電極ピッチＰ２で配置されている。第１電極ピッチＰ１は、およそ１５０〜１６０μｍ程度であり、第２電極ピッチＰ２は、およそ５０〜６０μｍ程度である。   A part of the upper layer conductor 9 forms a first semiconductor element connection pad 11a connected to the electrode T1 of the first semiconductor element S1 in the first mounting portion 1a. The first semiconductor element connection pads 11a are formed in an array corresponding to the electrode T1 of the first semiconductor element S1. The first semiconductor element connection pad 11a is connected to the lower layer conductor 6 by a first via conductor 10a formed immediately below the first semiconductor element connection pad 11a. Another part of the upper layer conductor 9 forms a second semiconductor element connection pad 11b connected to the electrode T2 of the second semiconductor element S2 in the second mounting portion 1b. The second semiconductor element connection pads 11b are formed in an array corresponding to the electrode T2 of the second semiconductor element S2. The second semiconductor element connection pad 11b is connected to the lower layer conductor 6 by a second via conductor 10b formed immediately below the second semiconductor element connection pad 11b. The electrodes T1 of the first semiconductor element S1 are arranged with a relatively large first electrode pitch P1, and the second semiconductor element S2 is arranged with a second electrode pitch P2 smaller than the first electrode pitch P1. . The first electrode pitch P1 is about 150 to 160 μm, and the second electrode pitch P2 is about 50 to 60 μm.

ところで、本例の配線基板Ａにおいては、第１ビアホール８ａの径は、およそφ２８〜３３μｍ程度であり、第２ビアホール８ｂの径は、およそφ２０〜２５μｍ程度である。
第１および第２ビア導体１０ａ、１０ｂは、それぞれ第１および第２ビアホール８ａ、８ｂ内を充填しているため、第１ビア導体１０ａの径は、第２ビア導体１０ｂの径よりも大きい。 By the way, in the wiring board A of this example, the diameter of the first via hole 8a is approximately φ28 to 33 μm, and the diameter of the second via hole 8b is approximately φ20 to 25 μm.
Since the first and second via conductors 10a and 10b fill the first and second via holes 8a and 8b, respectively, the diameter of the first via conductor 10a is larger than the diameter of the second via conductor 10b.

ソルダーレジスト層４は、絶縁層３の上面および絶縁基板１の下面に被着されている。上面側のソルダーレジスト層４は、第１および第２半導体素子接続パッド１１ａ、１１ｂを露出する第１開口部４ａおよび第２開口部４ｂを有している。そして、下面側のソルダーレジスト層４は、外部接続パッド７を露出する第３開口部４ｃを有している。
なお、図１に示すように、第１開口部４ａの開口径は、第２開口部４ｂの開口径よりも大きいことが好ましい。このように、第１半導体素子Ｓ１の電極Ｔ１と第１半導体素子接続パッド１１ａとの接続面積を大きくすることで両者の接合強度が向上できる。その結果、第２半導体素子Ｓ２の対角線長さよりも大きな対角線長さを有する第１半導体素子Ｓ１と配線基板Ａとの熱伸縮の差に起因して発生する応力に対しても、第１半導体素子Ｓ１と配線基板Ａとの接続を強固に維持することが可能になる。 The solder resist layer 4 is attached to the upper surface of the insulating layer 3 and the lower surface of the insulating substrate 1. The solder resist layer 4 on the upper surface side has a first opening 4a and a second opening 4b that expose the first and second semiconductor element connection pads 11a and 11b. The solder resist layer 4 on the lower surface side has a third opening 4 c that exposes the external connection pad 7.
In addition, as shown in FIG. 1, it is preferable that the opening diameter of the 1st opening part 4a is larger than the opening diameter of the 2nd opening part 4b. Thus, by increasing the connection area between the electrode T1 of the first semiconductor element S1 and the first semiconductor element connection pad 11a, the bonding strength between the two can be improved. As a result, the first semiconductor element is also resistant to stress generated due to a difference in thermal expansion and contraction between the first semiconductor element S1 having a diagonal length larger than the diagonal length of the second semiconductor element S2 and the wiring board A. It is possible to firmly maintain the connection between S1 and the wiring board A.

ソルダーレジスト層４は、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成る樹脂ペーストまたはフィルムを絶縁基板１の上に塗布または貼着して熱硬化させることにより形成される。   The solder resist layer 4 is formed by, for example, applying or pasting a resin paste or film made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin on the insulating substrate 1 and thermosetting it. The

そして、第１および第２半導体素子Ｓ１、Ｓ２の電極Ｔ１、Ｔ２を、それぞれ対応する第１および第２半導体素子接続パッド１１ａ、１１ｂに半田を介して接続するとともに、外部接続パッド７を外部の電気回路基板の配線導体に半田を介して接続することにより、第１および第２半導体素子Ｓ１、Ｓ２が外部の電気回路基板に電気的に接続されて稼働する。   The electrodes T1 and T2 of the first and second semiconductor elements S1 and S2 are connected to the corresponding first and second semiconductor element connection pads 11a and 11b via solder, respectively, and the external connection pad 7 is connected to the outside. By connecting to the wiring conductor of the electric circuit board via solder, the first and second semiconductor elements S1, S2 are electrically connected to the external electric circuit board and operate.

ところで、本発明においては、上述したように、第１半導体素子Ｓ１の電極Ｔ１が接続される第１半導体素子接続パッド１１ａと一体的に形成された第１ビア導体１０ａは、第２半導体素子Ｓ２の電極Ｔ２が接続される第２半導体素子接続パッド１１ｂと一体的に形成された第２ビア導体１０ｂよりも大きな径を有している。したがって、第１ビア導体１０ａと下層導体６との接続面を大きくすることで第１ビア導体１０ａと下層導体６との接合強度を向上させることができる。これにより、第２半導体素子Ｓ２の対角線長さよりも大きな対角線長さを有する第１半導体素子Ｓ１と配線基板Ａとの熱伸縮の差に起因して発生する応力により第１ビア導体１０ａと下層導体６との間にクラックが発生することを抑制して、半導体素子Ｓ１を安定的に稼働させることが可能な配線基板Ａを提供することができる。なお、第１半導体素子Ｓ１の電極ピッチＰ１は第２半導体素子Ｓ２の電極ピッチＰ２よりも大きいことから、第１ビア導体１０ａの径を大きなものとしたとしても、第１ビア導体１０ａ同士の間に十分な絶縁間隔を設けることができる。さらに、第２半導体素子Ｓ２は対角線長さが短いことから、第２半導体素子Ｓ２と配線基板Ａとの熱伸縮差に起因する大きな応力が発生することはなく、したがって第２ビア導体１０ｂの径が小さいままであっても第２ビア導体１０ｂと下層導体６との間にクラックが発生することはない。   By the way, in the present invention, as described above, the first via conductor 10a formed integrally with the first semiconductor element connection pad 11a to which the electrode T1 of the first semiconductor element S1 is connected includes the second semiconductor element S2. This electrode has a larger diameter than the second via conductor 10b formed integrally with the second semiconductor element connection pad 11b to which the electrode T2 is connected. Therefore, it is possible to improve the bonding strength between the first via conductor 10a and the lower conductor 6 by increasing the connection surface between the first via conductor 10a and the lower conductor 6. As a result, the first via conductor 10a and the lower layer conductor are caused by the stress generated due to the difference in thermal expansion and contraction between the first semiconductor element S1 having a diagonal length larger than the diagonal length of the second semiconductor element S2 and the wiring board A. Thus, it is possible to provide the wiring board A capable of stably operating the semiconductor element S <b> 1 by suppressing the occurrence of cracks between the semiconductor element S <b> 6 and the semiconductor device S <b> 6. In addition, since the electrode pitch P1 of the first semiconductor element S1 is larger than the electrode pitch P2 of the second semiconductor element S2, even if the diameter of the first via conductor 10a is made large, the gap between the first via conductors 10a. A sufficient insulation interval can be provided. Further, since the diagonal length of the second semiconductor element S2 is short, a large stress due to the thermal expansion / contraction difference between the second semiconductor element S2 and the wiring board A does not occur, and therefore the diameter of the second via conductor 10b. However, cracks are not generated between the second via conductor 10b and the lower layer conductor 6 even if remains small.

なお、本発明は上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施形態の一例では、図１に示したように、絶縁基板１の上面には絶縁層３が一層だけ形成されているが、複数の絶縁層３を形成しても良い。また、絶縁基板１の下面には絶縁層３が形成されていないが、絶縁層３を単層あるいは複数層形成しても良い。   In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, as illustrated in FIG. 1, only one insulating layer 3 is formed on the upper surface of the insulating substrate 1, but a plurality of insulating layers 3 may be formed. Further, although the insulating layer 3 is not formed on the lower surface of the insulating substrate 1, the insulating layer 3 may be formed as a single layer or a plurality of layers.

また、例えば、上述の実施形態の一例では、図１に示したように、全ての第１ビア導体１０ａの径が第２ビア導体１０ｂの径よりも大きい例を示したが、図２に示す配線基板Ａ２のように、第１搭載部１ａにおいて、外周部に配設された第１半導体素子接続パッド１１ｖと一体的に形成された第１ビア導体１０ｖの径のみを、中央部に配設された第１半導体素子接続パッド１１ｗと一体的に形成された第１ビア導体１０ｗの径、および第２ビア導体１０ｂの径より大きくしても良い。このようにすることによって、第１半導体素子Ｓ１と配線基板Ａ２との熱伸縮の差に起因して発生する応力が特に集中する第１搭載部１ａの外周部において第１半導体素子接続パッド１１ｖと一体的に形成された第１ビア導体１０ｖと下層導体６との接合強度を向上させることができる。その結果、第１搭載部１ａの外周部の第１半導体素子接続パッド１１ｖに接続された第１ビア導体１０ｖと下層導体６との間にクラックが生じることを抑制できる。
なお、大きな対角線長さを有する第１搭載部１ａに配設された第１半導体素子接続パッド１１ｖおよび第１ビア導体１０ｖならびに第１半導体素子接続パッド１１ｗおよび第１ビア導体１０ｗをセミアディティブ法により形成する場合、セミアディティブ法における電解めっきを被着させると、電解めっきのための電流分布は第１搭載部１ａの外周部に集中して大きくなり、中央部では分散して小さくなる傾向にある。そのため、第１搭載部１ａの外周部では電解めっきの析出性が高いものの、中央部では低いものとなってしまう。しかしながら本例の配線基板Ａ２の場合、第１搭載部１ａの外周部に配設された第１ビア導体１０ｖのみの径を大きくし、中央部の第１ビア導体１０ｗの径を小さいままとしておくことで、セミアディティブ法における電解めっきを被着させる際に、電解めっきの析出性の低い中央部においても、第１ビア導体１０ｗを良好に析出させることができる。したがって、本例の配線基板Ａ２によれば、第１搭載部１ａの外周部のみならず、中央部においても電気的な接続信頼性に優れる配線基板Ａ２を提供することができる。 Further, for example, in the example of the above-described embodiment, as illustrated in FIG. 1, an example in which the diameters of all the first via conductors 10 a are larger than the diameters of the second via conductors 10 b is illustrated. Like the wiring board A2, in the first mounting portion 1a, only the diameter of the first via conductor 10v formed integrally with the first semiconductor element connection pad 11v disposed in the outer peripheral portion is disposed in the central portion. The diameter of the first via conductor 10w formed integrally with the first semiconductor element connection pad 11w and the diameter of the second via conductor 10b may be made larger. By doing so, the first semiconductor element connection pad 11v and the outer periphery of the first mounting part 1a where stress generated due to the difference in thermal expansion and contraction between the first semiconductor element S1 and the wiring board A2 is particularly concentrated. The joint strength between the integrally formed first via conductor 10v and the lower layer conductor 6 can be improved. As a result, it is possible to suppress the occurrence of cracks between the first via conductor 10v and the lower layer conductor 6 connected to the first semiconductor element connection pad 11v on the outer peripheral portion of the first mounting portion 1a.
The first semiconductor element connection pads 11v and the first via conductors 10v, the first semiconductor element connection pads 11w and the first via conductors 10w disposed on the first mounting portion 1a having a large diagonal length are formed by a semi-additive method. In the case of forming, when the electroplating in the semi-additive method is applied, the current distribution for the electroplating tends to be concentrated on the outer peripheral portion of the first mounting portion 1a, and tends to be dispersed and reduced in the central portion. . Therefore, although the precipitation of electrolytic plating is high at the outer peripheral portion of the first mounting portion 1a, it is low at the central portion. However, in the case of the wiring board A2 of this example, only the diameter of the first via conductor 10v disposed on the outer peripheral portion of the first mounting portion 1a is increased, and the diameter of the first via conductor 10w in the center is kept small. Thus, when depositing the electrolytic plating in the semi-additive method, the first via conductor 10w can be favorably deposited even in the central portion where the depositing ability of the electrolytic plating is low. Therefore, according to the wiring board A2 of this example, it is possible to provide the wiring board A2 having excellent electrical connection reliability not only in the outer peripheral portion of the first mounting portion 1a but also in the central portion.

さらに、図２に示した実施形態例では、第１搭載部１ａにおいて、外周部に配設された第１半導体素子接続パッド１１ｖと、中央部に配設された第１半導体素子接続パッド１１ｗとを露出する開口部４ａの開口径の大きさが同じ例を示したが、図３に示す配線基板Ａ３のように、第１半導体素子接続パッド１１ｖを露出する開口部１４ａの開口径を、第１半導体素子接続パッド１１ｗを露出する開口部４ａの開口径より大きくしてもよい。このようにすることによって、第１半導体素子Ｓ１と配線基板Ａ３との熱伸縮の差に起因して発生する応力が特に集中する第１搭載部１ａの外周部において、第１半導体素子Ｓ１の電極Ｔ１１と第１半導体素子接続パッド１１ｖとの接続面積を大きくすることで両者の接合強度が向上できる。その結果、第１半導体素子Ｓ１と配線基板Ａ３との熱伸縮の差に起因して発生する応力が特に集中する第１搭載部１ａの外周部においても、第１半導体素子Ｓ１と配線基板Ａ３との接続を強固に維持することが可能になる。   Further, in the embodiment shown in FIG. 2, in the first mounting portion 1a, the first semiconductor element connection pad 11v disposed in the outer peripheral portion, and the first semiconductor element connection pad 11w disposed in the central portion. In the example shown in FIG. 3, the opening diameter of the opening 14a exposing the first semiconductor element connection pad 11v is the same as that of the wiring board A3 shown in FIG. 1 The semiconductor element connection pad 11w may be larger than the opening diameter of the opening 4a that exposes the semiconductor element connection pad 11w. By doing in this way, in the outer peripheral part of the 1st mounting part 1a in which the stress which generate | occur | produces especially due to the difference of thermal expansion-contraction of 1st semiconductor element S1 and wiring board A3 concentrates, the electrode of 1st semiconductor element S1 By increasing the connection area between T11 and the first semiconductor element connection pad 11v, the bonding strength between the two can be improved. As a result, even in the outer peripheral portion of the first mounting portion 1a where stress generated due to the difference in thermal expansion and contraction between the first semiconductor element S1 and the wiring board A3 is particularly concentrated, the first semiconductor element S1 and the wiring board A3 It is possible to maintain a strong connection.

また、上述した実施形態例では、いずれも半導体素子接続パッドがソルダーレジスト層の開口部に露出している例を示したが、図４に示す配線基板Ａ４のように、第１半導体素子接続パッド１１ｖ、１１ｗおよび第２半導体素子接続パッド１１ｂの表面に、銅ポストＣ１、Ｃ２、Ｃ３を形成しておいてもよい。これらの銅ポストは、第１搭載部１ａの外周部に配設された第１半導体素子接続パッド１１ｖ表面に形成された銅ポストＣ１の径が、第１搭載部１ａの中央部に配設された第１半導体素子接続パッド１１ｗ表面に形成された銅ポストＣ２の径、および第２半導体素子接続パッド１１ｂ表面に形成された銅ポストＣ３の径よりも大きく形成されている。各銅ポストＣ１、Ｃ２、Ｃ３の径を同一に形成しても構わないが、上述のように形成することで、第１半導体素子Ｓ１と配線基板Ａ４との熱伸縮の差に起因して発生する応力が特に集中する第１搭載部１ａの外周部において、第１半導体素子Ｓ１の電極Ｔ１１と銅ポストＣ１との接続面積を大きくすることで両者の接合強度が向上できる。その結果、第１搭載部１ａの外周部においても、第１半導体素子Ｓ１と配線基板Ａ４との接続を強固に維持することが可能になる。
なお、銅ポストＣ１とＣ２の径を同ポストＣ３よりも大きな同一径としてもよい。
さらに、銅ポストＣ１およびＣ２のみを設けてもよい。この場合、銅ポストＣ１とＣ２の径を同一径としても良いし、銅ポストＣ１の径が銅ポストＣ２の径より大きくてもよい。
さらに、銅ポストＣ３のみを設けてもよい。
このような各銅ポストＣ１、Ｃ２、Ｃ３は、例えば次のように形成すればよい。まず、絶縁層３表面に各半導体素子接続パッドを露出する開口部を有するソルダーレジスト層４を上述した方法で被着させる。次に、ソルダーレジスト層４表面および開口部の内面に無電解めっきを被着させてから電解銅めっき層を析出させる。そして、各半導体素子接続パッドに対応する電解銅めっき層上にエッチングレジストを被着した後、エッチングレジストから露出する電解銅めっき層とその下側の無電解めっきとをエッチング除去することで銅ポストＣ１、Ｃ２、Ｃ３が形成される。
In the above-described embodiments, the semiconductor element connection pads are exposed in the openings of the solder resist layer. However, the first semiconductor element connection pads are similar to the wiring board A4 shown in FIG. Copper posts C1, C2, and C3 may be formed on the surfaces of 11v and 11w and the second semiconductor element connection pad 11b. In these copper posts, the diameter of the copper post C1 formed on the surface of the first semiconductor element connection pad 11v disposed on the outer peripheral portion of the first mounting portion 1a is disposed in the central portion of the first mounting portion 1a. The diameter of the copper post C2 formed on the surface of the first semiconductor element connection pad 11w and the diameter of the copper post C3 formed on the surface of the second semiconductor element connection pad 11b are formed. The copper posts C1, C2, and C3 may have the same diameter, but when formed as described above, the copper posts C1, C2, and C3 are generated due to the difference in thermal expansion and contraction between the first semiconductor element S1 and the wiring board A4. By increasing the connection area between the electrode T11 of the first semiconductor element S1 and the copper post C1 in the outer peripheral portion of the first mounting portion 1a where stress to be concentrated is particularly concentrated, the bonding strength between the two can be improved. As a result, the connection between the first semiconductor element S1 and the wiring board A4 can be firmly maintained even in the outer peripheral portion of the first mounting portion 1a.
The diameters of the copper posts C1 and C2 may be the same diameter larger than that of the post C3.
Further, only the copper posts C1 and C2 may be provided. In this case, the diameters of the copper posts C1 and C2 may be the same, or the diameter of the copper post C1 may be larger than the diameter of the copper post C2.
Furthermore, only the copper post C3 may be provided.
Such copper posts C1, C2, C3 may be formed as follows, for example. First, the solder resist layer 4 having an opening for exposing each semiconductor element connection pad on the surface of the insulating layer 3 is deposited by the method described above. Next, after electroless plating is applied to the surface of the solder resist layer 4 and the inner surface of the opening, an electrolytic copper plating layer is deposited. Then, after depositing an etching resist on the electrolytic copper plating layer corresponding to each semiconductor element connection pad, the copper post is removed by etching away the electrolytic copper plating layer exposed from the etching resist and the electroless plating therebelow. C1, C2, and C3 are formed.

１ａ 第１搭載部
１ｂ 第２搭載部
３ 絶縁層
６ 下層導体
８ａ 第１ビアホール
８ｂ 第２ビアホール
１０ａ、１０ｖ、１０ｗ 第１ビア導体
１０ｂ 第２ビア導体
１１ａ、１１ｖ、１１ｗ 第１半導体素子接続パッド
１１ｂ 第２半導体素子接続パッド
Ａ、Ａ２ 配線基板
Ｐ１ 第１電極ピッチ
Ｐ２ 第２電極ピッチ
Ｓ１ 第１半導体素子
Ｓ２ 第２半導体素子 DESCRIPTION OF SYMBOLS 1a 1st mounting part 1b 2nd mounting part 3 Insulating layer 6 Lower layer conductor 8a 1st via hole 8b 2nd via hole 10a, 10v, 10w 1st via conductor 10b 2nd via conductor 11a, 11v, 11w 1st semiconductor element connection pad 11b Second semiconductor element connection pads A and A2 Wiring board P1 First electrode pitch P2 Second electrode pitch S1 First semiconductor element S2 Second semiconductor element

Claims (8)

下面に下層導体を有する絶縁層と、該絶縁層上に形成されており第１電極ピッチを有する第１半導体素子を搭載する第１搭載部と、前記絶縁層上に形成されており前記第１電極ピッチより小さい第２電極ピッチを有するとともに前記第１半導体素子の対角線長さより小さい対角線長さを有する第２半導体素子を搭載する第２搭載部と、前記第１搭載部に前記第１電極ピッチと同ピッチで形成された第１半導体素子接続パッドと、前記第２搭載部に前記第２電極ピッチと同ピッチで形成された第２半導体素子接続パッドと、前記第１半導体素子接続パッド下の前記絶縁層に形成された第１ビアホールと、前記第２半導体素子接続パッド下の前記絶縁層に形成された第２ビアホールと、前記第１半導体素子接続パッドと一体的に形成されており前記第１ビアホールを充填して前記下層導体と電気的に接続された第１ビア導体と、前記第２半導体素子接続パッドと一体的に形成されており前記第２ビアホールを充填して前記下層導体と電気的に接続された第２ビア導体と、を具備して成る配線基板であって、前記第１ビア導体の径が、前記第２ビア導体の径よりも大きいことを特徴とする配線基板。   An insulating layer having a lower layer conductor on the lower surface, a first mounting portion for mounting a first semiconductor element formed on the insulating layer and having a first electrode pitch, and the first mounting portion formed on the insulating layer. A second mounting portion for mounting a second semiconductor element having a second electrode pitch smaller than the electrode pitch and having a diagonal length smaller than the diagonal length of the first semiconductor element; and the first electrode pitch on the first mounting portion. A first semiconductor element connection pad formed at the same pitch as the first semiconductor element connection pad, a second semiconductor element connection pad formed at the second mounting portion at the same pitch as the second electrode pitch, and a lower part of the first semiconductor element connection pad. The first via hole formed in the insulating layer, the second via hole formed in the insulating layer under the second semiconductor element connection pad, and the first semiconductor element connection pad are integrally formed. A first via conductor filling the first via hole and electrically connected to the lower conductor; and a second semiconductor element connection pad formed integrally with the second via hole to fill the lower conductor; A wiring board comprising a second via conductor electrically connected, wherein the diameter of the first via conductor is larger than the diameter of the second via conductor. 下面に下層導体を有する絶縁層と、該絶縁層上に形成されており第１電極ピッチを有する第１半導体素子を搭載する第１搭載部と、前記絶縁層上に形成されており前記第１電極ピッチより小さい第２電極ピッチを有するとともに前記第１半導体素子の対角線長さより小さい対角線長さを有する第２半導体素子を搭載する第２搭載部と、前記第１搭載部に前記第１電極ピッチと同ピッチで形成された第１半導体素子接続パッドと、前記第２搭載部に前記第２電極ピッチと同ピッチで形成された第２半導体素子接続パッドと、前記第１半導体素子接続パッド下の前記絶縁層に形成された第１ビアホールと、前記第２半導体素子接続パッド下の前記絶縁層に形成された第２ビアホールと、前記第１半導体素子接続パッドと一体的に形成されており前記第１ビアホールを充填して前記下層導体と電気的に接続された第１ビア導体と、前記第２半導体素子接続パッドと一体的に形成されており前記第２ビアホールを充填して前記下層導体と電気的に接続された第２ビア導体と、を具備して成る配線基板であって、前記第１搭載部において、外周部に配設された前記第１半導体素子接続パッドと一体的に形成された前記第１ビア導体の径が、中央部に配設された前記第１半導体素子接続パッドと一体的に形成された前記第１ビア導体の径、および前記第２ビア導体の径よりも大きいことを特徴とする配線基板。   An insulating layer having a lower layer conductor on the lower surface, a first mounting portion for mounting a first semiconductor element formed on the insulating layer and having a first electrode pitch, and the first mounting portion formed on the insulating layer. A second mounting portion for mounting a second semiconductor element having a second electrode pitch smaller than the electrode pitch and having a diagonal length smaller than the diagonal length of the first semiconductor element; and the first electrode pitch on the first mounting portion. A first semiconductor element connection pad formed at the same pitch as the first semiconductor element connection pad, a second semiconductor element connection pad formed at the second mounting portion at the same pitch as the second electrode pitch, and a lower part of the first semiconductor element connection pad. The first via hole formed in the insulating layer, the second via hole formed in the insulating layer under the second semiconductor element connection pad, and the first semiconductor element connection pad are integrally formed. A first via conductor filling the first via hole and electrically connected to the lower conductor; and a second semiconductor element connection pad formed integrally with the second via hole to fill the lower conductor; A wiring board comprising a second via conductor electrically connected to the first mounting portion, wherein the first mounting portion is formed integrally with the first semiconductor element connection pad disposed on the outer periphery. Further, the diameter of the first via conductor is larger than the diameter of the first via conductor and the diameter of the second via conductor formed integrally with the first semiconductor element connection pad disposed in the center portion. A wiring board characterized by that. 前記絶縁層の表面に、前記第１および第２半導体素子接続パッドを露出する開口部を有するソルダーレジスト層が被着されているとともに、前記第１半導体素子接続パッドを露出する開口部の径が、前記第２半導体素子接続パッドを露出する開口部の径よりも大きいことを特徴とする請求項１記載の配線基板。   A solder resist layer having an opening for exposing the first and second semiconductor element connection pads is deposited on the surface of the insulating layer, and the diameter of the opening for exposing the first semiconductor element connection pad is 2. The wiring board according to claim 1, wherein the diameter is larger than the diameter of the opening that exposes the second semiconductor element connection pad. 前記絶縁層の表面に、前記各半導体素子接続パッドを露出する開口部を有するソルダーレジスト層が被着されているとともに、前記第１搭載部の外周部の前記第１半導体素子接続パッドを露出する開口部の径が、前記第１搭載部の中央部の前記第１半導体素子接続パッドを露出する開口部の径、および前記第２半導体素子接続パッドを露出する開口部の径よりも大きいことを特徴とする請求項２記載の配線基板。   A solder resist layer having an opening for exposing the semiconductor element connection pads is deposited on the surface of the insulating layer, and the first semiconductor element connection pads on the outer periphery of the first mounting part are exposed. The diameter of the opening is larger than the diameter of the opening that exposes the first semiconductor element connection pad in the center of the first mounting part and the diameter of the opening that exposes the second semiconductor element connection pad. The wiring board according to claim 2, wherein 前記第１および第２半導体素子接続パッド上の少なくとも一方に、円柱状の銅ポストが形成されていることを特徴とする請求項１または２に記載の配線基板。   The wiring board according to claim 1, wherein a cylindrical copper post is formed on at least one of the first and second semiconductor element connection pads. 前記第１および第２半導体素子接続パッド上に円柱状の銅ポストが形成されているとともに、前記第１半導体素子接続パッド上の銅ポストの径が、前記第２半導体素子接続パッド上の銅ポストの径よりも大きいことを特徴とする請求項１に記載の配線基板。   A cylindrical copper post is formed on the first and second semiconductor element connection pads, and the diameter of the copper post on the first semiconductor element connection pad is equal to the copper post on the second semiconductor element connection pad. The wiring board according to claim 1, wherein the wiring board is larger than the diameter of the wiring board. 前記第１および第２半導体素子接続パッド上に円柱状の銅ポストが形成されているとともに、前記第１搭載部の外周部に配設された前記第１半導体素子接続パッド上の銅ポストの径が、前記第１搭載部の中央部に配設された前記第１半導体素子接続パッド上の銅ポストの径、および前記第２半導体素子接続パッド上の銅ポストの径よりも大きいことを特徴とする請求項２に記載の配線基板。   A cylindrical copper post is formed on the first and second semiconductor element connection pads, and the diameter of the copper post on the first semiconductor element connection pad disposed on the outer periphery of the first mounting portion. Is larger than the diameter of the copper post on the first semiconductor element connection pad and the diameter of the copper post on the second semiconductor element connection pad disposed in the center of the first mounting part. The wiring board according to claim 2. 前記第１半導体素子接続パッド上に円柱状の銅ポストが形成されているとともに、前記第１搭載部の外周部に配設された前記第１半導体素子接続パッド上の銅ポストの径が、前記第１搭載部の中央部に配設された前記第１半導体素子接続パッド上の銅ポストの径よりも大きいことを特徴とする請求項２に記載の配線基板。   A cylindrical copper post is formed on the first semiconductor element connection pad, and the diameter of the copper post on the first semiconductor element connection pad disposed on the outer periphery of the first mounting portion is The wiring board according to claim 2, wherein the wiring board is larger than a diameter of a copper post on the first semiconductor element connection pad disposed in a central portion of the first mounting portion.
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