JP5978587B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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JP5978587B2
JP5978587B2 JP2011225874A JP2011225874A JP5978587B2 JP 5978587 B2 JP5978587 B2 JP 5978587B2 JP 2011225874 A JP2011225874 A JP 2011225874A JP 2011225874 A JP2011225874 A JP 2011225874A JP 5978587 B2 JP5978587 B2 JP 5978587B2
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plating film
copper
terminal
palladium
wire bonding
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JP2013089630A (en
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芳則 江尻
芳則 江尻
長谷川　清
清 長谷川
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Resonac Corp
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/4557—Plural coating layers
    • H01L2224/45572—Two-layer stack coating
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
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    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]

Description

本発明は、半導体パッケージ及びその製造方法に関する。   The present invention relates to a semiconductor package and a manufacturing method thereof.

近年、パソコン、携帯電話、無線基地局、光通信装置、サーバ及びルータ等の電子機器において、大小問わず、機器の小型化、軽量化、高性能化及び高機能化が進んでいる。また、ＣＰＵ、ＤＳＰ及び各種メモリ等のＬＳＩの高速化並びに高機能化とともに、ＳｏＣ（Ｓｙｓｔｅｍ ｏｎ ａ ｃｈｉｐ）やＳｉＰ（Ｓｙｓｔｅｍ Ｉｎ Ｐａｃｋａｇｅ）等の高密度実装技術の開発も行われている。   In recent years, electronic devices such as personal computers, mobile phones, wireless base stations, optical communication devices, servers, and routers are becoming smaller, lighter, higher in performance, and higher in functionality regardless of size. In addition to increasing the speed and functionality of LSIs such as CPUs, DSPs, and various memories, high-density mounting technologies such as SoC (System on a chip) and SiP (System In Package) are also being developed.

このため、半導体チップ搭載用基板やマザーボードには、ビルドアップ方式の多層配線基板が使用されるようになっている。また、パッケージの多ピン狭ピッチ化といった実装技術の進歩により、半導体チップ搭載用基板は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）からＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）／ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ
Ｐａｃｋａｇｅ）実装へと進化している。 For this reason, build-up type multilayer wiring boards are used for semiconductor chip mounting boards and motherboards. Further, due to advances in mounting technology such as a narrow multi-pin pitch of a package, a semiconductor chip mounting substrate has been changed from QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size).
Package) has evolved.

半導体チップ搭載用基板と半導体チップとの接続には、例えば、金ワイヤなどのボンディングワイヤが用いられる。金ワイヤの素材は、これまで高純度４Ｎ系（純度＞９９．９９質量％）の金が主に用いられている。しかし、金は高価であるため、材料費が安価である他種金属のボンディングワイヤが所望されている。近年、金ワイヤより安価な銅ワイヤが急速に使用され始めている。銅ワイヤは金ワイヤと比較して電気特性や機械的特性に優れており、種々の銅ワイヤが販売されている（例えば、下記非特許文献１）。   For example, a bonding wire such as a gold wire is used to connect the semiconductor chip mounting substrate and the semiconductor chip. As a material for the gold wire, gold of high purity 4N type (purity> 99.99 mass%) has been mainly used so far. However, since gold is expensive, a bonding wire of another kind of metal having a low material cost is desired. In recent years, copper wires that are cheaper than gold wires have begun to be used rapidly. Copper wires are superior in electrical properties and mechanical properties compared to gold wires, and various copper wires are sold (for example, Non-Patent Document 1 below).

半導体チップ搭載用基板は、通常、半導体チップ又は配線板に接続するための接続端子を有している。これらの接続端子には、金ワイヤ又ははんだとの良好な金属接合を確保するために、金めっきが施されることが多い。   A semiconductor chip mounting substrate usually has connection terminals for connection to a semiconductor chip or a wiring board. These connection terminals are often plated with gold in order to ensure good metal bonding with gold wires or solder.

銅ワイヤによるボンディングに関し、銅ワイヤと接続するための端子部分の金めっき皮膜の厚みは、金ワイヤと接続する場合と比較して厚くする必要があることが知られている（例えば、下記非特許文２）。これは、金ワイヤ−金めっき皮膜（端子）では金・金の同金属接合であるのに対し、銅ワイヤ−金めっき皮膜（端子）では銅・金の異種金属接合になることに起因する。   Regarding bonding with copper wire, it is known that the thickness of the gold plating film of the terminal portion for connecting to the copper wire needs to be thicker than that for connecting to the gold wire (for example, the following non-patent patent) Sentence 2). This is because the gold wire-gold plating film (terminal) is the same metal joint of gold and gold, whereas the copper wire-gold plating film (terminal) is a different metal joint of copper and gold.

しかし、近年の金価格の高騰に対し、金ワイヤを銅ワイヤにすることでワイヤのコストを低減することができても、半導体チップ搭載用基板の接続端子の金めっき皮膜の厚みを厚くしなければならず、半導体チップ搭載用基板のコストが高くなる課題がある。   However, in response to the recent rise in gold prices, even if the cost of the wires can be reduced by using gold wires as copper wires, the thickness of the gold plating film on the connection terminals of the semiconductor chip mounting board must be increased. In other words, there is a problem that the cost of the semiconductor chip mounting substrate becomes high.

一方、接続端子に金めっきを施す方法としては、電解金めっきが広く適用されてきた。しかし、最近では、半導体チップ搭載用基板の小型化による配線の高密度化に伴って、接続端子の表面に電解金めっきを施すための配線を確保することが困難になりつつある。そこで、接続端子への金めっき方法として、電解めっきをするためのリード線が不要である無電解金めっき（置換金めっきや還元金めっき）のプロセスが注目され始めている。例えば、端子部分の銅箔表面に、無電解ニッケルめっき皮膜／無電解金めっき皮膜を形成することが知られている（例えば、下記非特許文献３）。   On the other hand, electrolytic gold plating has been widely applied as a method of applying gold plating to connection terminals. However, recently, as the wiring density is increased by downsizing the semiconductor chip mounting substrate, it is becoming difficult to secure wiring for performing electrolytic gold plating on the surface of the connection terminal. Therefore, as a method of gold plating on the connection terminals, an electroless gold plating (substitution gold plating or reduction gold plating) process that does not require a lead wire for electrolytic plating has begun to attract attention. For example, it is known to form an electroless nickel plating film / electroless gold plating film on the copper foil surface of the terminal portion (for example, Non-Patent Document 3 below).

しかしながら、配線に無電解ニッケルめっきを行うと、「ブリッジ」と呼ばれる、配線間に無電解ニッケルめっき皮膜が析出する現象が発生し、これにより短絡不良が引き起こされる場合がある。このブリッジを抑制するためには、例えば、特許文献１、２に示すようなブリッジを抑制するための前処理液及び前処理方法が提案されている。また、特許文献３に示すように、ブリッジを抑制するための無電解めっき用触媒液も提案されている。   However, when the electroless nickel plating is performed on the wiring, a phenomenon called “bridge” occurs in which an electroless nickel plating film is deposited between the wirings, which may cause a short circuit failure. In order to suppress this bridge, for example, a pretreatment liquid and a pretreatment method for suppressing a bridge as shown in Patent Documents 1 and 2 have been proposed. Moreover, as shown in Patent Document 3, an electroless plating catalyst solution for suppressing bridging has also been proposed.

特開平９−２４１８５３号公報Japanese Patent Laid-Open No. 9-241853 特許第３３８７５０７号Japanese Patent No. 3387507 特開平１１−１２４６８０号公報Japanese Patent Laid-Open No. 11-124680

“使用実績の豊富なＴＡＮＡＫＡのＣｕボンディングワイヤ”、［on line］、田中電子工業株式会社、［２０１１年３月２５日検索］、インターネット＜URL: http://www.tanaka-bondingwire.com/images/pdf/gide_Cu.PDF＞“TANAKA's Cu bonding wire with abundant use results”, [on line], Tanaka Electronics Co., Ltd. [searched on March 25, 2011], Internet <URL: http://www.tanaka-bondingwire.com/ images / pdf / gide_Cu.PDF> 社団法人エレクトロニクス実装学会「第２５回エレクトロニクス実装学会春季講演大会」（２０１１年 ３６８〜３７２頁）Japan Institute of Electronics Packaging "25th Electronics Packaging Society Spring Lecture Meeting" (2011 pages 368-372) 社団法人プリント回路学会誌「サーキットテクノロジー」（１９９３年 Ｖｏｌ．８ Ｎｏ．５ ３６８〜３７２頁）Journal of Printed Circuit Society “Circuit Technology” (1993 Vol. 8 No. 5 pages 368-372)

しかし、上述した特許文献１〜３に記載の前処理液や前処理方法、無電解めっき用触媒液等のブリッジを低減する手法を適用しても、微細配線とした場合には導体間の基材上に無電解ニッケルめっきが析出し易いため、充分な効果が得られないことが判明した。   However, even if the pretreatment liquid and the pretreatment method described in Patent Documents 1 to 3 described above and the technique of reducing the bridge such as the electroless plating catalyst liquid are applied, in the case of fine wiring, It has been found that the electroless nickel plating tends to be deposited on the material, so that a sufficient effect cannot be obtained.

そこで、本発明者らは、ニッケルめっきを適用しないめっき皮膜が形成されたワイヤボンディング端子に対する銅ワイヤのボンディング性について検討を行ったところ、充分なワイヤプル強度が得られない場合があることを見出した。   Therefore, the present inventors have examined the bondability of a copper wire to a wire bonding terminal on which a plating film to which nickel plating is not applied is formed, and found that sufficient wire pull strength may not be obtained. .

本発明は、上記事情に鑑みてなされたものであり、微細配線に充分対応することができ、しかも銅ワイヤによる接続で充分なワイヤボンディング接続信頼性を有する半導体パッケージ及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a semiconductor package that can sufficiently cope with fine wiring, and has sufficient wire bonding connection reliability by connection with a copper wire, and a method for manufacturing the same. With the goal.

本発明の半導体パッケージは、端子形状の銅の表面にめっき皮膜が形成されたワイヤボンディング端子を有する半導体チップ搭載用基板と、ワイヤボンディング端子に接合された銅ワイヤで電気的に接続された半導体チップと、を備え、上記めっき皮膜が、銀めっき皮膜、パラジウムめっき皮膜、金めっき皮膜、又は、パラジウムめっき皮膜と金めっき皮膜との２層めっき皮膜であり、上記ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有する。   The semiconductor package of the present invention includes a semiconductor chip mounting substrate having a wire bonding terminal in which a plating film is formed on the surface of a terminal-shaped copper, and a semiconductor chip electrically connected by a copper wire bonded to the wire bonding terminal And the plating film is a silver plating film, a palladium plating film, a gold plating film, or a two-layer plating film of a palladium plating film and a gold plating film, and the wire bonding terminal is formed by a plating film. And a portion where the terminal-shaped copper and the copper wire are directly joined.

本発明の半導体パッケージは、上記構成を有することにより、微細配線に充分対応することができ、しかも銅ワイヤによる接続で充分なワイヤボンディング接続信頼性を有することができる。   Since the semiconductor package of the present invention has the above-described configuration, it can sufficiently cope with fine wiring and can have sufficient wire bonding connection reliability by connection with a copper wire.

本発明の半導体パッケージは、端子形状の銅と銅ワイヤとが直接接合されている箇所の表面の十点平均粗さが０．１５〜１．０μｍの範囲であることが好ましい。   In the semiconductor package of the present invention, the 10-point average roughness of the surface where the terminal-shaped copper and the copper wire are directly bonded is preferably in the range of 0.15 to 1.0 μm.

また、上記めっき皮膜が、下記（１）〜（４）のいずれかのめっき皮膜であることが好ましい。
（１）厚さが０．０３〜０．４μｍの銀めっき皮膜
（２）厚さが０．００５〜０．３５μｍのパラジウムめっき皮膜
（３）厚さが０．０３〜０．４μｍの金めっき皮膜
（４）厚さが０．００３〜０．２μｍのパラジウムめっき皮膜及び厚さが０．０３〜０．２μｍの金めっき皮膜の２層めっき皮膜 Moreover, it is preferable that the said plating film is a plating film in any one of following (1)-(4).
(1) Silver plating film having a thickness of 0.03 to 0.4 μm (2) Palladium plating film having a thickness of 0.005 to 0.35 μm (3) Gold plating having a thickness of 0.03 to 0.4 μm Film (4) Two-layer plating film of palladium plating film having a thickness of 0.003 to 0.2 μm and gold plating film having a thickness of 0.03 to 0.2 μm

更に、上記めっき皮膜の純度が９９％以上であることが好ましい。   Furthermore, the purity of the plating film is preferably 99% or more.

また、上記めっき皮膜が、下記（２−１）〜（２−４）のいずれかのパラジウムめっき皮膜であってもよい。
（２−１）厚さが０．００５〜０．３５μｍであり、純度が９９％以上のパラジウムめっき皮膜
（２−２）厚さが０．００５〜０．２５μｍであり、純度が９８％以上のパラジウムめっき皮膜
（２−３）厚さが０．００５〜０．１５μｍであり、純度が９７％以上のパラジウムめっき皮膜
（２−４）厚さが０．００５〜０．１２μｍであり、純度が９４％以上のパラジウムめっき皮膜 Moreover, the palladium plating film in any one of following (2-1)-(2-4) may be sufficient as the said plating film.
(2-1) A palladium plating film having a thickness of 0.005 to 0.35 μm and a purity of 99% or more (2-2) A thickness of 0.005 to 0.25 μm and a purity of 98% or more The palladium plating film (2-3) has a thickness of 0.005 to 0.15 μm, and the purity of the palladium plating film (2-4) having a purity of 97% or more is 0.005 to 0.12 μm. Palladium plating film with 94% or more

本発明の半導体パッケージの製造方法は、基板、及び該基板上に設けられ、端子形状の銅の表面にめっき皮膜が形成されたワイヤボンディング端子を備える半導体チップ搭載用基板と、ワイヤボンディング端子に接合された銅ワイヤで電気的に接続された半導体チップと、を備える半導体パッケージの製造方法であって、めっき皮膜が、銀めっき皮膜、パラジウムめっき皮膜、金めっき皮膜、又は、パラジウムめっき皮膜と金めっき皮膜との２層めっき皮膜であり、ワイヤボンディング端子に銅ワイヤを接合して、ワイヤボンディング端子の一部に端子形状の銅と銅ワイヤとが直接接合する箇所を設ける工程を備える。   The semiconductor package manufacturing method of the present invention includes a substrate, a semiconductor chip mounting substrate provided on the substrate and provided with a wire bonding terminal having a plating film formed on the surface of the terminal-shaped copper, and the wire bonding terminal. A semiconductor package comprising: a semiconductor chip electrically connected with a copper wire, wherein the plating film is a silver plating film, a palladium plating film, a gold plating film, or a palladium plating film and a gold plating It is a two-layer plating film with a film, and includes a step of bonding a copper wire to a wire bonding terminal and providing a portion where a terminal-shaped copper and a copper wire are directly bonded to a part of the wire bonding terminal.

本発明の半導体パッケージの製造方法によれば、微細配線に充分対応することができ、しかも銅ワイヤによる接続で充分なワイヤボンディング接続信頼性を有する半導体パッケージを得ることができる。   According to the method for manufacturing a semiconductor package of the present invention, it is possible to obtain a semiconductor package that can sufficiently cope with fine wiring and has sufficient wire bonding connection reliability by connection with a copper wire.

本発明の半導体パッケージの製造方法においては、先端面がマット加工されたキャピラリーにより銅ワイヤをワイヤボンディング端子に接合することが好ましい。これにより、銅の表面に上記めっき皮膜が形成されたワイヤボンディング端子に、端子形状の銅と銅ワイヤとが直接接合する箇所を設けることがより確実にできる。   In the method for manufacturing a semiconductor package of the present invention, it is preferable to bond a copper wire to a wire bonding terminal with a capillary whose tip surface is matted. Thereby, the location where the terminal-shaped copper and the copper wire are directly joined can be more reliably provided on the wire bonding terminal in which the plating film is formed on the copper surface.

また、微細配線の形成性を充分確保しつつ、充分なワイヤプル強度を得る観点から、上記めっき皮膜が、下記（１）〜（４）のいずれかのめっき皮膜であることが好ましい。
（１）厚さが０．０３〜０．４μｍの銀めっき皮膜
（２）厚さが０．００５〜０．３５μｍのパラジウムめっき皮膜
（３）厚さが０．０３〜０．４μｍの金めっき皮膜
（４）厚さが０．００３〜０．２μｍのパラジウムめっき皮膜と厚さが０．０３〜０．２μｍの金めっき皮膜との２層めっき皮膜 Moreover, it is preferable that the said plating film is a plating film in any one of following (1)-(4) from a viewpoint of obtaining sufficient wire pull intensity | strength, ensuring the formation property of fine wiring sufficiently.
(1) Silver plating film having a thickness of 0.03 to 0.4 μm (2) Palladium plating film having a thickness of 0.005 to 0.35 μm (3) Gold plating having a thickness of 0.03 to 0.4 μm Film (4) Two-layer plating film of a palladium plating film having a thickness of 0.003 to 0.2 μm and a gold plating film having a thickness of 0.03 to 0.2 μm

ワイヤボンディングを行なった際に、めっき皮膜の純度が高いほど変形しやすいため、銅ワイヤの銅とワイヤボンディング端子の銅との接合が起こりやすくなる観点から、上記めっき皮膜の純度が９９％以上であることが好ましい。   When wire bonding is performed, the higher the purity of the plating film, the easier it is to deform. From the viewpoint of easy joining of copper of the copper wire and copper of the wire bonding terminal, the purity of the plating film is 99% or more. Preferably there is.

ワイヤボンディングを行なった際に、銅ワイヤの銅とワイヤボンディング端子の銅との接合が起こりやすくなる観点から、上記めっき皮膜が、下記（２−１）〜（２−４）のいずれかのパラジウムめっき皮膜であることが好ましい。
（２−１）厚さが０．００５〜０．３５μｍであり、純度が９９％以上のパラジウムめっき皮膜
（２−２）厚さが０．００５〜０．２５μｍであり、純度が９８％以上のパラジウムめっき皮膜
（２−３）厚さが０．００５〜０．１５μｍであり、純度が９７％以上のパラジウムめっき皮膜
（２−４）厚さが０．００５〜０．１２μｍであり、純度が９４％以上のパラジウムめっき皮膜 From the viewpoint of facilitating the bonding of copper of the copper wire and copper of the wire bonding terminal when wire bonding is performed, the plating film is any one of the following palladium (2-1) to (2-4) A plating film is preferred.
(2-1) A palladium plating film having a thickness of 0.005 to 0.35 μm and a purity of 99% or more (2-2) A thickness of 0.005 to 0.25 μm and a purity of 98% or more The palladium plating film (2-3) has a thickness of 0.005 to 0.15 μm, and the purity of the palladium plating film (2-4) having a purity of 97% or more is 0.005 to 0.12 μm. Palladium plating film with 94% or more

本発明によれば、微細配線に充分対応することができ、しかも銅ワイヤによる接続で充分なワイヤボンディング接続信頼性を有する半導体パッケージ及びその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor package which can fully respond to fine wiring, and has sufficient wire bonding connection reliability by the connection by a copper wire, and its manufacturing method can be provided.

実施例１における銅ワイヤが接合されたワイヤボンディング端子の表面のＳＥＭ観察結果を示す図である。It is a figure which shows the SEM observation result of the surface of the wire bonding terminal in which the copper wire in Example 1 was joined. 比較例２３における銅ワイヤが接合されたワイヤボンディング端子の表面のＳＥＭ観察結果を示す図である。It is a figure which shows the SEM observation result of the surface of the wire bonding terminal in which the copper wire in the comparative example 23 was joined.

本実施形態の半導体パッケージは、端子形状の銅の表面にめっき皮膜が形成されたワイヤボンディング端子を有する半導体チップ搭載用基板と、ワイヤボンディング端子に接合された銅ワイヤで電気的に接続された半導体チップと、を備え、上記めっき皮膜が、銀めっき皮膜、パラジウムめっき皮膜、金めっき皮膜、又は、パラジウムめっき皮膜と金めっき皮膜との２層めっき皮膜であり（以下、これらをまとめて本発明に係るめっき皮膜という場合もある。）、上記ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有する。   The semiconductor package of this embodiment includes a semiconductor chip mounting substrate having a wire bonding terminal in which a plating film is formed on the surface of a terminal-shaped copper, and a semiconductor electrically connected by a copper wire bonded to the wire bonding terminal. The plating film is a silver plating film, a palladium plating film, a gold plating film, or a two-layer plating film of a palladium plating film and a gold plating film (hereinafter, these are collectively referred to in the present invention). The said wire bonding terminal has the location where the plating membrane was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

本実施形態の半導体パッケージにおいては、ワイヤボンディング端子の一部に、端子形状の銅と銅ワイヤの銅とが直接接合されて銅・銅結合が生じている。ここで意味する銅・銅結合とは、銅ワイヤボンディングを行うことで、銀めっき皮膜、パラジウムめっき皮膜、金めっき皮膜、又は、パラジウムめっき皮膜と金めっき皮膜との２層めっき皮膜が押し退けられて、これらのめっき皮膜の下部にあった端子形状の銅と銅ワイヤの銅とが直接接合されている状態のことである。   In the semiconductor package of this embodiment, the copper of the terminal shape and the copper of the copper wire are directly joined to a part of the wire bonding terminal to form a copper-copper bond. The copper-copper bond as used herein means that by performing copper wire bonding, the silver plating film, the palladium plating film, the gold plating film, or the two-layer plating film of the palladium plating film and the gold plating film is pushed away. This is a state in which the copper in the terminal shape and the copper of the copper wire that are located under these plating films are directly joined.

上記の本実施形態の半導体パッケージを製造する方法は、端子形状の銅の表面に本発明に係るめっき皮膜が形成されたワイヤボンディング端子に銅ワイヤを接合して、ワイヤボンディング端子の一部に端子形状の銅と銅ワイヤとが直接接合する箇所を設ける工程を備える。   In the method of manufacturing the semiconductor package of the present embodiment, the copper wire is bonded to the wire bonding terminal in which the plating film according to the present invention is formed on the surface of the terminal-shaped copper, and the terminal is formed on a part of the wire bonding terminal. A step of providing a location where the shaped copper and the copper wire are directly joined.

上記本発明に係るめっき皮膜は、電解めっき又は無電解めっきにより形成することが可能であるが、皮膜の厚みの均一性の点から無電解めっき皮膜であることが好ましい。皮膜が厚い部分があると、銅ワイヤボンディングを行っても皮膜を押し退けることができずに、銅・銅結合が得られないワイヤボンディング端子が生じやすくなるため、充分なワイヤボンディング性が得られない場合がある。   The plating film according to the present invention can be formed by electrolytic plating or electroless plating, but is preferably an electroless plating film from the viewpoint of uniformity of the film thickness. If there is a thick part of the film, even if copper wire bonding is performed, the film cannot be pushed away, and a wire bonding terminal that cannot obtain a copper-copper bond is likely to occur, so that sufficient wire bonding properties cannot be obtained. There is a case.

上記本発明に係るめっき皮膜は、置換型の無電解めっきにより形成されていることが好ましい。置換型の無電解めっきであれば端子形状の銅における置換反応だけであるためにブリッジが発生を防止することができる。微細配線を形成する場合、ブリッジの発生を抑制する観点から、還元型の無電解めっきを追加して行わないことが好ましい。   The plating film according to the present invention is preferably formed by substitutional electroless plating. Substitution-type electroless plating can prevent the occurrence of bridging because it is only a substitution reaction in terminal-shaped copper. When forming fine wiring, it is preferable not to perform additional reduction-type electroless plating from the viewpoint of suppressing the occurrence of bridges.

上記本発明に係るめっき皮膜は、純度が９９％以上であることが好ましく、９９．９％であることがより好ましい。   The plating film according to the present invention preferably has a purity of 99% or more, and more preferably 99.9%.

めっき皮膜の純度が９９％以上であれば、めっき皮膜の硬度を下げることができるため、銅ワイヤボンディングを行った際に皮膜が変形しやすく、皮膜の下部の銅と銅ワイヤの銅との直接接合が起こりやすくなる。端子形状の銅と銅ワイヤとの直接接合を形成させる観点から、上記本発明に係るめっき皮膜は、変形が最も起こりやすい純度１００％に近いことが最も好ましい。   If the purity of the plating film is 99% or more, the hardness of the plating film can be lowered, so that the film easily deforms when copper wire bonding is performed, and the copper below the film and the copper of the copper wire directly Joining is likely to occur. From the viewpoint of forming a direct bond between terminal-shaped copper and copper wire, the plating film according to the present invention is most preferably close to a purity of 100% at which deformation is most likely to occur.

上記本発明に係るめっき皮膜について更に詳細に説明する。   The plating film according to the present invention will be described in more detail.

銀めっき皮膜は、厚みが０．０３〜０．４μｍであると好ましく、０．０５〜０．３μｍであるとより好ましく、０．１〜０．２μｍであると更に好ましい。   The silver plating film preferably has a thickness of 0.03 to 0.4 μm, more preferably 0.05 to 0.3 μm, and still more preferably 0.1 to 0.2 μm.

銀めっき皮膜の厚みが０．４μｍよりも厚く、０．６μｍ以下の範囲では、銅ワイヤボンディングを行っても皮膜を押し退けることができずに、銅・銅結合を有していないワイヤボンディング端子が生じる場合がある。特に、銅ワイヤボンディング後に、端子形状の銅／０．０５〜０．２μｍの銀めっき皮膜／銅ワイヤの３層構造となり、高温の環境下で０．０５〜０．２μｍの銀めっき皮膜が銅と合金化されて銀・銅合金を形成し、脆弱層が形成されてボンディング部の接続信頼性が低下する問題があり、好ましくない。銀めっき皮膜の厚みを０．４μｍ以下とすることで、ワイヤボンディング性を向上させることができる。   When the thickness of the silver plating film is greater than 0.4 μm and within the range of 0.6 μm or less, even if copper wire bonding is performed, the film cannot be pushed away, and a wire bonding terminal having no copper-copper bond is present. May occur. In particular, after copper wire bonding, it becomes a three-layer structure of terminal-shaped copper / 0.05-0.2 μm silver plating film / copper wire, and 0.05-0.2 μm silver plating film is copper in a high temperature environment. And a silver / copper alloy is formed, and a brittle layer is formed, resulting in a decrease in connection reliability of the bonding portion, which is not preferable. Wire bonding property can be improved by making the thickness of a silver plating film into 0.4 micrometer or less.

銀めっき皮膜の厚みが０．６μｍを越えると、銀めっき皮膜と銅ワイヤとの良好な接続が得られるが、微細配線に用いた場合は、ブリッジが発生しやすくなるとともに、高温高湿の環境下でマイグレーションが発生しやすくなる。なお、この場合も、銅・銅結合を得られないワイヤボンディング端子が生じてしまう。   If the thickness of the silver plating film exceeds 0.6 μm, a good connection between the silver plating film and the copper wire can be obtained. However, when used for fine wiring, bridges are likely to occur and the environment is hot and humid. Migration tends to occur below. In this case as well, a wire bonding terminal that cannot obtain a copper-copper bond is generated.

一方、厚みが０．０３μｍ以上であると、銀めっき皮膜が充分に析出し、例えば、ワイヤボンディング前に行う１５０℃の高温処理を考慮した場合であっても、銅が銀めっき表面に拡散しにくくなるため、充分なワイヤボンディング接続信頼性が得られやすい。   On the other hand, when the thickness is 0.03 μm or more, the silver plating film is sufficiently deposited, for example, copper is diffused to the surface of the silver plating even when considering a high temperature treatment of 150 ° C. performed before wire bonding. Therefore, sufficient wire bonding connection reliability is easily obtained.

本実施形態で用いる無電解銀めっき液としては、例えば、可溶性銀塩、錯化剤、ｐＨ調整剤、界面活性剤を含んだ溶液を使用することができる。   As the electroless silver plating solution used in the present embodiment, for example, a solution containing a soluble silver salt, a complexing agent, a pH adjusting agent, and a surfactant can be used.

可溶性銀塩としては、硫酸銀、亜硫酸銀、炭酸銀、酢酸銀、乳酸銀、スルホコハク酸銀、硝酸銀、有機スルホン酸銀、ホウフッ化銀、クエン酸銀、酒石酸銀、グルコン酸銀、スルファミン酸銀、シュウ酸銀、酸化銀などの可溶性塩が使用でき、また、本来は難溶性であるが、スルフィド系化合物などの作用によりある程度の溶解性を確保できる塩化銀なども使用できる。銀塩の好ましい具体例としては、メタンスルホン酸銀、エタンスルホン酸銀、酢酸銀、乳酸銀、クエン酸銀などが挙げられる。メッキ浴に対する当該可溶性銀塩の金属塩換算の含有量は、０.００１〜２００ｇ／Ｌが好ましく、０．１〜３０ｇ／Ｌがより好ましく、０．５〜１０ｇ／Ｌが更により好ましい。   Soluble silver salts include silver sulfate, silver sulfite, silver carbonate, silver acetate, silver lactate, silver sulfosuccinate, silver nitrate, silver organic sulfonate, silver borofluoride, silver citrate, silver tartrate, silver gluconate, silver sulfamate Soluble salts such as silver oxalate and silver oxide can be used, and silver chloride which is originally poorly soluble but can ensure a certain degree of solubility by the action of sulfide compounds and the like can also be used. Preferable specific examples of the silver salt include silver methanesulfonate, silver ethanesulfonate, silver acetate, silver lactate, and silver citrate. 0.001-200 g / L is preferable, as for content of the said soluble silver salt with respect to a plating bath as metal salt, 0.1-30 g / L is more preferable, 0.5-10 g / L is still more preferable.

無電解銀めっき液に用いる錯化剤としては、チオ尿素類、スルフィド類、メルカプタン類などの含イオウ化合物、グリシン、ニトリロ三酢酸、Ｎ−ヒドロキシエチルエチレンジアミン三酢酸、エチレンジアミン四酢酸、ジエチレントリアミン五酢酸等のアミノカルボン酸化合物、乳酸、クエン酸、サリチル酸等の水酸基を有するヒドロキシカルボン酸化合物、１，２，３−トリアゾール、１，２，４−トリアゾール、３−アミノ−１，２，４−トリアゾール等のトリアゾール化合物、ニトロフェノール、ジニトロフェノール、トリニトロフェノール、ニトロレゾルシノール等のフェノール類、ニトロベンジルアルコール、ニトロフェノキシエタノール等のアルコール類、ニトロアニリン、ニトロナフチルアミン等のアミン類、ニトロベンゼンスルホン酸、ニトロフェノールスルホン酸、ニトロナフタリンスルホン酸等のスルホン酸類及びこれらのスルホン塩、ニトロ安息香酸、クロルニトロ安息香酸、アミノニトロ安息香酸、ニトロフタル酸、ニトロイソフタル酸、ニトロテレフタル酸、ニトロサリチル酸、ジニトロサリチル酸等のカルボン酸類及びこれらのカルボン酸塩等を適用できるが、添加する錯化剤は特に限定されない。これらの錯化剤は各々を単用又は併用できる。メッキ浴に対する錯化剤の添加量は、０.０００１〜５モル／Ｌが好ましく、０.０３〜２モル／Ｌがより好ましい。   Complexing agents used in electroless silver plating solutions include sulfur-containing compounds such as thioureas, sulfides, mercaptans, glycine, nitrilotriacetic acid, N-hydroxyethylethylenediaminetriacetic acid, ethylenediaminetetraacetic acid, diethylenetriaminepentaacetic acid, etc. Aminocarboxylic acid compounds, hydroxycarboxylic acid compounds having a hydroxyl group such as lactic acid, citric acid, salicylic acid, 1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, etc. Triazole compounds, phenols such as nitrophenol, dinitrophenol, trinitrophenol and nitroresorcinol, alcohols such as nitrobenzyl alcohol and nitrophenoxyethanol, amines such as nitroaniline and nitronaphthylamine, nitrobenzene Sulfonic acids such as sulfonic acid, nitrophenol sulfonic acid, nitronaphthalene sulfonic acid and their sulfonates, nitrobenzoic acid, chloronitrobenzoic acid, aminonitrobenzoic acid, nitrophthalic acid, nitroisophthalic acid, nitroterephthalic acid, nitrosalicylic acid, dinitro Carboxylic acids such as salicylic acid and their carboxylates can be applied, but the complexing agent to be added is not particularly limited. Each of these complexing agents can be used alone or in combination. The amount of the complexing agent added to the plating bath is preferably 0.0001 to 5 mol / L, and more preferably 0.03 to 2 mol / L.

本実施形態に係る銀めっき液のｐＨは、使用する錯化剤に適したｐＨを選択すればよいが、銀めっき液の保存安定性、銀めっき皮膜の実用的な形成速度等の観点から、０．２〜２の範囲であることが好ましい。ｐＨが２より高い場合には、下地に対する密着性に優れ、光沢のある銀めっき皮膜が形成されるが、銀めっき皮膜の形成速度が遅く、銀めっき液の保存安定性が損なわれる。また、０．２より低い場合には、酸の使用量が徒に増加するばかりであり、銀めっき皮膜の特性は改善されない。   The pH of the silver plating solution according to the present embodiment may be selected to be a pH suitable for the complexing agent to be used, but from the viewpoint of storage stability of the silver plating solution, practical formation rate of the silver plating film, etc. A range of 0.2 to 2 is preferable. When the pH is higher than 2, a silver plating film having excellent adhesion to the base and a gloss is formed, but the formation rate of the silver plating film is slow and the storage stability of the silver plating solution is impaired. On the other hand, if it is lower than 0.2, the amount of acid used is only increased and the characteristics of the silver plating film are not improved.

銀めっき液のｐＨを０．２〜２の範囲に調製するためには、有機酸および無機酸を使用することができる。有機酸としては、ギ酸、クロロ酢酸、２−クロロプロピオン酸、グリコール酸、乳酸、アミノ安息香酸、パラニトロ安息香酸、メタンスルホン酸、パラトルエンスルホン酸、サリチル酸、シュウ酸、マレイン酸、フマール酸、酒石酸、クエン酸、フェノキシ酢酸、フタル酸等であり、無機酸としては、リン酸、硫酸、硝酸等が挙げられるが、これらに限定されるものではない。これらの酸は一種または二種以上を併用して用いることができる。   In order to adjust the pH of the silver plating solution to a range of 0.2 to 2, an organic acid and an inorganic acid can be used. Organic acids include formic acid, chloroacetic acid, 2-chloropropionic acid, glycolic acid, lactic acid, aminobenzoic acid, paranitrobenzoic acid, methanesulfonic acid, paratoluenesulfonic acid, salicylic acid, oxalic acid, maleic acid, fumaric acid, tartaric acid Citric acid, phenoxyacetic acid, phthalic acid and the like, and inorganic acids include, but are not limited to, phosphoric acid, sulfuric acid, nitric acid and the like. These acids can be used alone or in combination of two or more.

なお、銀めっき液のｐＨを調整するために、水酸化ナトリウム、水酸化カリウム等の水酸化アルカリやアンモニア水等を用いることができる。   In order to adjust the pH of the silver plating solution, an alkali hydroxide such as sodium hydroxide or potassium hydroxide, aqueous ammonia, or the like can be used.

銀めっき液は、銀めっき皮膜の光沢を高めるために、界面活性剤を含んでも良い。界面活性剤としては、ポリオキシエチレンアルキルエーテル、ポリオキシエチレンアルキルフェニルエーテル、ポリオキシエチレンポリオキシプロピレンブロックコポリマー、アルキルアミンポリエチレンオキサイド等の非イオン系界面活性剤が好ましい。銀めっき液中の界面活性剤の濃度は、０．０１〜５質量％であることが好ましい。   The silver plating solution may contain a surfactant in order to increase the gloss of the silver plating film. As the surfactant, nonionic surfactants such as polyoxyethylene alkyl ether, polyoxyethylene alkylphenyl ether, polyoxyethylene polyoxypropylene block copolymer, alkylamine polyethylene oxide and the like are preferable. The concentration of the surfactant in the silver plating solution is preferably 0.01 to 5% by mass.

銀めっき液を用いて、被めっき物である端子形状の銅に銀めっき処理を行う際の条件としては、銀めっき液の温度を１０〜７０℃に設定することが好ましい。銀めっきの処理時間については、所望の膜厚の銀めっき皮膜が析出するまで、被めっき物を銀めっき液に接触させればよく、その接触時間は通常１０秒〜３０分の範囲が好ましく、好ましくは１分〜５分であり、より好ましくは３０秒〜１０分である。銀めっき液と被めっき物との接触方法としては、浸漬、噴霧、塗布等の方法が挙げられる。なお、銀めっき処理を行うに当たっては、酸クリーナーあるいはマイクロエッチング剤を使用して、予め被めっき物の金属表面を清浄化することが望ましい。   As a condition for performing silver plating on the terminal-shaped copper that is the object to be plated using the silver plating solution, the temperature of the silver plating solution is preferably set to 10 to 70 ° C. About the processing time of silver plating, what is necessary is just to contact a to-be-plated object with a silver plating solution until the silver plating film of desired film thickness deposits, The contact time has the preferable range normally for 10 second-30 minutes, Preferably it is 1 minute-5 minutes, More preferably, it is 30 seconds-10 minutes. Examples of the contact method between the silver plating solution and the object to be plated include methods such as immersion, spraying and coating. In performing silver plating, it is desirable to clean the metal surface of the object to be plated in advance using an acid cleaner or a microetching agent.

無電解パラジウムめっき皮膜を形成する場合、置換パラジウムめっきや還元剤を用いる還元型パラジウムめっきが適用できる。無電解パラジウムめっきによるパラジウム層の形成方法としては、特に、置換パラジウムめっきを行った後、還元型パラジウムめっきを行う方法が好ましい。これは、銅表面はそのままでは無電解パラジウムめっき反応が起こりづらい傾向にあるためである。あらかじめ置換パラジウムめっきでパラジウムを置換析出させておき、その後に還元型パラジウムめっきによりパラジウム層を析出させることで、良好にパラジウム層を形成することができる。   When forming an electroless palladium plating film, substitutional palladium plating or reduced palladium plating using a reducing agent can be applied. As a method for forming a palladium layer by electroless palladium plating, a method in which reduced palladium plating is performed after displacement palladium plating is particularly preferable. This is because the electroless palladium plating reaction tends to hardly occur if the copper surface is left as it is. A palladium layer can be satisfactorily formed by preliminarily depositing and depositing palladium by substitution palladium plating and then depositing a palladium layer by reduction-type palladium plating.

無電解パラジウムめっき皮膜の厚みは、０．００５〜０．３５μｍであると好ましく、０．０１〜０．２μｍであるとより好ましく、０．０３〜０．１５μｍであると更に好ましい。無電解パラジウムめっき皮膜の厚みが０．３５μｍを越えると、銅ワイヤボンディングを行っても無電解パラジウムめっき皮膜を押し退けることができずに、銅・銅結合を得られないワイヤボンディング端子が生じてしまうことがある。パラジウムと銅ワイヤは接合強度そのものが低いため、良好なワイヤボンディング性を得るためには、無電解パラジウムめっき皮膜の厚みは０．３５μｍ以下とすることが好ましい。一方、無電解パラジウムめっき皮膜の厚みを０．００５μｍ以上とすることにより、無電解パラジウムめっき皮膜が充分に析出し、例えばワイヤボンディング前に行う１５０℃の高温処理を考慮した場合であっても、銅がパラジウムめっき表面に拡散しにくくなるため、充分なワイヤボンディング接続信頼性が得られやすい。   The thickness of the electroless palladium plating film is preferably 0.005 to 0.35 μm, more preferably 0.01 to 0.2 μm, and still more preferably 0.03 to 0.15 μm. If the thickness of the electroless palladium plating film exceeds 0.35 μm, even if copper wire bonding is performed, the electroless palladium plating film cannot be pushed away, resulting in a wire bonding terminal that cannot obtain a copper-copper bond. Sometimes. Since the bonding strength itself of palladium and copper wire is low, the thickness of the electroless palladium plating film is preferably 0.35 μm or less in order to obtain good wire bonding properties. On the other hand, by setting the thickness of the electroless palladium plating film to 0.005 μm or more, the electroless palladium plating film is sufficiently deposited, for example, even when considering a high temperature treatment at 150 ° C. performed before wire bonding, Since copper hardly diffuses on the surface of the palladium plating, sufficient wire bonding connection reliability is easily obtained.

特にパラジウムめっき皮膜は、金めっき皮膜や銀めっき皮膜と比較して、銅の拡散抑制効果が高いために、パラジウムめっき皮膜を用いることが最も好ましいが、金めっき皮膜や銀めっき皮膜と比較して硬度が硬く、銅ワイヤボンディングを行った際に皮膜を押し退けることができないため、純度の選定が非常に重要である。   In particular, a palladium plating film is most preferable to use a palladium plating film because it has a higher copper diffusion suppression effect than a gold plating film or a silver plating film, but compared to a gold plating film or a silver plating film. Since the hardness is hard and the film cannot be pushed away when copper wire bonding is performed, the selection of purity is very important.

無電解パラジウムめっきに用いる還元剤に、ギ酸化合物を使用すると、得られるパラジウム層の純度がほぼ１００％になり、その時のビッカース硬度は１５０ＨＶである。純度がほぼ１００％の金めっき皮膜のビッカース硬度が４０〜８０ＨＶ、純度がほぼ１００％の銀めっき皮膜のビッカース硬度が６０〜１００ＨＶであることから、パラジウム皮膜は金や銀めっき皮膜と比較して銅ワイヤボンディングを行った際に皮膜を押し退けづらくなる。一方、還元剤に次亜リン酸を用いて、リン濃度を１．５％、３％、６％にすると、ビッカース硬度はそれぞれ約４２０ＨＶ、約５３０ＨＶ、約５８０ＨＶとなり非常に硬くなる。このため、純度がほぼ１００％のパラジウムめっき皮膜の厚みは０．３５μｍ以下であることが好ましく、リン濃度が１．５％では０．２μｍ以下、リン濃度が３%では０．１５μｍ以下、リン濃度が６%以上では０．１２μｍ以下であることが好ましい。   When a formic acid compound is used as a reducing agent used for electroless palladium plating, the purity of the obtained palladium layer becomes almost 100%, and the Vickers hardness at that time is 150 HV. Since the Vickers hardness of the gold plating film having a purity of almost 100% is 40 to 80 HV and the Vickers hardness of the silver plating film having a purity of almost 100% is 60 to 100 HV, the palladium film is compared with the gold or silver plating film. When copper wire bonding is performed, it is difficult to push the film. On the other hand, when hypophosphorous acid is used as the reducing agent and the phosphorus concentration is 1.5%, 3%, and 6%, the Vickers hardness becomes about 420 HV, about 530 HV, and about 580 HV, respectively, and becomes extremely hard. For this reason, the thickness of the palladium plating film having a purity of almost 100% is preferably 0.35 μm or less, 0.2 μm or less at a phosphorus concentration of 1.5%, 0.15 μm or less at a phosphorus concentration of 3%, phosphorus When the concentration is 6% or more, it is preferably 0.12 μm or less.

ワイヤボンディング端子に、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とをより確実に設ける観点から、めっき皮膜がパラジウムめっき皮膜である場合、下記（２−１）〜（２−４）のいずれかのパラジウムめっき皮膜が好ましい。
（２−１）厚さが０．００５〜０．３５μｍであり、純度が９９％以上のパラジウムめっき皮膜
（２−２）厚さが０．００５〜０．２５μｍであり、純度が９８％以上のパラジウムめっき皮膜
（２−３）厚さが０．００５〜０．１５μｍであり、純度が９７％以上のパラジウムめっき皮膜
（２−４）厚さが０．００５〜０．１２μｍであり、純度が９４％以上のパラジウムめっき皮膜 From the viewpoint of more reliably providing the wire bonding terminal with the place where the plating film is formed and the place where the terminal-shaped copper and the copper wire are directly joined, when the plating film is a palladium plating film, the following (2 The palladium plating film in any one of -1)-(2-4) is preferable.
(2-1) A palladium plating film having a thickness of 0.005 to 0.35 μm and a purity of 99% or more (2-2) A thickness of 0.005 to 0.25 μm and a purity of 98% or more The palladium plating film (2-3) has a thickness of 0.005 to 0.15 μm, and the purity of the palladium plating film (2-4) having a purity of 97% or more is 0.005 to 0.12 μm. Palladium plating film with 94% or more

無電解パラジウムめっきに用いるめっき液のパラジウムの供給源としては、特に限定されないが、塩化パラジウム、塩化パラジウムナトリウム、塩化パラジウムアンモニウム、硫酸パラジウム、硝酸パラジウム、酢酸パラジウム、酸化パラジウム等のパラジウム化合物等が挙げられる。具体的には、酸性塩化パラジウム「ＰｄＣｌ２／ＨＣｌ」、硝酸テトラアンミンパラジウム「Ｐｄ（ＮＨ３）４（ＮＯ３）2」、ジニトロジアンミンパラジウム「Ｐｄ（ＮＨ３）２（ＮＯ２）２」、ジシアノジアンミンパラジウム「Ｐｄ（ＣＮ）２（ＮＨ３）２」、ジクロロテトラアンミンパラジウム「Ｐｄ（ＮＨ３）４Ｃｌ２」、スルファミン酸パラジウム「Ｐｄ（ＮＨ２ＳＯ３）２」、硫酸ジアンミンパラジウム「Ｐｄ（ＮＨ３）２ＳＯ４」、シュウ酸テトラアンミンパラジウム「Ｐｄ（ＮＨ３）４Ｃ２Ｏ４」、硫酸パラジウム「ＰｄＳＯ４」等を適用することができる。また、めっき液に添加する緩衝剤等についても特に限定されない。 Although it does not specifically limit as a supply source of palladium of the plating solution used for electroless palladium plating, Palladium compounds, such as palladium chloride, sodium palladium chloride, palladium ammonium chloride, palladium sulfate, palladium nitrate, palladium acetate, palladium oxide, etc. are mentioned. It is done. Specifically, acidic palladium chloride “PdCl 2 / HCl”, tetraammine palladium nitrate “Pd (NH 3 ) 4 (NO 3 ) 2 ”, dinitrodiammine palladium “Pd (NH 3 ) 2 (NO 2 ) 2 ”, dicyano Diammine palladium “Pd (CN) 2 (NH 3 ) 2 ”, dichlorotetraammine palladium “Pd (NH 3 ) 4 Cl 2 ”, palladium sulfamate “Pd (NH 2 SO 3 ) 2 ”, diammine palladium sulfate “Pd (NH 3 ) 2 SO 4 ”, tetraamminepalladium oxalate“ Pd (NH 3 ) 4 C 2 O 4 ”, palladium sulfate“ PdSO 4 ”and the like can be applied. Further, the buffering agent added to the plating solution is not particularly limited.

無電解パラジウムめっきにより形成されるパラジウム層は、パラジウムの純度が９０質量％以上であると好ましく、９９質量％以上であるとより好ましく、１００質量％に近いと特に好ましい。パラジウムの純度が９０質量％以上であると、その形成時に銅上への析出が充分に得られやすくなり、ワイヤボンディング性やはんだ接続信頼性が充分に得られやすくなる。   The palladium layer formed by electroless palladium plating preferably has a palladium purity of 90% by mass or more, more preferably 99% by mass or more, and particularly preferably close to 100% by mass. When the purity of palladium is 90% by mass or more, precipitation on copper is easily obtained at the time of formation, and wire bonding property and solder connection reliability are easily obtained.

無電解パラジウムめっきに用いる還元剤に、ギ酸化合物を使用すると、得られるパラジウム層の純度が９９質量％以上になり易くなり、均一な析出は可能となる。また、還元剤に次亜リン酸や亜リン酸等のリン含有化合物や、ホウ素含有化合物を使用する場合は、得られるパラジウム層がパラジウム−リン合金やパラジウム−ホウ素合金になるため、その場合は、パラジウムの純度が９０質量％以上となるように還元剤の濃度、ｐＨ、浴温などを調節することが好ましい。   When a formic acid compound is used as a reducing agent used in electroless palladium plating, the purity of the obtained palladium layer is likely to be 99% by mass or more, and uniform precipitation is possible. In addition, when a phosphorus-containing compound such as hypophosphorous acid or phosphorous acid or a boron-containing compound is used as the reducing agent, the resulting palladium layer becomes a palladium-phosphorus alloy or palladium-boron alloy. It is preferable to adjust the concentration, pH, bath temperature and the like of the reducing agent so that the purity of palladium is 90% by mass or more.

パラジウムめっき皮膜の上部に更に無電解金めっき皮膜を形成してもよい。無電解金めっき皮膜は、例えば、置換・還元金めっきを行うか、或いは、置換金めっきを行った後に還元型の金めっきを行う無電解金めっきなどによって形成することができる。パラジウムめっき皮膜の厚みが０．０３μｍ以下の場合、パラジウムめっき皮膜と金めっき皮膜の厚みの合計は０．４μｍ以下、パラジウムめっき皮膜の厚みが０．０３μｍよりも厚く、０．３μｍ以下の場合は、パラジウムめっき皮膜と金めっき皮膜の厚みの合計は０．３μｍ以下であることが好ましい。   An electroless gold plating film may be further formed on the palladium plating film. The electroless gold plating film can be formed, for example, by substitution / reduction gold plating, or by electroless gold plating in which reduction gold plating is performed after substitution gold plating. When the thickness of the palladium plating film is 0.03 μm or less, the total thickness of the palladium plating film and the gold plating film is 0.4 μm or less, and when the thickness of the palladium plating film is greater than 0.03 μm and 0.3 μm or less The total thickness of the palladium plating film and the gold plating film is preferably 0.3 μm or less.

本実施形態においては、厚さが０．００３〜０．２μｍのパラジウムめっき皮膜と厚さが０．０３〜０．２μｍの金めっき皮膜との組合せが好ましく、厚みが０．０１〜０．１μｍのパラジウムめっき皮膜と、厚みが０．００５〜０．１μｍの金めっき皮膜との組み合わせがより好ましい。パラジウムめっき皮膜が銅の拡散を防止することでワイヤボンディング前の熱処理によるワイヤボンディング性の低下を抑制できるとともに、銅ワイヤボンディングを行った際に、パラジウムめっき皮膜に直接銅ワイヤを接着させる場合と比較し、金めっき皮膜が銅ワイヤとの初期の接着性を改善できるので、パラジウムめっき皮膜と金めっき皮膜両方の皮膜の変形が起こりやすくなるため、端子形状の銅と銅ワイヤの銅との接合が起こりやすく、結果として銅ワイヤボンディング性を向上させることができる。   In the present embodiment, a combination of a palladium plating film having a thickness of 0.003 to 0.2 μm and a gold plating film having a thickness of 0.03 to 0.2 μm is preferable, and the thickness is 0.01 to 0.1 μm. A combination of the palladium plating film and a gold plating film having a thickness of 0.005 to 0.1 μm is more preferable. The palladium plating film prevents copper from diffusing and prevents the wire bondability from deteriorating due to heat treatment before wire bonding. Compared with copper wire bonding directly to the palladium plating film when copper wire bonding is performed. However, since the gold plating film can improve the initial adhesiveness with the copper wire, the deformation of both the palladium plating film and the gold plating film is likely to occur, so that the copper of the terminal shape and the copper of the copper wire can be joined. As a result, the copper wire bonding property can be improved.

無電解金めっき皮膜は、例えば、置換・還元金めっきを行うか、或いは、置換金めっきを行った後に還元型の金めっきを行う無電解金めっきなどによって形成することができる。無電解金めっきは、本発明による効果が得られる限り、どちらの手法を用いて行ってもよいが、置換金めっきを行った後に還元型の金めっきを行う方法は、下層の金属（この場合は銅）との良好な密着性が得られる観点から好ましく、また置換・還元金めっきを行う方法は、めっきの際に下層の金属（この場合は銅）を溶出させ難く、良好な金めっき皮膜を形成できる傾向にある。   The electroless gold plating film can be formed, for example, by substitution / reduction gold plating, or by electroless gold plating in which reduction gold plating is performed after substitution gold plating. Electroless gold plating may be performed using either method as long as the effect of the present invention can be obtained. However, the method of performing reduction-type gold plating after performing substitution gold plating is performed by using a lower layer metal (in this case). Is preferable from the viewpoint of obtaining good adhesion to copper), and the method of performing substitution / reduction gold plating is difficult to elute the lower layer metal (copper in this case) during plating, and a good gold plating film Tend to form.

置換金めっき後、還元型の金めっきを行う場合、具体的には、ＨＧＳ―１００（日立化成工業株式会社製、商品名）のような置換金めっき液により、０．０１〜０．１μｍ程度の金めっき下地皮膜（置換金めっき皮膜）を形成した後、その上に、ＨＧＳ―２０００（日立化成工業株式会社製、商品名）のような還元型の無電解金めっき液により、０．１〜０．４μｍ程度の金めっき仕上げ層（還元型の金めっき皮膜）を形成する方法が挙げられる。ただし、無電解金めっきの手法はこれに限定されず、通常行われる金めっきに適した方法であれば制限なく適用できる。   When reducing gold plating is performed after displacement gold plating, specifically, about 0.01 to 0.1 μm with a displacement gold plating solution such as HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.). After forming a gold plating base film (substitution gold plating film) of 0.1%, a reduced electroless gold plating solution such as HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) A method of forming a gold plating finish layer (reduction type gold plating film) of about ~ 0.4 μm can be mentioned. However, the method of electroless gold plating is not limited to this, and any method that is suitable for gold plating that is usually performed can be applied without limitation.

置換金めっきに用いるめっき液には、シアン化合物を含むものと含まないものがあるが、いずれのめっき液でも使用できる。なかでも、シアン化合物を含むものが好ましい。この理由としては、銅における置換金めっきの均一性は、シアンを含むめっき液を用いた方が、シアンを含まないものを用いた場合と比較して良好であることが挙げられる。このようなシアンを含むめっき液で置換金めっきを行った後に、後述するような還元型の金めっきを行うと、金めっき皮膜が均一に成長し易い傾向にある。   Plating solutions used for displacement gold plating include those containing a cyanide compound and those containing no cyanide compound, but any plating solution can be used. Of these, those containing a cyanide compound are preferred. The reason for this is that the uniformity of the displacement gold plating in copper is better when a plating solution containing cyan is used than when a solution containing no cyan is used. After performing substitution gold plating with such a plating solution containing cyan, if reduction-type gold plating as described later is performed, the gold plating film tends to grow uniformly.

還元型の金めっき皮膜は、置換金めっき皮膜に更に金皮膜を形成することができる。そのため、置換金めっきに続いて還元型の金めっきを行うことで、厚い金めっき皮膜を形成することが可能となる。還元型の金めっきに用いるめっき液は、還元剤を含むことで、自己触媒的に金層を形成できる。このめっき液にも、シアン化合物を含むものと含まないものがあるが、いずれのめっき液でも使用できる。   The reduction-type gold plating film can further form a gold film on the replacement gold plating film. Therefore, it is possible to form a thick gold plating film by performing reduction-type gold plating following substitution gold plating. The plating solution used for reduction-type gold plating can form a gold layer in an autocatalytic manner by containing a reducing agent. These plating solutions include those containing a cyanide compound and those not containing a cyanide compound, but any plating solution can be used.

還元型の金めっきに用いるめっき液の還元剤としては、酸化により水素ガスが発生しないものが好ましい。ここで、水素ガスが発生しない、もしくは発生しにくい還元剤としては、アスコルビン酸、尿素系化合物、フェニル系化合物等が挙げられる。なお、水素ガスが発生する還元剤としては、ホスフィン酸塩、ヒドラジンがある。このような還元剤を含む金めっき液は、６０〜８０℃程度の温度で使用可能なものが好ましい。   As the reducing agent for the plating solution used for reduction-type gold plating, one that does not generate hydrogen gas by oxidation is preferable. Here, examples of the reducing agent that does not generate or hardly generates hydrogen gas include ascorbic acid, urea-based compounds, and phenyl-based compounds. Examples of the reducing agent that generates hydrogen gas include phosphinates and hydrazine. The gold plating solution containing such a reducing agent is preferably one that can be used at a temperature of about 60 to 80 ° C.

一方、置換・還元金めっきは、置換金めっきと還元型の金めっき反応を同一の液で行うものである。このようなめっき液には、シアン化合物を含むものと含まないものがあり、いずれのめっき液でも使用することができる。また、置換・還元金めっきを行った後に、金層の厚膜化のために更に無電解金めっきを行うこともできる。   On the other hand, substitution / reduction gold plating is a method in which substitution gold plating and reduction type gold plating reaction are performed in the same solution. Such plating solutions include those containing a cyanide compound and those containing no cyanide compound, and any plating solution can be used. In addition, after the substitution / reduction gold plating, electroless gold plating can be further performed to increase the thickness of the gold layer.

このようにして形成される金めっき皮膜は、９９質量％以上の純度の金からなることが好ましい。金めっき皮膜の金の純度が９９質量％以上であると、この部分を端子として適用する際に銅ワイヤボンディング接続信頼性が得られやすい。接続信頼性をより高める観点からは、金層の純度は、９９．５質量％以上であることがより好ましい。   The gold plating film thus formed is preferably made of gold having a purity of 99% by mass or more. When the gold purity of the gold plating film is 99% by mass or more, it is easy to obtain copper wire bonding connection reliability when this portion is applied as a terminal. From the viewpoint of further improving connection reliability, the purity of the gold layer is more preferably 99.5% by mass or more.

また、金めっき皮膜の厚さは、０．０３〜０．４μｍとすることが好ましく、０．０５〜０．３μｍとすることがより好ましく、０．１μｍ〜０．２５μｍとすることが更に好ましい。   The thickness of the gold plating film is preferably 0.03 to 0.4 μm, more preferably 0.05 to 0.3 μm, and still more preferably 0.1 μm to 0.25 μm. .

金めっき皮膜の厚みが０．４μｍ〜０．７μｍの範囲では、銅ワイヤボンディングを行っても皮膜を押し退けることができずに、銅・銅結合を得られないワイヤボンディング端子が生じてしまう。特に、銅ワイヤボンディング後に、端子形状の銅／０．０５〜０．３μｍの金めっき皮膜／銅ワイヤの３層構造となり、高温高湿の環境下で０．０５〜０．３μｍの金めっき皮膜が銅と合金化されて金・銅合金を形成し、脆弱層が形成されてボンディング部の接続信頼性が低下する問題があり好ましくない。   When the thickness of the gold plating film is in the range of 0.4 μm to 0.7 μm, even if copper wire bonding is performed, the film cannot be pushed away, resulting in a wire bonding terminal that cannot obtain a copper / copper bond. In particular, after copper wire bonding, it becomes a three-layer structure of terminal-shaped copper / 0.05-0.3 μm gold plating film / copper wire, and 0.05-0.3 μm gold plating film in a high temperature and high humidity environment This is not preferable because it is alloyed with copper to form a gold / copper alloy, and a brittle layer is formed to reduce the connection reliability of the bonding portion.

金めっき皮膜の厚みが０．７μｍを越えると、金めっき皮膜と銅ワイヤとの良好な接続が得られるが、微細配線に用いた場合は、ブリッジが発生しやすくなるために、好ましくなく、また、経済的な観点からも好ましくない。更に、この場合も、銅・銅結合を得られないワイヤボンディング端子が生じてしまう。   If the thickness of the gold plating film exceeds 0.7 μm, a good connection between the gold plating film and the copper wire can be obtained. However, when used for fine wiring, it is not preferable because a bridge is easily generated. This is also not preferable from an economic viewpoint. Furthermore, also in this case, a wire bonding terminal that cannot obtain a copper-copper bond is generated.

一方、金めっき皮膜の厚みが０．０３μｍ以上であると、金めっき皮膜が析出していない部分ができにくくなり、例えばワイヤボンディング前に行う１５０℃の高温処理を考慮した場合であっても、銅が金めっき表面に拡散しにくくなるため、充分なワイヤボンディング接続信頼性が得られやすくなる。   On the other hand, when the thickness of the gold plating film is 0.03 μm or more, it becomes difficult to form a portion where the gold plating film is not deposited, for example, even when considering a high temperature treatment at 150 ° C. performed before wire bonding, Since copper hardly diffuses on the gold plating surface, sufficient wire bonding connection reliability is easily obtained.

ワイヤボンディング端子と銅ワイヤとの接合にはキャピラリーが用いられる。   A capillary is used to join the wire bonding terminal and the copper wire.

ワイヤボンディングで用いるキャピラリーとしては、キャピラリー先端の仕上げは「ポリッシュ加工」と呼ばれる平滑性のある表面仕上げが一般的であるが、本実施形態で用いるキャピラリーは、「マット加工」と呼ばれるキャピラリーの先端面を粗くした仕上げの方がより効果的である。具体的には、ＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）のような「マット加工」を施したキャピラリーが好ましい。   As for the capillary used in wire bonding, the finish of the capillary tip is generally a smooth surface finish called “polishing”, but the capillary used in this embodiment is the tip of the capillary called “matting” A rough finish is more effective. Specifically, a capillary subjected to “mat processing” such as CuPRAplus (registered trademark) Capillary (product name, manufactured by Kulicke & Soffa) is preferable.

ワイヤボンディング後の、端子形状の銅と銅ワイヤとが直接接合された箇所の十点平均粗さ（Ｒｚ）を０．１５〜１．０μｍとすることが好ましく、０．２〜０．８μｍとすることがより好ましく、０．３μｍ〜０．６μｍとすることが更に好ましい。   The ten-point average roughness (Rz) of the portion where the terminal-shaped copper and the copper wire are directly bonded after wire bonding is preferably 0.15 to 1.0 μm, and is preferably 0.2 to 0.8 μm. More preferably, it is more preferably 0.3 μm to 0.6 μm.

十点平均粗さ（Ｒｚ）が、１．０μｍ以下であると、端子形状の銅と銅ワイヤとが直接接合された領域が狭くなりにくく、充分なワイヤボンディング接続信頼性が得られやすい。また、一方、十点平均粗さ（Ｒｚ）が、０．１５μｍ以上であると、端子形状の銅と銅ワイヤとが直接接合されやすく、端子形状の銅と銅ワイヤとが直接接合された領域を広くすることができ、充分なワイヤボンディング接続信頼性が得られやすくなる。   When the ten-point average roughness (Rz) is 1.0 μm or less, the region where the terminal-shaped copper and the copper wire are directly bonded is not easily narrowed, and sufficient wire bonding connection reliability is easily obtained. On the other hand, when the 10-point average roughness (Rz) is 0.15 μm or more, the terminal-shaped copper and the copper wire are easily bonded directly, and the terminal-shaped copper and the copper wire are directly bonded. Therefore, sufficient wire bonding connection reliability can be easily obtained.

本実施形態で用いる銅ワイヤは、９９．９質量％以上のＣｕであることが好ましい。また、銅ワイヤは、表面の酸化を防止するために異種金属がコートされていてもよい。異種金属としては、銅の拡散防止効果に優れたＰｄが好ましい。   The copper wire used in this embodiment is preferably 99.9% by mass or more of Cu. Further, the copper wire may be coated with a different metal in order to prevent surface oxidation. As the dissimilar metal, Pd having an excellent copper diffusion preventing effect is preferable.

＜半導体チップ搭載用基板の製造＞
（実施例１）
（１ａ）内層板の準備
まず、絶縁基材に厚さ１８μｍの銅箔を両面に貼り合わせた、厚さ０．２ｍｍのガラス布基材エポキシ銅張積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）を準備し、その不要な箇所の銅箔をエッチングにより除去し、スルーホールを形成して、表面に内層回路が形成された内層板を得た。 <Manufacture of semiconductor chip mounting substrate>
Example 1
(1a) Preparation of inner layer board First, MCL-E-679 (Hitachi), which is a glass cloth base epoxy copper clad laminate having a thickness of 0.2 mm, in which a copper foil having a thickness of 18 μm is bonded to both sides of an insulating base. Kasei Kogyo Co., Ltd., trade name) was prepared, and the copper foil at unnecessary portions was removed by etching to form through holes, thereby obtaining an inner layer plate having an inner layer circuit formed on the surface.

（１ｂ）樹脂付き銅箔の積層
内層板の両面に、３μｍの厚みの銅箔に接着剤を塗布したＭＣＦ−７０００ＬＸ（日立化成工業株式会社製、商品名）を、１７０℃、３０ｋｇｆ／ｃｍ２の条件で６０分間加熱加圧してラミネートした。 (1b) Lamination of resin-coated copper foil MCF-7000LX (trade name, manufactured by Hitachi Chemical Co., Ltd.) obtained by applying an adhesive to a copper foil having a thickness of 3 μm on both surfaces of the inner layer plate, 170 ° C., 30 kgf / cm 2. The laminate was heated and pressed for 60 minutes under the following conditions.

（１ｃ）ＩＶＨの形成
炭酸ガスインパクトレーザー穴あけ機Ｌ−５００（住友重機械工業株式会社製、商品名）により、銅箔上から直径８０μｍの非貫通孔であるＩＶＨ３０をあけた。さらに、ＩＶＨ３０形成後の基板を過マンガン酸カリウム６５ｇ／Ｌと水酸化ナトリウム４０ｇ／Ｌの混合水溶液に、液温７０℃で２０分間浸漬し、孔内のスミアの除去を行った。 (1c) Formation of IVH IVH30, which is a non-through hole having a diameter of 80 μm, was drilled from above the copper foil using a carbon dioxide impact laser drilling machine L-500 (trade name, manufactured by Sumitomo Heavy Industries, Ltd.). Furthermore, the substrate after IVH30 formation was immersed in a mixed aqueous solution of potassium permanganate 65 g / L and sodium hydroxide 40 g / L at a liquid temperature of 70 ° C. for 20 minutes to remove smears in the holes.

（１ｄ）無電解銅めっき
（１ｃ）の工程後の基板を、パラジウム溶液であるＨＳ−２０２Ｂ（日立化成工業株式会社製、商品名）に２５℃で１５分間浸漬して、銅箔表面に触媒を付与した。その後、ＣＵＳＴ−２０１（日立化成工業株式会社製、商品名）を使用して、液温２５℃、３０分の条件で無電解銅めっきを行った。これにより銅箔上及びＩＶＨ内の表面に厚さ０．３μｍの無電解銅めっき層を形成した。 (1d) The substrate after the electroless copper plating (1c) step is immersed in HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a palladium solution, for 15 minutes at 25 ° C. Was granted. Then, using CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), electroless copper plating was performed at a liquid temperature of 25 ° C. for 30 minutes. Thus, an electroless copper plating layer having a thickness of 0.3 μm was formed on the copper foil and on the surface in IVH.

（１ｅ）電解めっきレジストの形成
ドライフィルムフォトレジストであるＲＹ−３０２５（日立化成工業株式会社製、商品名）を、無電解銅めっき層の表面にラミネートし、電解銅めっきを行うべき箇所をマスクするフォトマスクを介してフォトレジストに紫外線を露光した後、現像して、電解めっきレジストを形成した。 (1e) Formation of electrolytic plating resist RY-3025 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film photoresist, is laminated on the surface of the electroless copper plating layer, and a portion to be subjected to electrolytic copper plating is masked The photoresist was exposed to ultraviolet light through a photomask to be developed and then developed to form an electrolytic plating resist.

（１ｆ）電解銅めっき
硫酸銅浴を用い、液温２５℃、電流密度１．０Ａ／ｄｍ２の条件で、銅めっき層３上に電解銅めっきを１２μｍほどの厚さが得られるように行い、回路導体幅／回路導体間隔（Ｌ／Ｓ）＝１５／１５μｍのパターン形状を有する第２の銅層を形成した。また、かかるパターン形状を形成した面と反対側の面には、はんだボール接続用のランド径６００μｍのパッドが形成されるように、電解銅めっき皮膜を形成した。 (1f) Electrolytic copper plating Using a copper sulfate bath, electrolytic copper plating is performed on the copper plating layer 3 at a liquid temperature of 25 ° C. and a current density of 1.0 A / dm 2 so as to obtain a thickness of about 12 μm. Then, a second copper layer having a pattern shape of circuit conductor width / circuit conductor interval (L / S) = 15/15 μm was formed. Further, an electrolytic copper plating film was formed on the surface opposite to the surface on which the pattern shape was formed, so that a pad having a land diameter of 600 μm for solder ball connection was formed.

（１ｇ）電解めっきレジストの剥離
レジスト剥離液であるＨＴＯ（ニチゴー・モートン株式会社製、商品名）を用いて、電解めっきレジストの除去を行った。 (1g) Stripping of Electroplating Resist The electrolytic plating resist was removed using HTO (trade name, manufactured by Nichigo Morton Co., Ltd.) which is a resist stripping solution.

（１ｈ）エッチング
主成分として硫酸２０ｇ／Ｌ、過酸化水素１０ｇ／Ｌの組成のエッチング液を用いて、電解めっきレジストで覆われていた部分の銅をエッチングにより除去した。 (1h) Etching Using an etching solution having a composition of 20 g / L sulfuric acid and 10 g / L hydrogen peroxide as main components, the copper portion covered with the electrolytic plating resist was removed by etching.

（１ｉ）ソルダーレジストの形成
エッチング後の基板の上側の表面に、感光性のソルダーレジスト「ＰＳＲ−４０００ ＡＵＳ５」（太陽インキ製造株式会社製、商品名）をロールコータにより塗布し、硬化後の厚みが４０μｍとなるようにした。続いて、露光・現像をすることにより、導体回路上の所望の場所に開口部を有するソルダーレジストを形成した。また、下側の表面には、はんだボール接続用のパッドを形成するために、ランド径６００μｍの銅パッドの上部に、５００μｍの開口径を有するソルダーレジストを形成した。 (1i) Formation of Solder Resist A photosensitive solder resist “PSR-4000 AUS5” (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) is applied to the upper surface of the substrate after etching with a roll coater, and the thickness after curing. Was set to 40 μm. Subsequently, by performing exposure and development, a solder resist having an opening at a desired location on the conductor circuit was formed. On the lower surface, a solder resist having an opening diameter of 500 μm was formed on a copper pad having a land diameter of 600 μm in order to form a solder ball connection pad.

（１ｊ）無電解パラジウムめっき
ソルダーレジスト形成後の基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗した。得られた無電解パラジウムめっき皮膜の厚みは０．００５μｍであった。なお、本実施例及び以下の実施例や比較例においては、パラジウム層、銀層、金層の膜厚は、蛍光Ｘ線膜厚計ＳＦＴ９５００（エスアイアイ・ナノテクノロジー株式会社製、商品名）を用いて測定した。 (1j) Electroless palladium plating The substrate after the solder resist is formed is immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L. Was immersed in an ammonium persulfate solution for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes and washed with water for 2 minutes. The thickness of the obtained electroless palladium plating film was 0.005 μm. In the present example and the following examples and comparative examples, the film thickness of the palladium layer, the silver layer, and the gold layer is the fluorescent X-ray film thickness meter SFT9500 (trade name, manufactured by SII Nano Technology Co., Ltd.). And measured.

このようにして、上下面にパラジウム層で覆われた端子部分を有する半導体チップ搭載用基板を得た。この半導体チップ搭載用基板においては、片面の端子部分がワイヤボンディング接続用の端子に該当し、反対面の端子部分がはんだ接続用の端子に該当する。半導体チップ搭載用基板は、これらの端子をそれぞれ１０００個有している（以下の実施例、比較例も同様）。   In this manner, a semiconductor chip mounting substrate having terminal portions covered with palladium layers on the upper and lower surfaces was obtained. In this semiconductor chip mounting substrate, the terminal portion on one side corresponds to a terminal for wire bonding connection, and the terminal portion on the opposite surface corresponds to a terminal for solder connection. The semiconductor chip mounting substrate has 1000 of each of these terminals (the same applies to the following examples and comparative examples).

＜特性評価＞
（１）微細配線形成性
上記で得られた半導体チップ搭載用基板について、下記の基準によりめっき皮膜形成後の微細配線形成性を評価した。得られた結果を表１に示す。
Ａ：ブリッジが形成されておらず、端子部分にめっき皮膜が良好に形成されており、回路導体間隔が１３μｍ以上である。
Ｂ：端子部分の外周に部分的にめっきがはみ出して析出しており、回路導体間隔が１０μｍ以上、１３μｍ未満である。
Ｃ：端子部分の外周に部分的にめっきがはみ出して析出しており、回路導体間隔が８μｍ以上、１０μｍ未満である。
Ｄ：端子部分の外周に部分的にめっきがはみ出して析出しており、回路導体間隔が５μｍ以上、８μｍ未満である。
Ｅ：端子部分の外周に部分的にめっきがはみ出して析出しており、回路導体間隔が５μｍ未満である。 <Characteristic evaluation>
(1) Fine wiring formability About the semiconductor chip mounting substrate obtained above, the fine wiring formability after plating film formation was evaluated according to the following criteria. The obtained results are shown in Table 1.
A: No bridge is formed, the plating film is formed well on the terminal portion, and the circuit conductor interval is 13 μm or more.
B: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is 10 μm or more and less than 13 μm.
C: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the circuit conductor interval is 8 μm or more and less than 10 μm.
D: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is 5 μm or more and less than 8 μm.
E: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is less than 5 μm.

（２）ワイヤボンディング性
上記で得られた半導体チップ搭載用基板について、下記の基準により接続端子のワイヤボンディング性（ワイヤボンディング接続性）を評価した。 (2) Wire bonding property About the board | substrate for semiconductor chip mounting obtained above, the wire bonding property (wire bonding connectivity) of the connection terminal was evaluated by the following reference | standard.

すなわち、実施例１に対応する複数の半導体チップ搭載用基板に対し、未処理（熱処理無し：０時間）と、１５０℃で３、１０、５０時間の熱処理とをそれぞれ実施し、各熱処理時間が経過した時点でワイヤボンディングを行った。ワイヤボンディングは、ワイヤ径２５μｍのＰｄ被覆銅ワイヤ（日鉄マイクロメタル社製、商品名）を用い、１０００箇所のワイヤボンディング接続用の端子の全てで行った。ワイヤボンディング装置としては、Ｐｏｗｅｒ Ｓｅｒｉｅｓ Ｉｃｏｎｎ（Ｋ＆Ｓ社製、商品名）を用い、ボンディング温度（ヒートブロック温度）:１７５℃、ボンド荷重：７０ｇｆ、超音波出力：１２５ｍＡｍｐｓ、超音波時間：２５ｍｓ、スクラブの種類：サークル（円状）、スクラブ回数：２回、の条件を設定した。キャピラリーとして、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いた。   That is, the unprocessed (no heat treatment: 0 hour) and the heat treatment at 150 ° C. for 3, 10 and 50 hours were performed on the plurality of semiconductor chip mounting substrates corresponding to Example 1, respectively. Wire bonding was performed when it passed. Wire bonding was performed using all Pd-coated copper wires having a wire diameter of 25 μm (trade name, manufactured by Nippon Steel Micrometal Co., Ltd.) at all 1000 terminals for wire bonding connection. As the wire bonding apparatus, Power Series Icon (trade name, manufactured by K & S) was used, bonding temperature (heat block temperature): 175 ° C., bond load: 70 gf, ultrasonic output: 125 mAmps, ultrasonic time: 25 ms, scrub The conditions of type: circle (circular), scrub frequency: 2 times were set. As the capillary, CuPRAplus (registered trademark) Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “matted” was used.

銅ワイヤが接合されたワイヤボンディング端子の表面を、収束イオンビーム加工観察装置（ＦＩＢ：Ｆｏｒｃｕｓｅｄ Ｉｏｎ Ｂｅａｍ Ｓｙｓｔｅｍ）を用いて断面加工し、ＦＩＢに併設されているエネルギー分散型Ｘ線分析（ＥＤＳ:Ｅｎｅｒｇｙ Ｄｉｓｐｅｒｓｉｖｅ ｘ−ｒａｙ Ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて断面の面分析を行うことで、端子形状の銅と銅ワイヤとが直接接合されていることを確認した。また、ワイヤボンディング端子の一部にはめっき皮膜が残されていることを確認した。なお、銅ワイヤが接合されたワイヤボンディング端子の表面のＳＥＭ観察結果を図１に示す。   The surface of the wire bonding terminal to which the copper wire is bonded is subjected to cross-section processing using a focused ion beam processing observation apparatus (FIB) and energy dispersive X-ray analysis (EDS: Energy) attached to the FIB. By performing surface analysis of the cross section using Dispersive x-ray Spectroscopy, it was confirmed that the terminal-shaped copper and the copper wire were directly joined. It was also confirmed that a plating film was left on a part of the wire bonding terminal. In addition, the SEM observation result of the surface of the wire bonding terminal with which the copper wire was joined is shown in FIG.

端子形状の銅と銅ワイヤとが直接接合されている箇所の十点平均粗さ（Ｒｚ）は０．３２μｍであった。なお、十点平均粗さ（Ｒｚ）は、原子間力顕微鏡ナノピクス２１００（エスアイアイ・ナノテクノロジー社製）により測定した。   The ten-point average roughness (Rz) of the portion where the terminal-shaped copper and the copper wire were directly joined was 0.32 μm. The ten-point average roughness (Rz) was measured with an atomic force microscope Nanopics 2100 (manufactured by SII Nanotechnology).

ワイヤボンディング後の半導体チップ搭載用基板について、ボンドテスタ（Ｄａｇｅ社製、商品名：ＢＴ２４００ＰＣ）を用いて、銅ワイヤを引っ張り、端子から外れるまでの強度を測定する銅ワイヤプルテストを行い、下記基準に基づいて、ワイヤボンディング接続信頼性について端子毎にそれぞれ評価した。また、ワイヤボンディング前の熱処理を行わなかった基板にワイヤボンディングを行った後、１５０℃で１００、３００、５００、１０００時間の熱処理をそれぞれ実施し、銅ワイヤプルテストを行い、下記基準に基づいて、ワイヤボンディング接続信頼性について端子毎にそれぞれ評価した。得られた結果を表１に示す。
Ａ：ワイヤプル強度の平均値が１０ｇ以上
Ｂ：ワイヤプル強度の平均値が８ｇ以上１０ｇ未満
Ｃ：ワイヤプル強度の平均値が３ｇ以上８ｇ未満
Ｄ：ワイヤプル強度の平均値が３ｇ未満 For the semiconductor chip mounting substrate after wire bonding, using a bond tester (Dage, product name: BT2400PC), a copper wire pull test was performed to measure the strength until the copper wire was pulled and removed from the terminal. Based on this, wire bonding connection reliability was evaluated for each terminal. In addition, after wire bonding was performed on a substrate that had not been heat-treated before wire bonding, heat treatment was performed at 150 ° C. for 100, 300, 500, and 1000 hours, respectively, and copper wire pull tests were performed. The wire bonding connection reliability was evaluated for each terminal. The obtained results are shown in Table 1.
A: The average value of wire pull strength is 10 g or more B: The average value of wire pull strength is 8 g or more and less than 10 g C: The average value of wire pull strength is 3 g or more and less than 8 g D: The average value of wire pull strength is less than 3 g

（３）皮膜の硬度
めっき皮膜の硬度（ビッカース硬度）の測定は、マイクロビッカース硬度計を用いて、クリープ速度５ｇｆ／２ｓ、クリープ時間５ｓで測定した。 (3) Film hardness The plating film hardness (Vickers hardness) was measured using a micro Vickers hardness meter at a creep rate of 5 gf / 2 s and a creep time of 5 s.

（実施例２）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の還元型無電解パラジウムめっき液に７０℃で５秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０１μｍ析出させることにより、端子の銅上に純度約１００％の無電解パラジウム層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 2)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it is immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and reduced electroless palladium plating solution having the following composition. A step of forming an electroless palladium layer having a purity of about 100% on the copper of the terminal by immersing the substrate in 70 ° C. for 5 seconds and further washing with water for 2 minutes to deposit 0.01 μm of the electroless palladium plating film. It was.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３〜７）
実施例２記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表１に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 3 to 7)
Semiconductor chip in the same manner as in Example 2 except that the immersion time in the reduced electroless palladium plating solution described in Example 2 was changed to form an electroless palladium plating film having the film thickness shown in Table 1. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例８）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の無電解パラジウムめっき液に６０℃で５秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０１μｍ析出させることにより、端子の銅上に純度約９９．２％（パラジウム：９９．２質量％、リン：０．８質量％）の無電解パラジウム層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
次亜リン酸ナトリウム：０．００３ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 8)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and electroless palladium plating solution having the following composition. After immersing at 5 ° C. for 5 seconds and further washing with water for 2 minutes to deposit 0.01 μm of electroless palladium plating film, purity of about 99.2% (palladium: 99.2% by mass, phosphorus: A step of forming a 0.8 mass% electroless palladium layer was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Sodium hypophosphite: 0.003 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例９〜１２）
実施例８に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表１に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例８と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 9 to 12)
In the same manner as in Example 8, except that the immersion time in the reduced electroless palladium plating solution described in Example 8 was changed to form an electroless palladium plating film having the film thickness shown in Table 1. A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例１３）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の無電解パラジウムめっき液に６０℃で７秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０１μｍ析出させることにより、端子の銅上に純度約９８．５％（パラジウム：９８．５質量％、リン：１．５質量％）の無電解パラジウム層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
次亜リン酸ナトリウム：０．００５ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 13)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and electroless palladium plating solution having the following composition. It was immersed at 7 ° C. for 7 seconds, and further washed with water for 2 minutes to deposit 0.01 μm of an electroless palladium plating film, whereby a purity of about 98.5% (palladium: 98.5% by mass, phosphorus: A step of forming a 1.5 mass%) electroless palladium layer was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Sodium hypophosphite: 0.005 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例１４〜１６）
実施例１３に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表１に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例１３と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 14 to 16)
In the same manner as in Example 13, except that the immersion time in the reduced electroless palladium plating solution described in Example 13 was changed to form an electroless palladium plating film having the film thickness shown in Table 1. A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例１７）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の無電解パラジウムめっき液に６０℃で１０秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０１μｍ析出させることにより、端子の銅上に純度約９７％（パラジウム：９７質量％、リン：３質量％）の無電解パラジウム層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
次亜リン酸ナトリウム：０．０３ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 17)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and electroless palladium plating solution having the following composition. It is immersed for 10 seconds at a temperature of 2 ° C. and further washed with water for 2 minutes to deposit an electroless palladium plating film of 0.01 μm, so that the purity of the terminal copper is about 97% (palladium: 97 mass%, phosphorus: 3 mass%). The step of forming an electroless palladium layer was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium hypophosphite: 0.03 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例１８〜２０）
実施例１７に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表１に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例１７と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 18 to 20)
The semiconductor was fabricated in the same manner as in Example 17 except that the immersion time in the reduced electroless palladium plating solution described in Example 17 was changed to form an electroless palladium plating film having the film thickness shown in Table 1. A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例２１）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の無電解パラジウムめっき液に６０℃で１０秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０１μｍ析出させることにより、端子の銅上に純度約９４％（パラジウム：９４質量％、リン：６質量％）の無電解パラジウム層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
次亜リン酸ナトリウム：０．１２ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 21)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and electroless palladium plating solution having the following composition. It is immersed for 10 seconds at a temperature of 2 ° C., and further washed with water for 2 minutes to deposit an electroless palladium plating film of 0.01 μm, so that the purity is about 94% on the copper of the terminal (palladium: 94 mass%, phosphorus: 6 mass%). The step of forming an electroless palladium layer was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium hypophosphite: 0.12 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例２２〜２４）
実施例２１に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表１に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例２１と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 22 to 24)
In the same manner as in Example 21, except that the immersion time in the reduced electroless palladium plating solution described in Example 21 was changed to form an electroless palladium plating film having the thickness shown in Table 1, the semiconductor A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例２５）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、プリディップ（商品名：ＳＳＰ−７００Ｐ 四国化成製）、液温＝４０℃にて４０秒間浸漬し、置換銀めっき（商品名：ＳＳＰ−７００Ｍ 四国化成製）、液温＝４０℃にて３０秒間浸漬し、更に２分間水洗して、無電解銀めっき皮膜を０．０３μｍ析出させることにより、端子の銅上に純度１００質量％の無電解銀めっき層を形成する工程を行った。 (Example 25)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, pre-dip (trade name: SSP-700P, manufactured by Shikoku Kasei), immersion for 40 seconds at a liquid temperature of 40 ° C., substitution silver plating (trade name: SSP-700M, manufactured by Shikoku Chemical), liquid temperature = 40 ° C. For 30 seconds, and further washed with water for 2 minutes to deposit 0.03 μm of an electroless silver plating film, thereby forming an electroless silver plating layer having a purity of 100% by mass on the copper of the terminal.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例２６〜３０）
実施例２５に記載の置換銀めっき液への浸漬時間を変化させて表２に示される膜厚を有する無電解銀めっき皮膜を形成したこと以外は実施例２５と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 26 to 30)
For mounting a semiconductor chip in the same manner as in Example 25 except that the immersion time in the replacement silver plating solution described in Example 25 was changed to form an electroless silver plating film having the film thickness shown in Table 2 A substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３１）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社、商品名）に、８５℃で２分間浸漬し、更に２分間水洗して、無電解金めっき皮膜を０．０３μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。 (Example 31)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it is immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name), which is a displacement gold plating solution, at 85 ° C. for 2 minutes and further washed with water for 2 minutes to deposit 0.03 μm of electroless gold plating film. Thus, a step of forming an electroless gold layer having a purity of 100% by mass on copper of the terminal was performed.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３２）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社、商品名）に、８５℃で２分間浸漬した。次いで、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）に、７０℃で２分間浸漬させ、更に５分間水洗して、無電解金めっき皮膜を０．０５μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。 (Example 32)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name), which is a displacement gold plating solution, at 85 ° C. for 2 minutes. Then, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a reduced type gold plating solution at 70 ° C. for 2 minutes, and further washed with water for 5 minutes to form an electroless gold plating film of 0.05 μm. A step of forming an electroless gold layer having a purity of 100% by mass on the copper of the terminal was performed by precipitation.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３３〜３６）
実施例３２に記載の還元型の金めっき液への浸漬時間を変化させて表２に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は実施例３２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 33 to 36)
A semiconductor chip was obtained in the same manner as in Example 32 except that the immersion time in the reduced gold plating solution described in Example 32 was changed to form an electroless gold plating film having the film thickness shown in Table 2. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３７）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の還元型無電解パラジウムめっき液に７０℃で１５秒間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．０３μｍ析出させることにより、端子の銅上に純度約１００質量％の無電解パラジウム層を形成する工程を行った。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社、商品名）に、８５℃で２分間浸漬し、更に２分間水洗して、無電解金めっき皮膜を０．０３μｍ析出させることにより、無電解パラジウムめっき皮膜上に１００質量％の無電解金層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 37)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it is immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and reduced electroless palladium plating solution having the following composition. A step of forming an electroless palladium layer having a purity of about 100% by mass on the copper of the terminal by immersing the substrate in 70 ° C. for 15 seconds and further washing with water for 2 minutes to deposit 0.03 μm of the electroless palladium plating film. went. Subsequently, it is immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name), which is a displacement gold plating solution, at 85 ° C. for 2 minutes and further washed with water for 2 minutes to deposit 0.03 μm of electroless gold plating film. Thus, a step of forming a 100% by mass electroless gold layer on the electroless palladium plating film was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３８）
実施例３７と同様にして無電解金層を形成する工程までを行った後、さらに、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）に、７０℃で２分間浸漬させ、更に５分間水洗して、無電解金めっき皮膜を０．０５μｍ析出させることにより、端子の銅上に１００質量％の無電解金層を形成する工程を行った。 (Example 38)
After performing the process of forming an electroless gold layer in the same manner as in Example 37, it was further applied to HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, at 70 ° C. A step of forming an electroless gold layer of 100% by mass on copper of the terminal was performed by immersing for 2 minutes and further washing with water for 5 minutes to deposit 0.05 μm of an electroless gold plating film.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例３９〜４１）
実施例３８に記載の還元型の金めっき液への浸漬時間を変化させて表２に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は実施例３８と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 39 to 41)
Semiconductor chip in the same manner as in Example 38 except that the immersion time in the reduced gold plating solution described in Example 38 was changed to form an electroless gold plating film having the film thickness shown in Table 2 A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４２）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の還元型無電解パラジウムめっき液に７０℃で１分間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．１μｍ析出させることにより、端子の銅上に純度約１００質量％の無電解パラジウム層を形成する工程を行った。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社、商品名）に、８５℃で２分間浸漬し、更に２分間水洗して、無電解金めっき皮膜を０．０３μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 42)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it is immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and reduced electroless palladium plating solution having the following composition. In which the electroless palladium plating film having a purity of about 100% by mass is formed on the copper of the terminal by depositing the electroless palladium plating film at a temperature of 70 ° C. for 1 minute and then washing with water for 2 minutes. went. Subsequently, it is immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name), which is a displacement gold plating solution, at 85 ° C. for 2 minutes and further washed with water for 2 minutes to deposit 0.03 μm of electroless gold plating film. Thus, a step of forming an electroless gold layer having a purity of 100% by mass on copper of the terminal was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４３）
実施例４２と同様にして無電解金層を形成する工程までを行った後、さらに、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）に、７０℃で２分間浸漬させ、更に５分間水洗して、無電解金めっき皮膜を０．０５μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。 (Example 43)
After performing the process of forming an electroless gold layer in the same manner as in Example 42, it was further applied to HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, at 70 ° C. A step of forming an electroless gold layer having a purity of 100% by mass on copper of the terminal was performed by immersing for 2 minutes and further washing with water for 5 minutes to deposit 0.05 μm of an electroless gold plating film.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４４〜４６）
実施例４３に記載の還元型の金めっき液への浸漬時間を変化させて表２に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は実施例４３と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 44 to 46)
A semiconductor chip was obtained in the same manner as in Example 43, except that the immersion time in the reduced gold plating solution described in Example 43 was changed to form an electroless gold plating film having the film thickness shown in Table 2. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４７）
実施例１の工程（１ａ）〜（１ｉ）を行った後、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に1分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗し、下記組成の還元型無電解パラジウムめっき液に７０℃で２分間浸漬し、更に２分間水洗して、無電解パラジウムめっき皮膜を０．２μｍ析出させることにより、端子の銅上に純度約１００％の無電解パラジウム層を形成する工程を行った。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社、商品名）に、８５℃で２分間浸漬し、更に２分間水洗して、無電解金めっき皮膜を０．０３μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。
塩化パラジウム：０．０１ｍｏｌ／Ｌ
エチレンジアミン：０．０８ｍｏｌ／Ｌ
ギ酸ナトリウム：０．１ｍｏｌ／Ｌ
チオジグリコール酸：１０ｐｐｍ
ｐＨ：８ (Example 47)
After performing the steps (1a) to (1i) of Example 1, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then 100 g / L of ammonium persulfate solution was immersed for 1 minute, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it is immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes, washed with water for 2 minutes, and reduced electroless palladium plating solution having the following composition. A step of forming an electroless palladium layer having a purity of about 100% on the copper of the terminal by immersing the substrate in 70 ° C. for 2 minutes and washing with water for 2 minutes to deposit 0.2 μm of the electroless palladium plating film. It was. Subsequently, it is immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name), which is a displacement gold plating solution, at 85 ° C. for 2 minutes and further washed with water for 2 minutes to deposit 0.03 μm of electroless gold plating film. Thus, a step of forming an electroless gold layer having a purity of 100% by mass on the copper of the terminal was performed.
Palladium chloride: 0.01 mol / L
Ethylenediamine: 0.08 mol / L
Sodium formate: 0.1 mol / L
Thiodiglycolic acid: 10ppm
pH: 8

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４８）
実施例４７と同様にして無電解金層を形成する工程までを行った後、さらに、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）に、７０℃で２分間浸漬させ、更に５分間水洗して、無電解金めっき皮膜を０．１μｍ析出させることにより、端子の銅上に純度１００質量％の無電解金層を形成する工程を行った。 (Example 48)
After performing the process of forming an electroless gold layer in the same manner as in Example 47, it was further applied to HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, at 70 ° C. A step of forming an electroless gold layer having a purity of 100% by mass on copper of the terminal was performed by immersing for 2 minutes and further washing with water for 5 minutes to deposit 0.1 μm of an electroless gold plating film.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（実施例４９〜５０）
実施例４８に記載の還元型の金めっき液への浸漬時間を変化させて表２に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は実施例４８と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、めっき皮膜が形成された箇所と、端子形状の銅と銅ワイヤとが直接接合された箇所とを有していることが確認された。 (Examples 49 to 50)
Semiconductor chip in the same manner as in Example 48 except that the immersion time in the reduced gold plating solution described in Example 48 was changed to form an electroless gold plating film having the film thickness shown in Table 2 A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, it was confirmed that the wire bonding terminal has the location where the plating film was formed, and the location where the terminal-shaped copper and the copper wire were directly joined.

（比較例１）
実施例１に記載の置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）への浸漬時間を２分間に変化させ、無電解パラジウムめっき皮膜の厚みを０．００３μｍとしたこと以外は実施例１と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 1)
The immersion time in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is the substituted palladium plating solution described in Example 1, was changed to 2 minutes, and the thickness of the electroless palladium plating film was 0.003 μm. A semiconductor chip mounting substrate was produced in the same manner as in Example 1 except that. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例２）
実施例２に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて、無電解パラジウムめっき皮膜の厚みを０．４μｍとしたこと以外は実施例２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 2)
For mounting a semiconductor chip in the same manner as in Example 2, except that the immersion time in the reduced electroless palladium plating solution described in Example 2 was changed and the thickness of the electroless palladium plating film was changed to 0.4 μm. A substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例３）
実施例８に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて、無電解パラジウムめっき皮膜の厚みを０．４μｍとしたこと以外は実施例２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 3)
For mounting a semiconductor chip in the same manner as in Example 2, except that the immersion time in the reduced electroless palladium plating solution described in Example 8 was changed and the thickness of the electroless palladium plating film was changed to 0.4 μm. A substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例４）
実施例１３に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて、無電解パラジウムめっき皮膜の厚みを０．３μｍとしたこと以外は実施例２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 4)
For mounting a semiconductor chip in the same manner as in Example 2, except that the immersion time in the reduced electroless palladium plating solution described in Example 13 was changed so that the thickness of the electroless palladium plating film was 0.3 μm. A substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例５〜６）
実施例１７に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例１７と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Examples 5-6)
In the same manner as in Example 17, except that the immersion time in the reduced electroless palladium plating solution described in Example 17 was changed to form an electroless palladium plating film having the film thickness shown in Table 3, the semiconductor A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例７〜９）
実施例２１に記載の還元型無電解パラジウムめっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解パラジウムめっき皮膜を形成したこと以外は実施例２１と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Examples 7-9)
In the same manner as in Example 21, except that the immersion time in the reduced electroless palladium plating solution described in Example 21 was changed to form an electroless palladium plating film having the film thickness shown in Table 3, the semiconductor A chip mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例１０〜１４）
実施例２５に記載の置換銀めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解銀めっき皮膜を形成したこと以外は実施例２５と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Examples 10-14)
For mounting a semiconductor chip in the same manner as in Example 25 except that the immersion time in the replacement silver plating solution described in Example 25 was changed to form an electroless silver plating film having the film thickness shown in Table 3 A substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例１５）
実施例３１に記載の置換金めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は全て実施例３１と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 15)
Mounting a semiconductor chip in the same manner as in Example 31 except that the immersion time in the displacement gold plating solution described in Example 31 was changed to form an electroless gold plating film having the film thickness shown in Table 3 A substrate was prepared. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例１６〜１９）
実施例３２記載の還元型の金めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は全て実施例３２と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Examples 16-19)
A semiconductor chip was obtained in the same manner as in Example 32 except that the immersion time in the reduced gold plating solution described in Example 32 was changed to form an electroless gold plating film having the film thickness shown in Table 3. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例２０）
実施例３８記載の還元型の金めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は全て実施例３８と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 20)
A semiconductor chip was obtained in the same manner as in Example 38 except that the immersion time in the reduced gold plating solution described in Example 38 was changed to form an electroless gold plating film having the film thickness shown in Table 3. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例２１）
実施例４３記載の還元型の金めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は全て実施例４３と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 21)
A semiconductor chip was obtained in the same manner as in Example 43 except that the immersion time in the reduced gold plating solution described in Example 43 was changed to form an electroless gold plating film having a film thickness shown in Table 3. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例２２）
実施例４８記載の還元型の金めっき液への浸漬時間を変化させて表３に示される膜厚を有する無電解金めっき皮膜を形成したこと以外は全て実施例４８と同様にして、半導体チップ搭載用基板を作製した。得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。なお、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。 (Comparative Example 22)
A semiconductor chip was obtained in the same manner as in Example 48 except that the immersion time in the reduced gold plating solution described in Example 48 was changed to form an electroless gold plating film having a film thickness shown in Table 3. A mounting substrate was produced. The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1. In addition, the wire bonding terminal did not have the location where terminal-shaped copper and copper wire were directly joined.

（比較例２３〜２６）
比較例２３〜２６はそれぞれ、実施例４〜７と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。なお、比較例２３の銅ワイヤが接合されたワイヤボンディング端子の表面のＳＥＭ観察結果を図２に示す。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 23 to 26)
In Comparative Examples 23 to 26, substrates prepared in the same manner as in Examples 4 to 7 were used, respectively, and the capillaries used for wire bonding were CuPRAplus (registered trademark) Capillary (manufactured by Kulicke & Soffa, Inc.) with the tip surface “matted”. In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. In addition, the SEM observation result of the surface of the wire bonding terminal with which the copper wire of the comparative example 23 was joined is shown in FIG. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例２７〜３０）
比較例２７〜３０はそれぞれ、実施例２７〜３０と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 27-30)
Comparative Examples 27 to 30 respectively use substrates prepared in the same manner as in Examples 27 to 30, and the capillaries used for wire bonding are CuPRAplus (registered trademark) Capillary (manufactured by Kulicke & Soffa, Inc.) whose tip surface is “matted” In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例３１〜３４）
比較例３１〜３４はそれぞれ、実施例３３〜３６と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 31-34)
In Comparative Examples 31 to 34, substrates prepared in the same manner as in Examples 33 to 36 were used, respectively, and the capillaries used for wire bonding were CuPRAplus (registered trademark) Capillary (manufactured by Kulicke & Soffa Corp.) with the tip surface being “matted”. In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例３５〜３７）
比較例３５〜３７はそれぞれ、実施例３８〜４０と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 35-37)
In Comparative Examples 35 to 37, substrates prepared in the same manner as in Examples 38 to 40 were used, respectively, and the capillaries used for wire bonding were CuPRAplus (registered trademark) Capillary (manufactured by Kulikke & Soffa, Inc.) with the tip surface being “matted” In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例３８〜３９）
比較例３８〜３９はそれぞれ、実施例４３〜４４と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 38-39)
In Comparative Examples 38 to 39, substrates prepared in the same manner as in Examples 43 to 44 were used, respectively, and the capillaries used for wire bonding were CuPRAplus (registered trademark) Capillary (manufactured by Kulicke & Soffa, Inc.) with the tip surface “matted” In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例４０〜４１）
比較例４０〜４１はそれぞれ、実施例４７〜４８と同様にして作製した基板をそれぞれ用い、ワイヤボンディングに用いたキャピラリーを、先端面を「マット加工」したＣｕＰＲＡｐｌｕｓ（登録商標） Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）の代わりに、先端面を「ポリッシュ加工」したＣＩＣ Ｃａｐｉｌｌａｒｙ（Ｋｕｌｉｃｋｅ＆Ｓｏｆｆａ社製、商品名）を用いてワイヤボンディングを行った。しかし、ワイヤボンディング端子は、端子形状の銅と銅ワイヤとが直接接合された箇所を有していなかった。ワイヤボンディング性以外については実施例１と同様に特性評価を行った。 (Comparative Examples 40-41)
In Comparative Examples 40 to 41, substrates prepared in the same manner as in Examples 47 to 48 were used, respectively, and the capillaries used for wire bonding were CuPRAplus (registered trademark) Capillary (manufactured by Kulicke & Soffa, Inc.) whose tip surface was “matted” In place of (trade name), wire bonding was performed using CIC Capillary (trade name, manufactured by Kulicke & Soffa) whose tip surface was “polished”. However, the wire bonding terminal does not have a portion where the terminal-shaped copper and the copper wire are directly bonded. Except for wire bonding properties, the characteristics were evaluated in the same manner as in Example 1.

（比較例４２）
実施例１に示した工程（１ａ）〜（１ｉ）を行った。ソルダーレジスト形成後の基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、置換パラジウムめっき液であるＳＡ−１００（日立化成工業株式会社製、商品名）に、２５℃で５分間、浸漬処理し、２分間水洗した。続いて、下記組成の処理液に浸漬した後、水洗乾燥した。
チオ硫酸カリウム：５０ｇ／Ｌ
ｐＨ：６
ｐＨ調整剤：クエン酸ナトリウム (Comparative Example 42)
The steps (1a) to (1i) shown in Example 1 were performed. The board | substrate after solder resist formation is immersed in degreasing liquid Z-200 (the World Metal Co., Ltd. make, brand name) for 3 minutes at 50 degreeC, and it rinses with water for 2 minutes, Then, it is 1 minute to a 100 g / L ammonium persulfate solution for 1 minute. Immersion was performed, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, it was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution, at 25 ° C. for 5 minutes and washed with water for 2 minutes. Subsequently, it was immersed in a treatment solution having the following composition, and then washed with water and dried.
Potassium thiosulfate: 50 g / L
pH: 6
pH adjuster: sodium citrate

続いて、無電解ニッケルめっき液であるニッケルＰＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で８分間、浸漬処理し、１分間水洗した。こうして、２μｍの無電解ニッケルめっき皮膜を得た。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で１０分間、浸漬処理し１分間水洗した。さらに、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）へ、７０℃において２５分間浸漬させ、５分間水洗した。このとき、置換金めっき及び還元型の金めっき皮膜の膜厚の合計は０．３μｍであった。   Subsequently, it was immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 8 minutes and washed with water for 1 minute. Thus, a 2 μm electroless nickel plating film was obtained. Subsequently, it was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating solution, at 85 ° C. for 10 minutes and washed with water for 1 minute. Further, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, for 25 minutes at 70 ° C. and washed with water for 5 minutes. At this time, the total thickness of the displacement gold plating and the reduction-type gold plating film was 0.3 μm.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1.

（比較例４３）
実施例１に示した工程（１ａ）〜（１ｉ）を行った。ソルダーレジスト形成後の基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／Ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗した。続いて、めっき活性化処理液である下記組成の置換パラジウムめっき液に、５分間浸漬後、水洗、乾燥した。
塩酸（３５%）：７０ｍｌ／Ｌ
塩化パラジウム（Ｐｄ）として：５０ｍｇ／Ｌ
次亜リン酸：１００ｍｇ／Ｌ
酸性度：約０．８Ｎ (Comparative Example 43)
The steps (1a) to (1i) shown in Example 1 were performed. The board | substrate after solder resist formation is immersed in degreasing liquid Z-200 (the World Metal Co., Ltd. make, brand name) for 3 minutes at 50 degreeC, and it rinses with water for 2 minutes, Then, it is 1 minute to a 100 g / L ammonium persulfate solution for 1 minute. Immersion was performed, washed with water for 2 minutes, immersed in 10% sulfuric acid for 1 minute, and washed with water for 2 minutes. Subsequently, after being immersed in a substituted palladium plating solution having the following composition, which is a plating activation treatment solution, washed with water and dried.
Hydrochloric acid (35%): 70 ml / L
As palladium chloride (Pd): 50 mg / L
Hypophosphorous acid: 100 mg / L
Acidity: about 0.8N

続いて、無電解ニッケルめっき液であるニッケルＰＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で８分間、浸漬処理し、１分間水洗した。なお、２μｍの無電解ニッケルめっき皮膜を得た。続いて、置換金めっき液であるＨＧＳ−１００（日立化成工業株式会社製、商品名）に、８５℃で１０分間、浸漬処理し１分間水洗した。さらに、還元型の金めっき液であるＨＧＳ−２０００（日立化成工業株式会社製、商品名）へ、７０℃において２５分間浸漬させ、５分間水洗した。このとき、置換金めっき及び還元型の金めっき皮膜の膜厚の合計は０．３μｍであった。   Subsequently, it was immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 8 minutes and washed with water for 1 minute. A 2 μm electroless nickel plating film was obtained. Subsequently, it was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating solution, at 85 ° C. for 10 minutes and washed with water for 1 minute. Further, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, for 25 minutes at 70 ° C. and washed with water for 5 minutes. At this time, the total thickness of the displacement gold plating and the reduction-type gold plating film was 0.3 μm.

得られた半導体チップ搭載用基板について、実施例１と同様に特性評価を行った。   The obtained semiconductor chip mounting substrate was evaluated for characteristics in the same manner as in Example 1.






Claims (4)

端子形状の銅の表面にめっき皮膜が形成されたワイヤボンディング端子を有する半導体チップ搭載用基板と、前記ワイヤボンディング端子に接合された銅ワイヤで電気的に接続された半導体チップと、を備え、
前記ワイヤボンディング端子は、前記めっき皮膜が形成された箇所と、前記端子形状の銅と前記銅ワイヤとが直接接合された箇所とを有し、
前記端子形状の銅と前記銅ワイヤとが直接接合されている箇所の前記銅ワイヤの表面の十点平均粗さが０．１５〜１．０μｍの範囲であり、
前記めっき皮膜が、下記（１）、（２−１）〜（２−４）、（３）又は（４）のいずれかのめっき皮膜である、半導体パッケージ。
（１）厚さが０．０３〜０．４μｍの銀めっき皮膜
（２−１）厚さが０．００５〜０．３５μｍであり、純度が９９％以上のパラジウムめっき皮膜
（２−２）厚さが０．００５〜０．２５μｍであり、純度が９８％以上のパラジウムめっき皮膜
（２−３）厚さが０．００５〜０．１５μｍであり、純度が９７％以上のパラジウムめっき皮膜
（２−４）厚さが０．００５〜０．１２μｍであり、純度が９４％以上のパラジウムめっき皮膜
（３）厚さが０．０３〜０．４μｍの金めっき皮膜
（４）厚さが０．００３〜０．２μｍのパラジウムめっき皮膜と厚さが０．０３〜０．２μｍの金めっき皮膜との２層めっき皮膜 A semiconductor chip mounting substrate having a wire bonding terminal in which a plating film is formed on the surface of the terminal-shaped copper, and a semiconductor chip electrically connected by a copper wire bonded to the wire bonding terminal,
The wire bonding terminal has a place where the plating film is formed and a place where the terminal-shaped copper and the copper wire are directly joined,
The ten-point average roughness of the surface of the copper wire where the terminal-shaped copper and the copper wire are directly bonded is in the range of 0.15 to 1.0 μm,
The semiconductor package whose said plating film is a plating film in any one of following (1), (2-1)-(2-4), (3) or (4).
(1) Silver plating film having a thickness of 0.03 to 0.4 μm (2-1) Palladium plating film (2-2) having a thickness of 0.005 to 0.35 μm and a purity of 99% or more Palladium plating film (2-3) having a thickness of 0.005 to 0.25 μm and a purity of 98% or more Palladium plating film (2-3) having a thickness of 0.005 to 0.15 μm and a purity of 97% or more -4) A palladium plating film having a thickness of 0.005 to 0.12 μm and a purity of 94% or more (3) A gold plating film having a thickness of 0.03 to 0.4 μm (4) A thickness of 0.004. Two-layer plating film of 003-0.2 μm palladium plating film and 0.03-0.2 μm gold plating film 前記めっき皮膜の純度が９９％以上である、請求項１に記載の半導体パッケージ。   The semiconductor package of Claim 1 whose purity of the said plating film is 99% or more. 基板、及び該基板上に設けられ、端子形状の銅の表面にめっき皮膜が形成されたワイヤボンディング端子を備える半導体チップ搭載用基板と、前記ワイヤボンディング端子に接合された銅ワイヤで電気的に接続された半導体チップと、を備える半導体パッケージの製造方法であって、
先端面がマット加工されたキャピラリーにより前記ワイヤボンディング端子に前記銅ワイヤを接合して、前記ワイヤボンディング端子の一部に前記端子形状の銅と前記銅ワイヤとが直接接合する箇所を設ける工程を備え、
前記めっき皮膜が、下記（１）、（２−１）〜（２−４）、（３）又は（４）のいずれかのめっき皮膜である、半導体パッケージの製造方法。
（１）厚さが０．０３〜０．４μｍの銀めっき皮膜
（２−１）厚さが０．００５〜０．３５μｍであり、純度が９９％以上のパラジウムめっき皮膜
（２−２）厚さが０．００５〜０．２５μｍであり、純度が９８％以上のパラジウムめっき皮膜
（２−３）厚さが０．００５〜０．１５μｍであり、純度が９７％以上のパラジウムめっき皮膜
（２−４）厚さが０．００５〜０．１２μｍであり、純度が９４％以上のパラジウムめっき皮膜
（３）厚さが０．０３〜０．４μｍの金めっき皮膜
（４）厚さが０．００３〜０．２μｍのパラジウムめっき皮膜と厚さが０．０３〜０．２μｍの金めっき皮膜との２層めっき皮膜 Electrical connection between a substrate and a semiconductor chip mounting substrate provided on the substrate and provided with a wire bonding terminal having a plating film formed on the surface of a terminal-shaped copper, and a copper wire bonded to the wire bonding terminal A semiconductor package comprising: a manufactured semiconductor chip, comprising:
A step of joining the copper wire to the wire bonding terminal with a capillary having a matted tip surface, and providing a portion where the terminal-shaped copper and the copper wire are directly joined to a part of the wire bonding terminal; ,
The method for manufacturing a semiconductor package, wherein the plating film is any one of the following (1), (2-1) to (2-4), (3), or (4).
(1) Silver plating film having a thickness of 0.03 to 0.4 μm (2-1) Palladium plating film (2-2) having a thickness of 0.005 to 0.35 μm and a purity of 99% or more Palladium plating film (2-3) having a thickness of 0.005 to 0.25 μm and a purity of 98% or more Palladium plating film (2-3) having a thickness of 0.005 to 0.15 μm and a purity of 97% or more -4) A palladium plating film having a thickness of 0.005 to 0.12 μm and a purity of 94% or more (3) A gold plating film having a thickness of 0.03 to 0.4 μm (4) A thickness of 0.004. Two-layer plating film of 003-0.2 μm palladium plating film and 0.03-0.2 μm gold plating film 前記めっき皮膜の純度が９９％以上である、請求項３に記載の半導体パッケージの製造方法。   The manufacturing method of the semiconductor package of Claim 3 whose purity of the said plating film is 99% or more.
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