JP5877121B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP5877121B2 JP5877121B2 JP2012113557A JP2012113557A JP5877121B2 JP 5877121 B2 JP5877121 B2 JP 5877121B2 JP 2012113557 A JP2012113557 A JP 2012113557A JP 2012113557 A JP2012113557 A JP 2012113557A JP 5877121 B2 JP5877121 B2 JP 5877121B2
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- 125000005843 halogen group Chemical group 0.000 description 1
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- 239000011261 inert gas Substances 0.000 description 1
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- 229910052747 lanthanoid Inorganic materials 0.000 description 1
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- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
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- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical class [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
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- 229910052724 xenon Inorganic materials 0.000 description 1
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- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Description
<記憶装置の構成>
図1に本実施の形態の記憶装置のブロック図を示す。図1に示す記憶装置100は、比較器201、メモリ部202、メモリ部203、出力電位確定器204を有している。
図6に、本実施の形態の記憶装置100を駆動するためのタイミングチャートを示す。
まず図6の期間T1では、クロック信号CLKがローレベル電位(VSS)、信号CLKBがハイレベル電位(VDD)、入力信号Aがハイレベル電位(VDD)、入力信号Aと位相が反転した信号ABはローレベル電位(VSS)である。なお本実施の形態の記憶装置100では、電源電位Vxは常にハイレベル電位(VDD)であり、低電位基準電位はローレベル電位(VSS)、例えば接地電位GNDである。
期間T2では、クロック信号CLKがハイレベル電位(VDD)、信号CLKBがローレベル電位(VSS)となる。
期間T3では、クロック信号CLK及び信号CLKBは、それぞれローレベル電位(VSS)及びハイレベル電位(VDD)であり、期間T1と同様である。ただし期間T3では、入力信号A及び信号ABがローレベル電位(VSS)及びハイレベル電位(VDD)であり、入力信号A及び信号ABは期間T1とは逆の位相となっている。
期間T4では、クロック信号CLKがハイレベル電位(VDD)、信号CLKBがローレベル電位(VSS)となり、期間T2と同様である。ただし期間T3の終わりにおいて、ノードM1及びノードM2は、それぞれローレベル電位(VSS)及びハイレベル電位(VDD)となっている。
<記憶装置の構成>
本実施の形態では、実施の形態1とは異なる構成の記憶装置について説明する。
図14に、本実施の形態の記憶装置250を駆動するためのタイミングチャートを示す。
まず図14の期間T1では、クロック信号CLKがハイレベル電位(VDD)、入力信号Aがハイレベル電位(VDD)、入力信号Aと位相が反転した信号ABはローレベル電位(VSS)である。なお本実施の形態の記憶装置250では、高電位基準電位である電源電位Vxは常にハイレベル電位(VDD)であり、低電位基準電位は、ローレベル電位(VSS)、例えば接地電位GNDである。
期間T2では、クロック信号CLKがローレベル電位(VSS)となる。
期間T3では、クロック信号CLKハイレベル電位(VDD)であり、期間T1と同様である。ただし期間T3では、入力信号A及び信号ABがローレベル電位(VSS)及びハイレベル電位(VDD)であり、入力信号A及び信号ABは期間T1とは逆の位相となっている。
期間T4では、クロック信号CLKがローレベル電位(VSS)となり、期間T2と同様である。ただし期間T3の終わりにおいて、ノードM3及びノードM4は、それぞれローレベル電位(VSS)及びハイレベル電位(VDD)となっている。
本実施の形態では、酸化物半導体トランジスタについて説明する。
本実施の形態では、記憶装置の構造の一形態について説明する。
本実施の形態では、開示される発明の一態様に係る信号処理回路の一つである、CPU(Central Processing Unit(中央処理装置、又は中央演算処理装置))の構成について説明する。
本実施の形態では、開示される発明の一様態で用いられる酸化物半導体トランジスタについて詳細に説明する。なお本実施の形態の酸化物半導体トランジスタは、実施の形態3で説明した酸化物半導体トランジスタに援用可能である。
線形領域におけるドレイン電流Idは、以下の式で表現できる。
101 トランジスタ
102 トランジスタ
111 トランジスタ
112 トランジスタ
113 トランジスタ
114 トランジスタ
115 トランジスタ
116 トランジスタ
117 トランジスタ
120 ラッチ回路
121 クロックドインバータ
122 インバータ
123 クロックドインバータ
130 インバータ
131 トランジスタ
132 トランジスタ
140 クロックドインバータ
140A クロックドインバータ
140B クロックドインバータ
141 トランジスタ
142 トランジスタ
143 トランジスタ
144 トランジスタ
161 保持容量
162 保持容量
201 比較器
202 メモリ部
203 メモリ部
204 出力電位確定器
211 トランジスタ
212 トランジスタ
213 トランジスタ
214 トランジスタ
215 トランジスタ
216 トランジスタ
217 トランジスタ
221 トランジスタ
222 トランジスタ
250 記憶装置
251 比較器
252 メモリ部
253 メモリ部
254 出力電位確定器
261 保持容量
262 保持容量
501 下地絶縁膜
502 埋め込み絶縁物
503a 半導体領域
503b 半導体領域
503c 半導体領域
504 ゲート絶縁膜
505 ゲート電極
506a 側壁絶縁膜
506b 側壁絶縁膜
507 絶縁膜
508a ソース領域
508b ドレイン領域
550 基板
552 下地絶縁膜
554 保護絶縁膜
556 酸化物半導体膜
556a 高抵抗領域
556b 低抵抗領域
558 ゲート絶縁膜
560 ゲート電極
562 側壁絶縁膜
564 電極
566 層間絶縁膜
568 配線
600 基板
602 下地絶縁膜
606 酸化物半導体膜
608 ゲート絶縁膜
610 ゲート電極
614 電極
616 層間絶縁膜
618 配線
620 保護膜
901 酸化物半導体トランジスタ
902 絶縁膜
903 酸化物半導体層
904 ソース電極
905 ドレイン電極
906 ゲート絶縁膜
907 ゲート電極
908 高濃度領域
909 チャネル形成領域
911 酸化物半導体トランジスタ
912 絶縁膜
913 酸化物半導体層
914 ソース電極
915 ドレイン電極
916 ゲート絶縁膜
917 ゲート電極
918 高濃度領域
919 チャネル形成領域
3000 基板
3001 トランジスタ
3003a 電極
3003b 電極
3003c 電極
3004 論理回路
3100a 配線
3100b 配線
3100c 配線
3100d 配線
3106 素子分離絶縁膜
3140a 絶縁膜
3140b 絶縁膜
3141a 絶縁膜
3141b 絶縁膜
3142a 絶縁膜
3142b 絶縁膜
3170a 記憶素子
3170b 記憶素子
3171a トランジスタ
3171b トランジスタ
3303 電極
3501a 電極
3501b 電極
3501c 電極
3502a 電極
3502b 電極
3502c 電極
3503a 電極
3503b 電極
3505 電極
9900 基板
9901 ALU
9902 ALU・Controller
9903 Instruction・Decoder
9904 Interrupt・Controller
9905 Timing・Controller
9906 Register
9907 Register・Controller
9908 Bus・I/F
9909 ROM
9920 ROM・I/F
Claims (11)
- 高電位基準電位と接続され、第1の出力信号及び第2の出力信号の電位を比較する比較器と、
酸化物半導体層にチャネル形成領域が形成される第1の酸化物半導体トランジスタ及びシリコン層にチャネル形成領域が形成される第1のシリコントランジスタを有する第1のメモリ部と、
第2の酸化物半導体トランジスタ及び第2のシリコントランジスタを有する第2のメモリ部と、
低電位基準電位と接続され、前記第1の出力信号及び前記第2の出力信号の電位を確定する出力電位確定器と、を有し、
前記第1の酸化物半導体トランジスタのソース又はドレインの一方は、前記第1のシリコントランジスタのゲートに電気的に接続されており、
前記第2の酸化物半導体トランジスタのソース又はドレインの一方は、前記第2のシリコントランジスタのゲートに電気的に接続されており、
前記第1の出力信号は前記比較器及び前記第1のメモリ部から出力され、
前記第2の出力信号は前記比較器及び前記第2のメモリ部から出力されることを特徴とする半導体集積回路。 - 請求項1において、
前記第1のシリコントランジスタ及び前記第2のシリコントランジスタは、nチャネル型トランジスタであることを特徴とする半導体集積回路。 - 請求項1または請求項2において、
前記第1の酸化物半導体トランジスタのソース又はドレインの一方及び前記第1のシリコントランジスタのゲートと接続する第1の保持容量、及び、前記第2の酸化物半導体トランジスタのソース又はドレインの一方及び前記第2のシリコントランジスタのゲートと接続する第2の保持容量が設けられていることを特徴とする半導体集積回路。 - 請求項1乃至請求項3のいずれか一項において、
前記第1の酸化物半導体トランジスタ及び前記第2の酸化物半導体トランジスタは、前記第1のシリコントランジスタ及び前記第2のシリコントランジスタに重畳して形成されることを特徴とする半導体集積回路。 - 高電位基準電位と接続され、第1の出力信号及び第2の出力信号の電位を比較する比較器と、
酸化物半導体層にチャネル形成領域が形成される第1の酸化物半導体トランジスタ及び第2の酸化物半導体トランジスタを有する第1のメモリ部と、
第3の酸化物半導体トランジスタ及び第4の酸化物半導体トランジスタを有する第2のメモリ部と、
低電位基準電位と接続され、前記第1の出力信号及び前記第2の出力信号の電位を確定する出力電位確定器と、を有し、
前記第1の酸化物半導体トランジスタのソース又はドレインの一方は、前記第2の酸化物半導体トランジスタのゲートに電気的に接続されており、
前記第3の酸化物半導体トランジスタのソース又はドレインの一方は、前記第4の酸化物半導体トランジスタのゲートに電気的に接続されており、
前記第1の出力信号は前記比較器及び前記第1のメモリ部から出力され、
前記第2の出力信号は前記比較器及び前記第2のメモリ部から出力されることを特徴とする半導体集積回路。 - 請求項5において、
前記第1の酸化物半導体トランジスタのソース又はドレインの一方及び前記第2の酸化物半導体トランジスタのゲートと接続する第1の保持容量、及び、前記第3の酸化物半導体トランジスタのソース又はドレインの一方及び前記第4の酸化物半導体トランジスタのゲートと接続する第2の保持容量が設けられていることを特徴とする半導体集積回路。 - 請求項1乃至請求項6のいずれか一項において、
前記比較器は、4つのトランジスタを有することを特徴とする半導体集積回路。 - 請求項7において、
前記比較器のトランジスタのそれぞれは、pチャネル型シリコントランジスタであることを特徴とする半導体集積回路。 - 請求項1乃至請求項8のいずれか一項において、
前記出力電位確定器は、1つのトランジスタを有することを特徴とする半導体集積回路。 - 請求項9において、
前記出力電位確定器のトランジスタは、nチャネル型シリコントランジスタであることを特徴とする半導体集積回路。 - 請求項9において、
前記出力電位確定器のトランジスタは、酸化物半導体トランジスタであることを特徴とする半導体集積回路。
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JP2016136725A (ja) | 2016-07-28 |
US20120292680A1 (en) | 2012-11-22 |
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TW201308901A (zh) | 2013-02-16 |
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