JP5795260B2 - 段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ - Google Patents
段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ Download PDFInfo
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Description
Claims (9)
- 第1のゲート電極構造の側壁上に形成された第1の側壁スペーサによって前記第1のゲート電極構造からオフセットされ、第1の深さまで延びる第1の複数の凹部を第1の結晶性半導体領域内に形成することであって、前記第1のゲート電極構造の上方および第2の結晶性半導体領域上に形成された第2のゲート電極構造の上方に第1のスペーサ層を形成し、前記第2のゲート電極構造及び前記第2の結晶性半導体領域の上方に形成された前記第1のスペーサ層を覆うために第1のマスクを形成し、前記第1のスペーサ層から前記第1の側壁スペーサを形成し、前記第1の側壁スペーサ及び前記第1のマスクの存在下で前記第1の結晶性半導体領域から材質を除去することを含む、ことと、
前記第1の側壁スペーサ上に形成された第2の側壁スペーサによって前記第1のゲート電極構造からオフセットされ、前記第1の深さよりも深い第2の深さまで延びる第2の複数の凹部を第1の結晶性半導体領域内に形成することであって、前記第1のマスクを除去し、第2のスペーサ層を堆積させ、前記第2のゲート電極構造の上方及び前記第2の結晶性半導体領域の上方に第2のマスクを形成し、前記第2のマスクの存在下で前記第2のスペーサ層から前記第2の側壁スペーサを形成することを含む、ことと、
を備えた方法。 - 選択的なエピタキシャル成長処理を実行することによって、前記第1の凹部及び前記第2の凹部に歪誘起半導体合金を形成することを含む請求項1の方法。
- 前記歪誘起半導体合金を形成することは、前記第1の側壁スペーサの存在下で前記第1の複数の凹部を前記歪誘起半導体合金の第1の部分で充填し、且つ、前記第1の側壁スペーサ及び前記第2の側壁スペーサの存在下で前記第2の複数の凹部の一部を前記歪誘起半導体合金の第2の部分で充填するように、第1のエピタキシャル成長プロセスを実行することを含む、請求項2の方法。
- 前記歪誘起半導体合金の前記第1の部分と前記第2の部分とは、少なくともインサイツドーピングの程度が異なる、請求項3の方法。
- 前記歪誘起半導体合金は錫を含む、請求項2の方法。
- 前記第1の複数の凹部及び前記第2の複数の凹部を形成することは、前記第2の複数の凹部の第1の部分を形成することと、前記第2の側壁スペーサの少なくとも一部を除去することと、前記第2の複数の凹部の第2の部分と前記第1の複数の凹部とを共通して形成することと、を含む、請求項1の方法。
- 前記第1の側壁スペーサは二酸化シリコンから構成されており、前記第2の側壁スペーサはシリコン窒化物から構成されている、請求項1の方法。
- 前記第1の深さ及び前記第2の深さよりも浅い第3の深さを有する第3の複数の凹部であって、前記第1の複数の凹部又は前記第2の複数の凹部のオフセットよりも小さなオフセットによって前記ゲート電極構造からオフセットされている第3の複数の凹部を形成することを備えた請求項1の方法。
- 前記第1の複数の凹部、前記第2の複数の凹部及び前記第3の複数の凹部を半導体合金で充填することを備えた請求項8の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008063427.1 | 2008-12-31 | ||
DE102008063427A DE102008063427B4 (de) | 2008-12-31 | 2008-12-31 | Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung |
US12/640,765 US8202777B2 (en) | 2008-12-31 | 2009-12-17 | Transistor with an embedded strain-inducing material having a gradually shaped configuration |
US12/640,765 | 2009-12-17 | ||
PCT/EP2009/009306 WO2010076017A1 (en) | 2008-12-31 | 2009-12-29 | A transistor with an embedded strain inducing material having a gradually shaped configuration |
Publications (3)
Publication Number | Publication Date |
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JP2012514317A JP2012514317A (ja) | 2012-06-21 |
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