JP5758296B2 - 積層素子における信号送出 - Google Patents
積層素子における信号送出 Download PDFInfo
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- JP5758296B2 JP5758296B2 JP2011526974A JP2011526974A JP5758296B2 JP 5758296 B2 JP5758296 B2 JP 5758296B2 JP 2011526974 A JP2011526974 A JP 2011526974A JP 2011526974 A JP2011526974 A JP 2011526974A JP 5758296 B2 JP5758296 B2 JP 5758296B2
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- 238000000034 method Methods 0.000 claims description 29
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/5317—Laminated device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
この特許出願は、参照により本明細書に組み込まれる2008年9月11日出願の米国特許出願番号12/209,052の利益を享受する優先権主張出願である。
Claims (40)
- 装置であって、
複数の信号を受け取るように構成されたベースと、
第1のダイであって、該第1のダイは、該第1のダイを少なくとも部分的に通る導電性パスを含み、該第1のダイは前記装置のデバイス内に含まれており、該デバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されており、前記第1のダイは、前記ダイの第1および第2の積層のうちの一方に含まれている、第1のダイと、
前記第1のダイ及び前記ベースと共に積層をなすように配列された第2のダイと、
前記積層内であって且つ前記第1及び第2のダイのうちの少なくとも一方の外部に設置され、且つ、前記ベースと前記第1及び第2のダイのうちの少なくとも一方との間で前記信号の少なくとも1つのサブセットを伝達するように構成された構造体と、
を含む装置。 - 前記第1のダイは前記ベースと前記第2のダイとの間に設置され、前記構造体は第1の構造体部分と第2の構造体部分とを含み、前記第1の構造体部分は前記ベースと前記第2のダイとの間であって且つ前記第1のダイの第1の側に設置され、また、前記第2の構造体部分は前記ベースと前記第2のダイとの間であって且つ前記第1のダイの第2の側に設置されている、請求項1に記載の装置。
- 前記構造体は、前記第1のダイと前記第2のダイとの間に設置されたインターポーザを含み、前記インターポーザは前記第1のダイと前記第2のダイとに結合された導電性パスを含む、請求項1に記載の装置。
- 前記構造体は、前記第2のダイに結合された導電性パスを有する一部分を含み、前記第1のダイ及び前記第2のダイは前記ベースと前記一部分との間に設置されている、請求項1に記載の装置。
- 前記ベースは、有機材料を有する基板と、該有機材料を通る導電性パスとを含む、請求項1に記載の装置。
- 前記ベースは、信号のフィルタリングを行うための回路要素を含む、請求項1に記載の装置。
- 信号を受け取るように構成されたベースと、
第1のデバイスであって、該第1のデバイスは、該第1のデバイスを少なくとも部分的に通る第1の導電性パスを含み、該第1のデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、第1のデバイスと、
第2のデバイスと、
前記ベース、前記第1のデバイス、及び前記第2のデバイスと共に積層をなすように設置されたインターポーザと、
を含み、
前記インターポーザは、前記第1及び第2のデバイス間に設置され、かつ、前記信号の少なくとも1つのサブセットを前記第1及び第2のデバイスのうちの一方に伝達するように構成され、
前記インターポーザは、第1の表面と、該第1の表面に相対する第2の表面と、前記第1の表面に設置されかつ前記第1のデバイスに結合された第1の導電性接点と、前記第2の表面に設置されかつ前記第2のデバイスに結合された第2の導電性接点と、前記第1の導電性接点を前記第2の導電性接点に結合する第2の導電性パスとを含む、装置。 - 第1の構造体部分と第2の構造体部分とをさらに含み、前記第1の構造体部分は、前記第1のデバイスの第1の側に設置され、かつ、前記ベースと前記インターポーザとに結合された導電性パスを含み、前記第2の構造体部分は、前記第1のデバイスの第2の側に設置され、かつ、前記ベースと前記インターポーザとに結合された導電性パスを含む、請求項7に記載の装置。
- 前記ダイの第1の積層と前記ダイの第2の積層との間に設置された第3の構造体部分をさらに含み、前記第3の構造体部分は、前記ベースと前記インターポーザとに結合された導電性パスを含む、請求項8に記載の装置。
- 前記第1、第2及び第3の構造体部分のうちの少なくとも1つは、前記ダイの第1及び第2の積層のうちの少なくとも一方におけるダイに組み込まれている、請求項9に記載の装置。
- 前記インターポーザは該インターポーザの両端間の長さを有し、前記インターポーザの前記長さは前記第1のデバイスの長さより長い、請求項7に記載の装置。
- 前記インターポーザは、前記第1の表面から前記第2の表面に伸びるビアを含み、前記第2の導電性パスのうちの1つの少なくとも一部が前記ビアを通って伸びる、請求項7に記載の装置。
- 前記インターポーザは多数の層を含み、該多数の層のそれぞれは、前記信号の異なるサブセットを伝達するために第2の導電性パスのうちの少なくとも1つに結合された少なくとも1つの導電性部分を含む、請求項7に記載の装置。
- 前記インターポーザは、正の値を有する第1の電力信号を伝達するために前記第2の導電性パスのうちの第1の選択された導電性パスに結合された第1の導電性部分と、接地電位を有する第2の電力信号を伝達するために前記第2の導電性パスのうちの第2の選択された導電性パスに結合された第2の導電性部分とを含み、前記第1及び第2の導電性部分のうちの少なくとも一方は前記第1及び第2の選択された導電性パスに垂直な次元に伸びる、請求項7に記載の装置。
- 前記第1の選択された導電性パスは、前記インターポーザを部分的にのみ通って伸びるビアを通り抜ける、請求項14に記載の装置。
- 前記第2の選択された導電性パスは、前記インターポーザを部分的にのみ通って伸びる追加のビアを通り抜ける、請求項15に記載の装置。
- 前記第1のデバイスは、データ信号を伝達するために前記第1の導電性パスのうちの選択された導電性パスに結合された導電性のセグメントを含み、該導電性のセグメントは前記選択された導電性パスに垂直な次元に伸びる、請求項16に記載の装置。
- 信号を受け取るように構成されたベースと、
第1のデバイスであって、該第1のデバイスは、該第1のデバイスを少なくとも部分的に通る第1の導電性パスを含み、該第1のデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、第1のデバイスと、
前記ベース及び前記第1のデバイスと共に積層をなすように配列された第2のデバイスであって、前記第1のデバイスが前記ベースと前記第2のデバイスとの間に設置され、前記第1のデバイスが前記第2のデバイスより短い長さを有する、第2のデバイスと、
前記第2のデバイスに前記信号の少なくとも1つのサブセットを伝達するように構成された構造体であって、該構造体が、前記第1のデバイスの第1の側に設置された第1の構造体部分と、前記第1のデバイスの第2の側に設置された第2の構造体部分とを含み、前記第1及び第2の構造体部分のそれぞれが、第1の表面と、該第1の表面に相対する第2の表面と、前記第1の表面に設置されかつ前記ベースに結合された第1の導電性接点と、前記第2の表面に設置されかつ前記第2のデバイスに結合された第2の導電性接点と、前記第1の導電性接点を前記第2の導電性接点に結合する第2の導電性パスとを備える、構造体と、
を含む装置。 - 前記第1の構造体部分は、該第1の構造体部分の第1の表面から第2の表面に伸びる第1のビアと、該第1のビアを通って伸びる前記第2の導電性パスのうちの1つの少なくとも一部とを含み、また、前記第2の構造体部分は、該第2の構造体部分の第1の表面から第2の表面に伸びる第2のビアと、該第2のビアを通って伸びる前記第2の導電性パスのうちの1つの少なくとも一部とを含む、請求項18に記載の装置。
- 前記構造体の高さは前記第1のデバイスの高さに等しい、請求項18に記載の装置。
- 前記構造体は、前記ダイの第1の積層と前記ダイの第2の積層との間に設置された第3の構造体部分をさらに含み、該第3の構造体部分は前記ベースと前記第2のデバイスとに結合された導電性パスを含む、請求項18に記載の装置。
- 信号を受け取るように構成されたベースと、
第1のデバイスであって、該第1のデバイスは、該第1のデバイスを少なくとも部分的に通る導電性パスを含み、該第1のデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、第1のデバイスと、
第1の表面、該第1の表面に相対する第2の表面、前記第1の表面に設置されかつ前記第1のデバイスに結合された第1の導電性接点、及び前記第2の表面に設置された第2の導電性接点を含む第2のデバイスと、
前記第2のデバイスに前記信号の少なくとも1つのサブセットを伝達するように構成された導電性パスを含む構造体であって、該構造体が、前記ベース、前記第1のデバイス及び前記第2のデバイスと共に積層をなすように配列された第1の構造体部分を含み、前記第1及び第2のデバイスは前記ベースと前記第1の構造体部分との間にある、構造体と、
を含む装置。 - 前記構造体は、第2の構造体部分と第3の構造体部分とをさらに含み、前記第2の構造体部分は、前記第1のデバイスの第1の側に設置され、かつ、前記ベースと前記第1の構造体部分とに結合された導電性パスを含み、前記第3の構造体部分は、前記第1のデバイスの第2の側に設置され、かつ、前記ベースと前記第1の構造体部分とに結合された導電性パスを含む、請求項22に記載の装置。
- 前記第2及び第3の構造体部分のそれぞれは、第1の表面と、該第1の表面に相対する第2の表面と、前記第1の表面に設置されかつ前記ベースに結合された第3の導電性接点と、前記第2の表面に設置されかつ前記第1の構造体部分に結合された第4の導電性接点と、前記第1の導電性接点を前記第2の導電性接点に結合する第2の導電性パスとを含む、請求項23に記載の装置。
- 前記ダイの第1の積層と前記ダイの第2の積層との間に設置された第4の構造体部分をさらに含み、該第4の構造体部分は、前記ベースと前記第2のデバイスとに結合された導電性パスを含む、請求項22に記載の装置。
- 前記第1の構造体部分は前記第2のデバイスの長さより大きい長さを有する、請求項22に記載の装置。
- プロセッサと、
前記プロセッサと共に集積回路パッケージ内に封入されたメモリデバイスであって、該メモリデバイスはダイを含み、該ダイは、該ダイを少なくとも部分的に通る導電性パスを有し、該メモリデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、メモリデバイスと、
前記メモリデバイス及び前記プロセッサと共に積層をなすように配列され、かつ、信号を受け取るように構成されたベースと、
前記積層内であって且つ前記プロセッサ及び前記メモリデバイスのうちの少なくとも一方の外部に配置され、かつ、前記ベースと前記プロセッサ及び前記メモリデバイスのうちの少なくとも一方との間で前記信号の少なくとも1つのサブセットを伝達するように構成された構造体と、
を含むシステム。 - 前記メモリデバイスはダイの積層を含む、請求項27に記載のシステム。
- 前記集積回路パッケージはアンテナに接続されている、請求項27に記載のシステム。
- 集積回路パッケージのベースで信号を受けることであって、前記集積回路パッケージが第1のデバイスと第2のデバイスとを含み、前記第2のデバイスが前記第1のデバイス及び前記ベースと共に積層をなすように配列され、前記第1のデバイスは、前記第1のデバイスを少なくとも部分的に通る少なくとも1つの導電性パスを含み、前記第1のデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、ことと、
前記積層の内部にあってかつ前記第1のデバイス及び前記第2のデバイスのうちの少なくとも一方の外部にある構造体の導電性パスを用いて、前記ベースから前記第2のデバイスに前記信号の少なくとも1つのサブセットを伝達することであって、前記構造体の前記導電性パスの少なくとも一部が前記構造体のビアを通り抜ける、ことと、
を含む方法。 - 前記信号の少なくとも1つを伝達することは、前記ベースから前記第2のデバイスに前記信号のうちの少なくとも1つのデータ信号を伝達することと、前記ベースから前記第2のデバイスに前記信号のうちの少なくとも1つの電力信号を伝達することと、を含む、請求項30に記載の方法。
- 前記信号の少なくとも1つのサブセットを伝達することは、前記ベースから前記第2のデバイスに電力信号のみを伝達することを含む、請求項30に記載の方法。
- 前記ベースから前記第1のデバイスに前記信号の追加のサブセットを伝達することと、
前記第1のデバイスから前記第2のデバイスに前記信号の前記追加のサブセットを伝達することと、
をさらに含む、請求項30に記載の方法。 - 前記信号の前記追加のサブセットは電力信号を除外する、請求項33に記載の方法。
- 前記第1のデバイスから前記第2のデバイスに前記信号の前記追加のサブセットを伝達することは、前記第1のデバイスから前記構造体の一部に前記信号の前記追加のサブセットを伝達することと、前記構造体の前記一部から前記第2のデバイスに前記信号の前記追加のサブセットを伝達することと、を含む、請求項33に記載の方法。
- 前記第1のデバイスから前記第2のデバイスに前記信号の前記追加のサブセットを伝達することは、前記信号の前記追加のサブセットを、前記第1のデバイスのダイの少なくとも1つの積層の少なくとも1つのビアを通して伝達することを含む、請求項33に記載の方法。
- 第1のデバイスを第2のデバイスと共に積層をなすように配列することであって、前記第1のデバイスは、前記第1のデバイスを少なくとも部分的に通る少なくとも1つの導電性パスを含み、前記第1のデバイスは、ダイの第1の積層と、ダイの第2の積層とを含み、該ダイの第1および第2の積層は互いに並んで配列されている、ことと、
ベースと前記第1及び第2のデバイスのうちの少なくとも一方との間で信号の少なくとも1つのサブセットを伝達するよう、前記第1および第2のデバイスと共に前記積層をなすように構造体を配置することであって、前記構造体は前記信号を伝達するための導電性パスを含み、該導電性パスの少なくとも一部が前記構造体のビアを通り抜けている、ことと、
を含む方法。 - 前記構造体を配置することは、前記第1及び第2のデバイス間に前記構造体の一部を配列することを含む、請求項37に記載の方法。
- 前記構造体を配置することは、前記第1のデバイスの第1の側に前記構造体の第1の部分を配置することと、前記第1のデバイスの第2の側に前記構造体の第2の部分を配置することと、を含む、請求項37に記載の方法。
- 前記構造体を配置することは、前記構造体の一部と前記ベースとの間に前記第1及び第2のデバイスを配置することを含む、請求項37に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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US12/209,052 | 2008-09-11 | ||
US12/209,052 US8106520B2 (en) | 2008-09-11 | 2008-09-11 | Signal delivery in stacked device |
PCT/US2009/056544 WO2010030804A1 (en) | 2008-09-11 | 2009-09-10 | Signal delivery in stacked device |
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JP2012502506A JP2012502506A (ja) | 2012-01-26 |
JP5758296B2 true JP5758296B2 (ja) | 2015-08-05 |
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