JP5733466B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5733466B2
JP5733466B2 JP2014502163A JP2014502163A JP5733466B2 JP 5733466 B2 JP5733466 B2 JP 5733466B2 JP 2014502163 A JP2014502163 A JP 2014502163A JP 2014502163 A JP2014502163 A JP 2014502163A JP 5733466 B2 JP5733466 B2 JP 5733466B2
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metal
aluminum
bonding
semiconductor chip
wiring metal
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JPWO2013129229A1 (en
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宮本　健二
健二 宮本
中川　成幸
成幸 中川
義貴 上原
義貴 上原
千花 山本
千花 山本
南部　俊和
俊和 南部
井上　雅之
雅之 井上
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
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Description

本発明は、半導体装置、特に表面にアルミニウム系金属を備えた半導体チップと、少なくとも表面がアルミニウム系金属である配線金属とを接合して成る半導体装置の製造方法と、このような方法により製造された半導体装置に関するものである。   The present invention relates to a method of manufacturing a semiconductor device, in particular, a semiconductor device comprising a semiconductor chip having an aluminum-based metal on the surface and a wiring metal having at least a surface made of an aluminum-based metal, and manufactured by such a method. The present invention relates to a semiconductor device.

近年の半導体装置、特に、大電流密度の所謂ハイパワーモジュールと称する半導体装置においては、高温環境下でも使用可能であることが要求されている。
そのため、半導体装置の実装構造においては、高温に保持されたり、高温熱サイクルを受けたりした場合の高温耐久性に優れた接合部が強く望まれている。また、環境保全の観点からすると、Ｐｂ（鉛）フリーの接合技術が必須となっている。2. Description of the Related Art Recent semiconductor devices, particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment.
Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.

このような半導体装置の実装のための接合には、現状では、Ｓｎ（錫）−Ａｇ（銀）−Ｃｕ（銅）系のはんだが広く使われているが、使用温度がはんだの融点（例えば２００℃程度）以下に制限される。また、例えば、電極がＣｕである接合部においては、界面にＣｕ−Ｓｎ系の脆い金属間化合物層が生成し、高温耐久性に乏しいものとなる。
そのため、接合部の高温耐久性を確保するために、いろいろな試みがなされている。Currently, Sn (tin) -Ag (silver) -Cu (copper) based solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Further, for example, in a joint where the electrode is Cu, a Cu-Sn brittle intermetallic compound layer is generated at the interface, resulting in poor high-temperature durability.
Therefore, various attempts have been made to ensure the high temperature durability of the joint.

例えば、金属ナノ粒子の活性な表面エネルギーを利用して、低温にて凝集、接合する低温接合工法が提案されている（特許文献１参照）。この接合工法を用いれば、凝集した後の接合界面はバルク金属となるため、高い、高温耐久性を有する。   For example, a low-temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to aggregate and bond at a low temperature (see Patent Document 1). If this joining method is used, the joining interface after agglomeration becomes a bulk metal, and thus has high durability at high temperatures.

特開２００４−１２８３５７号公報JP 2004-128357 A

しかしながら、金属ナノ粒子として、Ａｕ（金）、Ａｇ（銀）といった貴金属を用い、このような金属ナノ粒子の表面に有機物を修飾したような構造をとるため、非常に高コストなものとなり、実際に量産適用するには現実的ではない。また、粒子が凝集した構造となり、しかも有機物が接合プロセス時にガス化して、残存することから接合部にはボイドが存在するため、継手強度のバラツキの大きいものとなるという問題がある。   However, since noble metals such as Au (gold) and Ag (silver) are used as metal nanoparticles, and the surface of such metal nanoparticles is modified with an organic substance, it is very expensive. It is not practical to apply to mass production. In addition, there is a problem that the structure has a structure in which particles are agglomerated, and the organic matter is gasified during the joining process and remains, so that voids exist in the joint, resulting in large variations in joint strength.

なお、高温はんだとしてはこの他に、Ａｕ系の組成を有するものとして、Ａｕ−Ｇｅ（ゲルマニウム）系はんだや、Ａｕ−Ｓｎ系はんだがあるが、これらも、貴金属であるＡｕを用いているため、非常に高コストなものとなり、上記同様、現実的ではない。   Other high-temperature solders include Au-Ge (germanium) -based solders and Au-Sn-based solders that have an Au-based composition, but these also use precious metal Au. It becomes very expensive and is not realistic as described above.

本発明は、半導体装置の実装構造に適用される従来の接合技術における上記したような課題に鑑みてなされたものであって、その目的とするところは、高温耐久性に優れ、しかも貴金属やＰｂを用いることなく、低コストな接合を可能にする半導体装置の製造方法を提供することにある。また、このような接合方法を適用した低コストで高温耐久性に優れた半導体装置を提供することにある。   The present invention has been made in view of the above-described problems in the conventional bonding technology applied to the mounting structure of a semiconductor device. The object of the present invention is excellent in high-temperature durability, and furthermore, precious metal and Pb. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables low-cost bonding without using a semiconductor device. It is another object of the present invention to provide a low-cost and high-temperature durability semiconductor device to which such a bonding method is applied.

本発明者らは、上記目的を達成すべく、鋭意検討を重ねた結果、半導体チップと配線金属の接合面をアルミニウム系金属とすると共に、これらの間にインサート材を介在させ、接合面に微細凹凸を形成し、接合界面にＡｌとインサート材との共晶反応を生じさせることによって、上記課題が解決できることを見出し、本発明を完成するに到った。   As a result of intensive investigations to achieve the above object, the present inventors have made the joining surface of the semiconductor chip and the wiring metal an aluminum-based metal, and interposed an insert material between them to make the joining surface fine. It has been found that the above problems can be solved by forming irregularities and causing a eutectic reaction between Al and the insert material at the bonding interface, and the present invention has been completed.

すなわち、本発明は上記知見に基づくものであって、本発明の半導体装置の製造方法においては、半導体チップの接合面に備えたアルミニウム系金属と、配線金属の少なくとも接合面に備えたアルミニウム系金属との間に、Ａｌと共晶反応を生じるＺｎを主成分とする金属を含むインサート材を介在させると共に、上記アルミニウム系金属表面の酸化皮膜を破壊するための微細凹凸を上記接合面及びインサート材表面の少なくとも一部に設け、上記半導体チップと配線金属を相対的に加圧しつつＡｌと上記インサート材との共晶反応が生じる温度に加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップと配線金属のアルミニウム系金属同士を直接接合することを特徴とする。 That is, the present invention is based on the above knowledge, and in the method for manufacturing a semiconductor device according to the present invention, an aluminum-based metal provided on the bonding surface of the semiconductor chip and an aluminum-based metal provided on at least the bonding surface of the wiring metal. And an insert material containing a metal containing Zn as a main component that causes a eutectic reaction with Al, and a fine unevenness for breaking the oxide film on the surface of the aluminum-based metal. Provided on at least a part of the surface, the semiconductor chip and the wiring metal are relatively pressurized and heated to a temperature at which a eutectic reaction between Al and the insert material occurs, and the eutectic reaction melt generated at the bonding interface is It is discharged together with the oxide film, and the semiconductor chip and the aluminum metal of the wiring metal are directly bonded to each other at at least a part of the bonding interface. To.

また、本発明の半導体装置は、半導体チップと配線金属とが接合されて成る半導体装置であって、上記方法によって製造することができ、上記半導体チップはアルミニウム系金属を表面に備え、上記配線金属は少なくとも表面にアルミニウム系金属を備え、上記半導体チップと配線金属のアルミニウム系金属同士が、接合界面の少なくとも一部において直接接合され、この直接接合部の周囲にＡｌとＺｎの共晶組成物と、Ａｌの酸化物を含む排出物が介在していることを特徴としている。 The semiconductor device of the present invention is a semiconductor device in which a semiconductor chip and a wiring metal are joined, and can be manufactured by the above method, and the semiconductor chip has an aluminum-based metal on the surface, and the wiring metal Has an aluminum-based metal at least on its surface, and the semiconductor chip and the aluminum metal of the wiring metal are directly bonded at at least a part of the bonding interface, and an eutectic composition of Al and Zn is formed around the direct bonding portion. Further, the present invention is characterized in that an effluent containing an oxide of Al is present.

本発明によれば、接合部に設けた微細凹凸によってアルミニウム系金属表面の酸化皮膜が破壊され、Ａｌとインサート材との間に共晶反応が生じ、低温、低加圧で酸化皮膜を除去して、半導体チップと配線金属のアルミニウム系金属同士を強固に接合することができ、低コストで高温耐久性に優れた接合が可能になる。   According to the present invention, the oxide film on the surface of the aluminum-based metal is destroyed by the fine unevenness provided in the joint, and a eutectic reaction occurs between Al and the insert material, and the oxide film is removed at low temperature and low pressure. Thus, the semiconductor chip and the aluminum metal of the wiring metal can be firmly bonded to each other, and bonding with excellent high-temperature durability can be achieved at low cost.

（ａ）〜（ｅ）は本発明の半導体装置の製造方法による半導体チップと配線金属との接合過程を概略的に示す工程図である。(A)-(e) is process drawing which shows roughly the joining process of the semiconductor chip and wiring metal by the manufacturing method of the semiconductor device of this invention. （ａ）〜（ｃ）は本発明の半導体装置の製造方法において接合部に形成する微細凹凸の形状例を示す斜視図である。(A)-(c) is a perspective view which shows the example of a shape of the fine unevenness | corrugation formed in a junction part in the manufacturing method of the semiconductor device of this invention. 本発明の製造方法による半導体装置の一方を構成する半導体チップの構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the semiconductor chip which comprises one side of the semiconductor device by the manufacturing method of this invention. （ａ）〜（ｃ）は本発明の製造方法による半導体装置の他方を構成する配線金属の形態例を示すそれぞれ断面図である。(A)-(c) is each sectional drawing which shows the form example of the wiring metal which comprises the other of the semiconductor device by the manufacturing method of this invention. （ａ）〜（ｄ）は本発明の製造方法による半導体装置の実施形態例を示すそれぞれ概略断面図である。(A)-(d) is each a schematic sectional drawing which shows the example of embodiment of the semiconductor device by the manufacturing method of this invention. （ａ）及び（ｂ）は本発明の製造方法による半導体装置の他の実施形態例を示すそれぞれ概略断面図である。(A) And (b) is each schematic sectional drawing which shows the other embodiment of the semiconductor device by the manufacturing method of this invention.

以下に、本発明の半導体装置の製造方法について、さらに詳細、かつ具体的に説明する。なお、本明細書において「％」は、特記しない限り、質量百分率を意味するものとする。   The semiconductor device manufacturing method of the present invention will be described in further detail and specifically below. In the present specification, “%” means mass percentage unless otherwise specified.

本発明の半導体装置の製造方法においては、半導体チップを配線金属に接合するに際して、上記したように、半導体チップの接合面に備えたアルミニウム系金属と、配線金属の少なくとも接合面に備えたアルミニウム系金属との間に、Ａｌ（アルミニウム）と共晶反応を生じるＺｎを主成分とする金属を含むインサート材を介在させる。さらに、接合面やインサート材の表面に微細凹凸を設け、この状態で、半導体チップと配線金属を相対的に加圧すると共にＡｌと上記インサート材との共晶反応が生じる温度に加熱し、アルミニウム系金属表面に形成されている酸化皮膜を微細凹凸により破壊して、アルミニウム系金属とインサート材とを接触させ、接合界面にＡｌとインサート材に含まれる金属との共晶反応を生じさせる。そして、この共晶反応溶融物を酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップと配線金属のアルミニウム系金属同士を直接接合するようにしている。 In the method of manufacturing a semiconductor device according to the present invention, when bonding a semiconductor chip to a wiring metal, as described above, an aluminum-based metal provided on the bonding surface of the semiconductor chip and an aluminum-based metal provided at least on the bonding surface of the wiring metal. An insert material containing a metal mainly composed of Zn that causes a eutectic reaction with Al (aluminum) is interposed between the metal and the metal. Further, fine irregularities are provided on the bonding surface and the surface of the insert material, and in this state, the semiconductor chip and the wiring metal are relatively pressurized and heated to a temperature at which a eutectic reaction between Al and the insert material occurs. The oxide film formed on the metal surface is destroyed by fine irregularities, the aluminum metal and the insert material are brought into contact, and a eutectic reaction between Al and the metal contained in the insert material is caused at the bonding interface. The eutectic reaction melt is discharged together with the oxide film so that the semiconductor chip and the aluminum metal of the wiring metal are directly bonded to each other at least at a part of the bonding interface.

すなわち、微細凹凸の先端に応力が集中するため、比較的低い加圧力によって、チップへのダメージを与えることなく酸化皮膜を破壊することができる。そして、この破壊部を介してアルミニウム系金属とインサート材とが接触し、この接触部を起点として生じた共晶反応が接合面全体に拡大することによって、接合面の酸化皮膜が低温度（共晶温度）で除去されるので、アルミニウム系金属同士のダイレクトな接合が可能となる。
したがって、貴金属やＰｂが含まれないアルミニウム系金属同士の直接接合によって強度が確保されることから、高温保持した場合にも脆い金属間化合物層やカーケンダルボイドを生成せず、優れた高温耐久性を備えたＰｂフリーの接合部を備えた半導体装置を低コストに製造することができる。That is, since stress concentrates on the tips of the fine irregularities, the oxide film can be destroyed without damaging the chip with a relatively low applied pressure. The aluminum-based metal and the insert material come into contact with each other through the fractured portion, and the eutectic reaction generated from the contacted portion expands to the entire joining surface, so that the oxide film on the joining surface has a low temperature (co-current). Therefore, direct bonding between aluminum-based metals becomes possible.
Therefore, strength is ensured by direct bonding of noble metals and aluminum-based metals that do not contain Pb, so even when kept at high temperatures, brittle intermetallic compound layers and Kirkendall voids are not generated, and excellent high temperature durability A semiconductor device provided with a Pb-free bonding portion provided with can be manufactured at low cost.

図１（ａ）〜（ｅ）は、本発明による半導体装置の製造方法における半導体チップと配線金属の接合プロセスを順を追って説明する工程図である。   FIG. 1A to FIG. 1E are process diagrams for explaining in sequence a bonding process between a semiconductor chip and a wiring metal in the method for manufacturing a semiconductor device according to the present invention.

まず、図１（ａ）に示すように、配線金属２と半導体チップ３の間に、インサート材４を配置する。
このとき、配線金属２は、この例ではアルミニウム系金属から成るものであって、その接合面には、予め微細凹凸２ｒが形成してあると共に、半導体チップ３の接合面には、アルミニウム系金属から成るアルミニウム層３ｃが形成されている。なお、これらアルミニウム系金属から成る配線金属２やアルミニウム層３ｃの表面には、それぞれＡｌ２Ｏ３を主成分とする強固な酸化皮膜２ｆ、３ｆが生成している。First, as shown in FIG. 1A, the insert material 4 is disposed between the wiring metal 2 and the semiconductor chip 3.
At this time, the wiring metal 2 is made of an aluminum-based metal in this example, and fine irregularities 2r are formed in advance on the bonding surface, and the aluminum-based metal is formed on the bonding surface of the semiconductor chip 3. An aluminum layer 3c made of is formed. In addition, strong oxide films 2f and 3f mainly composed of Al 2 O 3 are formed on the surfaces of the wiring metal 2 and the aluminum layer 3c made of these aluminum-based metals.

ここで、上記した配線金属２や、半導体チップ３のアルミニウム層３ｃの素材であるアルミニウム系金属としては、純アルミニウム材（工業用純アルミニウム）やＡｌを主成分として８０％以上含有する合金材を用いることができる。すなわち、本発明において「アルミニウム系金属」とは、このようなアルミニウム又はアルミニウム合金を意味する。   Here, as the above-described wiring metal 2 and the aluminum-based metal that is the material of the aluminum layer 3c of the semiconductor chip 3, a pure aluminum material (industrial pure aluminum) or an alloy material containing 80% or more of Al as a main component is used. Can be used. That is, in the present invention, “aluminum-based metal” means such aluminum or aluminum alloy.

上記配線金属２の接合面に形成する微細凹凸２ｒの形状としては、応力を集中させて、酸化皮膜の破壊を促進させる機能さえあれば、その形状や数に制限はなく、例えば、図２（ａ）〜（ｃ）に示すようなものを採用することができる。
すなわち、図２（ａ）に示すように、台形状断面の凹凸構造として、凸部先端を略平面とすれば、応力集中度は若干低下するとしても、応力集中手段の形成が容易となり、加工費を削減することができる。The shape of the fine irregularities 2r formed on the joint surface of the wiring metal 2 is not limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film. For example, FIG. Those shown in a) to (c) can be employed.
That is, as shown in FIG. 2 (a), if the convex-convex tip is made to be a substantially flat surface as a trapezoidal cross-sectional concavo-convex structure, the stress concentration means can be easily formed even if the stress concentration level is slightly reduced. Costs can be reduced.

また、図２（ｂ）に示すように、三角柱を並列させたような凹凸構造を採用することも可能であり、これによって、凹凸構造の凸部先端が線状のものとなり、応力集中度を高めて、酸化皮膜の破断効果を向上させることができる。
さらに、図２（ｃ）に示すように、四角錐を縦横方向に並列させた凹凸構造を採用することもでき、凹凸構造の凸部先端が点状となることから、さらに応力集中度を高めて、酸化皮膜の破断性能を向上させることができる。In addition, as shown in FIG. 2B, it is also possible to adopt a concavo-convex structure in which triangular prisms are arranged in parallel, whereby the convex tip of the concavo-convex structure becomes linear, and the stress concentration degree is increased. This can enhance the effect of breaking the oxide film.
Furthermore, as shown in FIG. 2 (c), it is possible to adopt a concavo-convex structure in which square pyramids are juxtaposed in the vertical and horizontal directions. Thus, the breaking performance of the oxide film can be improved.

微細凹凸２ｒの形状としては、上記したように、応力を集中させて、酸化皮膜の破壊を促進させる機能さえあれば、特に限定されることはなく、上記の他には、波形やかまぼこ形、半球状など凸部先端を曲面とすることも可能である。なお、当該曲面の曲率半径は、小さいほど応力集中が顕著なものとなって、酸化皮膜が破壊し易くなることは言うまでもない。   The shape of the fine unevenness 2r is not particularly limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film as described above. The tip of the convex part such as a hemisphere can be curved. Needless to say, the smaller the radius of curvature of the curved surface, the more the stress concentration becomes more prominent, and the oxide film is easily broken.

このような微細凹凸２ｒは、例えば、切削加工、研削加工、塑性加工（ローラ加工）、レーザ加工、放電加工、エッチング加工、リソグラフィーなどによって形成することができ、その形成方法としては、特に限定されるものではない。これら加工方法のうち、塑性加工によれば、非常に低コストで形成が可能である。
なお、微細凹凸の寸法、形状としては、アスペクト比（高さ／幅）：０．００１以上、ピッチ：１μｍ以上で、望ましくはアスペクト比０．１以上、ピッチ：１０μｍ以上である。Such fine irregularities 2r can be formed by, for example, cutting, grinding, plastic processing (roller processing), laser processing, electric discharge processing, etching processing, lithography, or the like, and the formation method is particularly limited. It is not something. Of these processing methods, plastic processing enables formation at a very low cost.
The dimensions and shape of the fine irregularities are an aspect ratio (height / width): 0.001 or more, a pitch: 1 μm or more, and preferably an aspect ratio of 0.1 or more and a pitch: 10 μm or more.

一方、半導体チップ３は、上記したように接合面側に、上記アルミニウム系金属から成るアルミニウム層３ｃを備えているが、図３に示すように、ＳｉＣやＳｉ、ＧａＮなどから成る半導体チップ本体３とアルミニウム層３ｃの間に、密着層３ａ及びバリヤ層３ｂを介在させることができる。   On the other hand, the semiconductor chip 3 is provided with the aluminum layer 3c made of the aluminum-based metal on the joint surface side as described above, but as shown in FIG. 3, the semiconductor chip body 3 made of SiC, Si, GaN or the like. An adhesion layer 3a and a barrier layer 3b can be interposed between the aluminum layer 3c and the aluminum layer 3c.

バリヤ層３ｂは、Ａｌがアルミニウム層３ｃからチップ本体内に拡散するのを防止する機能を有し、Ｎｉ（ニッケル）やＲｔ−Ｉｒ（白金−イリジウム）などを適用することができる。
一方、密着層３ａは、上記バリヤ層３ｂとチップ本体３との密着性を向上させる機能を有し、例えば、Ｔｉ（チタン）、Ｃｒ（クロム）などを用いることができる。The barrier layer 3b has a function of preventing Al from diffusing from the aluminum layer 3c into the chip body, and Ni (nickel), Rt—Ir (platinum-iridium), or the like can be applied.
On the other hand, the adhesion layer 3a has a function of improving the adhesion between the barrier layer 3b and the chip body 3, and for example, Ti (titanium), Cr (chromium), or the like can be used.

インサート材４は、Ａｌと共晶反応を生じる金属を含むものであって、具体的には、Ｚｎ（亜鉛）を主成分とする金属（純亜鉛、亜鉛合金）や、Ｚｎと共晶反応を生じる金属とＺｎとの合金、例えばＺｎとＡｌを主成分とする合金、ＺｎとＭｇ（マグネシウム）を主成分とする合金、ＺｎとＣｕ（銅）を主成分とする合金、ＺｎとＳｎ（錫）を主成分とする合金、ＺｎとＡｇ（銀）を主成分とする合金、ＺｎとＭｇとＡｌを主成分とする合金、ＺｎとＣｕ（銅）とＡｌを主成分とする合金、ＺｎとＳｎ（錫）とＡｌを主成分とする合金、ＺｎとＡｇ（銀）とＡｌを主成分とする合金の薄板や箔を用いることができる。
なお、本発明において、「主成分」とは、上記金属の含有量の合計が８０％以上であることを意味するものとする。The insert material 4 includes a metal that causes a eutectic reaction with Al. Specifically, the insert material 4 has a metal (pure zinc, zinc alloy) containing Zn (zinc) as a main component, or a eutectic reaction with Zn. Alloys of the resulting metal and Zn, for example, alloys containing Zn and Al as main components, alloys containing Zn and Mg (magnesium) as main components, alloys containing Zn and Cu (copper) as main components, Zn and Sn (tin) ), An alloy mainly composed of Zn and Ag (silver), an alloy mainly composed of Zn, Mg and Al, an alloy mainly composed of Zn, Cu (copper) and Al, and Zn An alloy mainly composed of Sn (tin) and Al, or a thin plate or foil of an alloy mainly composed of Zn, Ag (silver), and Al can be used.
In the present invention, the “main component” means that the total content of the metals is 80% or more.

そして、図１（ａ）に示した状態で、半導体チップ３と配線金属２を相対的に加圧して、これらをインサート材４を介して密着させ、さらに加圧しながら加熱を開始する。
すると、図１（ｂ）に示すように、微細凹凸２ｒの凸部先端が接触した部位の応力が局所的に急激に上昇し、加圧力をさほど増すことなく、アルミニウム層３ｃの酸化被膜３ｆが機械的に破壊され、新生面が露出する。また、酸化被膜３ｆと共に、微細凹凸２ｒ先端の酸化皮膜２ｆも破壊され、配線金属２の新生面が露出する。Then, in the state shown in FIG. 1A, the semiconductor chip 3 and the wiring metal 2 are relatively pressurized, brought into close contact via the insert material 4, and heating is started while further pressing.
Then, as shown in FIG. 1 (b), the stress at the portion where the tip of the convex portion of the fine unevenness 2r contacts locally rapidly increases, and the oxide film 3f of the aluminum layer 3c is formed without increasing the applied pressure so much. It is mechanically destroyed and the new surface is exposed. In addition to the oxide film 3f, the oxide film 2f at the tip of the fine irregularities 2r is also destroyed, and the new surface of the wiring metal 2 is exposed.

アルミニウム層３ｃ及び配線金属２とインサート材４の間で拡散が生じ、共晶反応が発生する温度に到達すると、アルミニウム層３ｃ及び配線金属２中のＡｌとの間に共晶反応を起こし、共晶溶融相が発生する。
そして、この共晶溶融範囲が接合界面全体に拡がっていくことにより、アルミニウム層３ｃ及び配線金属２の酸化被膜３ｆ、２ｆが表面から除去され、図１（ｃ）に示すように、酸化皮膜３ｆ、２ｆの欠片が共晶溶融相中に分散する。When diffusion occurs between the aluminum layer 3c and the wiring metal 2 and the insert material 4 and reaches a temperature at which a eutectic reaction occurs, a eutectic reaction occurs between the aluminum layer 3c and Al in the wiring metal 2, and the co-crystal reaction occurs. A crystal melt phase is generated.
The eutectic melting range extends to the entire bonding interface, so that the aluminum layer 3c and the oxide films 3f and 2f of the wiring metal 2 are removed from the surface, and as shown in FIG. The 2f fragments are dispersed in the eutectic melt phase.

続く加圧によって、図１（ｄ）に示すように、共晶反応溶融物が接合界面から排出され、この液相中に分散されていた酸化皮膜３ｆ、２ｆの欠片もその大部分が共晶溶融物と共に接合界面から押し出され、アルミニウム系金属の新生面が露出し、接合界面にＡｌの拡散反応が生じる。
これによって、図１（ｅ）に示すように、配線金属２と半導体チップ３のアルミニウム層３ｃとの接合、すなわちアルミニウム系金属同士の直接的な接合が達成される。このとき、共晶反応生成物や酸化皮膜、インサート材に由来する金属などを含む微量の混合物が接合界面に残存することがあり得るが、アルミニウム系金属同士の直接接合部が形成されている限り、強度上の問題となることはない。また、このような残存物は、電気伝導や熱伝導に寄与することになる。By subsequent pressurization, as shown in FIG. 1 (d), the eutectic reaction melt is discharged from the bonding interface, and most of the fragments of the oxide films 3f and 2f dispersed in the liquid phase are eutectic. It is extruded from the bonding interface together with the melt, exposing a new surface of the aluminum-based metal, and causing Al diffusion reaction at the bonding interface.
As a result, as shown in FIG. 1E, the bonding between the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3, that is, the direct bonding between the aluminum-based metals is achieved. At this time, a small amount of a mixture containing eutectic reaction products, oxide films, metals derived from insert materials, etc. may remain at the bonding interface, but as long as a direct bonding portion between aluminum-based metals is formed. It will not be a problem on strength. Moreover, such a residue contributes to electric conduction and heat conduction.

なお、図１においては、微細凹凸２ｒを配線金属２の側に形成した例を示したが、これに限定されることはなく、微細凹凸の形成位置については、接合部位の少なくとも１箇所に形成すればよく、上記のように配線金属２と半導体チップ３の接合面の一方に形成するほか、接合面の両方に設けることができる。両面に形成することによって、酸化皮膜の破壊起点をより多くすることができる。
さらに、微細凹凸は、インサート材４の片面あるいは両面に形成することもでき、こうすることによって、配線金属２や半導体チップ３の微細凹凸の形成工程を加える必要がなくなるので、低コストの接合が可能になる。1 shows an example in which the fine unevenness 2r is formed on the wiring metal 2 side, but the present invention is not limited to this, and the formation position of the fine unevenness is formed in at least one of the joining parts. In addition to being formed on one of the bonding surfaces of the wiring metal 2 and the semiconductor chip 3 as described above, it can be provided on both of the bonding surfaces. By forming it on both surfaces, it is possible to increase the breakdown starting point of the oxide film.
Further, the fine irregularities can be formed on one side or both sides of the insert material 4, which eliminates the need to add a fine irregularity forming step for the wiring metal 2 or the semiconductor chip 3. It becomes possible.

また、上記では、薄板上のインサート材４を配線金属２の上に載置しただけの例を示したが、組成や形状（厚さ）などに関する選択の自由度が高いことから、箔の形態で両材料の間に挟み込むことが望ましい。
この他に、めっきやパウダーデポジション法によって、インサート材金属を配線金属２や半導体チップ３の一方あるいは両方の接合面に予め被覆しておくことも可能であり、この場合には、被覆によって酸化皮膜の生成を防止できる。Moreover, although the example which only mounted the insert material 4 on a thin plate on the wiring metal 2 was shown above, since the freedom degree of selection regarding a composition, a shape (thickness), etc. is high, the form of foil It is desirable to sandwich between the two materials.
In addition, it is also possible to preliminarily coat the joint surface of one or both of the wiring metal 2 and the semiconductor chip 3 by plating or a powder deposition method. Formation of a film can be prevented.

そして、図１においては、配線金属２として、アルミニウム系金属から成るものを用いたが、後述するように、他の金属から成る基材、例えば銅製基材の表面に上記アルミニウム系金属から成る層を形成したものを用いることもできる。
このようなアルミニウム層を基材上に形成するには、めっきやスパッタリング、溶射などの方法を適用することができる。なお、これらの方法は、半導体チップ３に対するアルミニウム層２ｃの形成にも適用されることは言うまでもない。In FIG. 1, the wiring metal 2 is made of an aluminum-based metal. However, as will be described later, a layer made of the above-mentioned aluminum-based metal on the surface of a substrate made of another metal, for example, a copper substrate. What formed this can also be used.
In order to form such an aluminum layer on the substrate, a method such as plating, sputtering, or thermal spraying can be applied. Needless to say, these methods are also applied to the formation of the aluminum layer 2 c on the semiconductor chip 3.

本発明の製造方法における配線金属２と半導体チップ３の上記接合は、不活性ガス雰囲気で行うこともできるが、大気中でも何ら支障はなく行うことができる。
もちろん、真空中で行うことも可能であるが、真空設備が必要となるばかりでなく、インサート材の溶融により真空計やゲートバルブを損傷する可能性があるので、大気中で行うことが設備面からもコスト的にも有利である。The above-described joining of the wiring metal 2 and the semiconductor chip 3 in the manufacturing method of the present invention can be performed in an inert gas atmosphere, but can be performed without any trouble even in the air.
Of course, it is possible to carry out in vacuum, but not only vacuum equipment is required, but also the vacuum gauge and gate valve may be damaged by melting of the insert material. Therefore, it is advantageous in terms of cost.

本発明における上記接合において、接合部を所定の温度範囲に加熱したり、維持したりするための手段としては、特に限定されることはなく、例えば、高周波加熱や赤外線加熱、ヒータ加熱あるいはこれらを組み合わせた方法を採用することができる。また、治具によって加圧状態に固定し、治具と共にろう付け炉内に保持するといった方法を用いることも可能である。   In the above-described bonding according to the present invention, means for heating or maintaining the bonding portion within a predetermined temperature range is not particularly limited. For example, high-frequency heating, infrared heating, heater heating, or the like can be used. A combined method can be employed. Moreover, it is also possible to use a method of fixing in a pressurized state with a jig and holding it in a brazing furnace together with the jig.

上記接合温度への昇温速度については、遅い場合には、界面が酸化されて溶融物の排出性が低下して、強度が低下する原因となることがあるため、速い方が望ましい。特に大気中の接合の場合には、この傾向がある。   As for the rate of temperature rise to the bonding temperature, if it is slow, the interface is oxidized and the melt discharge property is lowered, which may cause the strength to be lowered. This tendency occurs particularly in the case of bonding in the atmosphere.

一方、本発明の製造方法においては、微細凹凸２ｒの形成によって、接合時の加圧力を低減することができることから、接合時の加圧力については、１ＭＰａ以上、３０ＭＰａ以下とすることが望ましい。
すなわち、１ＭＰａに満たない場合は、酸化皮膜の破壊や、共晶反応物や酸化皮膜欠片の接合面からの排出が十分にできず、３０ＭＰａを超えると半導体チップ２が損傷する可能性があることによる。On the other hand, in the manufacturing method of the present invention, since the pressurizing force at the time of joining can be reduced by forming the fine unevenness 2r, the pressurizing force at the time of joining is preferably set to 1 MPa or more and 30 MPa or less.
That is, when the pressure is less than 1 MPa, the oxide film cannot be destroyed or the eutectic reaction product or the oxide film fragments can be sufficiently discharged from the joint surface. If the pressure exceeds 30 MPa, the semiconductor chip 2 may be damaged. by.

図４（ａ）〜（ｃ）は、本発明の製造方法における接合面、特に配線金属の形態例を示すそれぞれ断面図であって、図４（ａ）に示す形態例においては、半導体チップ３がその接合最表面にアルミニウム層３ｃを備える一方、配線金属２は、図１と同様に、全体がアルミニウム系金属から成り、接合面に微細凹凸２ｒを備えている。   4 (a) to 4 (c) are cross-sectional views showing examples of the bonding surface, particularly the wiring metal in the manufacturing method of the present invention. In the embodiment shown in FIG. 4 (a), the semiconductor chip 3 is shown. Is provided with an aluminum layer 3c on the outermost surface of the joint, and the wiring metal 2 is entirely made of an aluminum-based metal, and has fine irregularities 2r on the joint surface, as in FIG.

また、配線金属２は、図４（ｂ）及び（ｃ）に示すように、例えば銅製の基板２ｂの接合面に、上記アルミニウム系金属から成るアルミニウム層２ｃを備えたものを用いることもできる。   Further, as shown in FIGS. 4B and 4C, the wiring metal 2 may be one in which an aluminum layer 2c made of the aluminum-based metal is provided on the bonding surface of a copper substrate 2b, for example.

この場合、図４（ｂ）に示したように、基板２ｂの接合面に微細凹凸２ｒを形成した後に、アルミニウム層２ｃをめっきやスパッタリング、蒸着などによって形成することができる。これによれば、比較的自由な形状に形成された微細凹凸２ｒの全面にアルミニウム層２ｃを配置することができる。
一方、図４（ｃ）に示したように、基板２ｂの上にアルミニウム層２ｃを配置した後に微細凹凸２ｒの加工を行うこともでき、この場合には、アルミニウム層が予め基材上に配置された材料、例えばクラッド材などを用いることができ、適用可能な材料の選択範囲が拡がることになる。In this case, as shown in FIG. 4B, after forming the fine irregularities 2r on the bonding surface of the substrate 2b, the aluminum layer 2c can be formed by plating, sputtering, vapor deposition, or the like. According to this, the aluminum layer 2c can be disposed on the entire surface of the fine irregularities 2r formed in a relatively free shape.
On the other hand, as shown in FIG. 4C, after the aluminum layer 2c is disposed on the substrate 2b, the fine unevenness 2r can be processed. In this case, the aluminum layer is disposed on the base material in advance. The selected material, for example, a clad material can be used, and the range of applicable materials can be expanded.

本発明の製造方法により製造された半導体装置の構造は、半導体チップと配線金属とが接合されて成るものであって、半導体チップは接合面にアルミニウム系金属を備える一方、配線金属は、少なくとも接合面にアルミニウム系金属を備え、上記半導体チップと配線金属のアルミニウム系金属同士が、接合界面の少なくとも一部において直接接合されたものとなる。そして、このような直接接合部の周囲、すなわち微細凹凸２ｒの底部（谷部）や微細凹凸２ｒの最外周部にＡｌの共晶組成物と、Ａｌの酸化物を含む排出物が介在することになる（図２（ｅ）参照）。   The structure of the semiconductor device manufactured by the manufacturing method of the present invention is formed by bonding a semiconductor chip and a wiring metal, and the semiconductor chip includes an aluminum-based metal on the bonding surface, while the wiring metal is at least bonded. The surface is provided with an aluminum-based metal, and the semiconductor chip and the aluminum-based metal of the wiring metal are directly bonded at least at a part of the bonding interface. And the eutectic composition of Al and the discharge containing an oxide of Al intervene around such a direct joint part, that is, the bottom (valley part) of the fine unevenness 2r and the outermost peripheral part of the fine unevenness 2r. (See FIG. 2 (e)).

なお、ここで、「Ａｌの共晶組成物」とは、Ａｌとインサート材に含まれる少なくとも１種の金属との共晶反応による組成物、「Ａｌの酸化物」については、アルミニウム系金属表面、インサート材表面に生成していた酸化皮膜の欠片ということになる。
また、接合条件、すなわち、加圧力、接合温度、微細凹凸形状、インサート材の成分、量などの調整により、微細凹凸底部の残存を可及的に減らすことができ、断続的な接合を全面的な直接接合に近づけることができる。Here, “Al eutectic composition” means a composition obtained by a eutectic reaction between Al and at least one metal contained in the insert material, and “Al oxide” means an aluminum metal surface. This is a fragment of the oxide film generated on the surface of the insert material.
In addition, by adjusting the bonding conditions, that is, pressure, bonding temperature, fine uneven shape, insert material composition, amount, etc., the remaining of the bottom of the fine unevenness can be reduced as much as possible. Can be close to direct bonding.

図５（ａ）〜（ｄ）は、本発明の製造方法による半導体装置の実施形態の数例を示す概略断面図である。
第1の実施形態として、図５（ａ）に示す半導体装置１は、冷却体（ヒートシンク）１１上に、絶縁性セラミックス基板１２の片面側にアルミニウム系金属製の配線金属２を配置したバスバーが固定され、その配線金属２に半導体チップ３が接合された構造を備えている。そして、上記半導体チップ３は、その接合面にアルミニウム系金属から成るアルミニウム層３ｃを備えており、アルミニウム系金属同士が上記した方法により直接接合された構造となっている。5A to 5D are schematic cross-sectional views showing several examples of embodiments of a semiconductor device according to the manufacturing method of the present invention.
As a first embodiment, a semiconductor device 1 shown in FIG. 5A includes a bus bar in which a wiring metal 2 made of an aluminum-based metal is arranged on one side of an insulating ceramic substrate 12 on a cooling body (heat sink) 11. The semiconductor chip 3 is bonded to the wiring metal 2 and fixed. The semiconductor chip 3 is provided with an aluminum layer 3c made of an aluminum-based metal on the bonding surface thereof, and has a structure in which the aluminum-based metals are directly bonded by the method described above.

図５（ｂ）に示す半導体装置１は、絶縁性セラミックス基板１２の両面にアルミニウム系金属から成る配線金属２を備えたセラミックス基板の一方の面に冷却体１１を備え、他方の面上の配線金属２と、同様に接合面にアルミニウム層３ｃを備えた半導体チップ３が接合された構造となっている。   The semiconductor device 1 shown in FIG. 5B includes a cooling body 11 on one surface of a ceramic substrate provided with a wiring metal 2 made of an aluminum-based metal on both surfaces of an insulating ceramic substrate 12, and wiring on the other surface. The metal 2 and the semiconductor chip 3 having the aluminum layer 3c on the joint surface are similarly joined.

図５（ｃ）に示す半導体装置１は、図５（ａ）及び（ｂ）が片側実装であったのに対し、両面実装タイプの半導体装置の例を示すものであって、両面にアルミニウム層３ｃを備えた半導体チップ３の上下に、絶縁性セラミックス基板１２の片面側に配線金属２を備えたバスバーが冷却体１１と共に配置されている。半導体チップ３の上下両面に備えたアルミニウム層３ｃとバスバーのアルミニウム系金属製配線金属２が上記した方法により直接接合された構造となっている。   The semiconductor device 1 shown in FIG. 5 (c) shows an example of a double-sided mounting type semiconductor device, whereas FIGS. 5 (a) and 5 (b) show single-sided mounting, and an aluminum layer is formed on both sides. A bus bar provided with the wiring metal 2 on one side of the insulating ceramic substrate 12 is disposed together with the cooling body 11 above and below the semiconductor chip 3 provided with 3c. The aluminum layer 3c provided on the upper and lower surfaces of the semiconductor chip 3 and the aluminum metal wiring metal 2 of the bus bar are directly joined by the method described above.

第４の実施形態として、図５（ｄ）に示す半導体装置１は、絶縁性セラミックス基板１２の両面にアルミニウム系金属製の配線金属２を備えたセラミックス基板を用いた両面実装タイプのものであって、セラミックス基板を用いたことを除いて、図５（ｃ）に示した形態と実質的に同様の構造となっている。   As a fourth embodiment, the semiconductor device 1 shown in FIG. 5 (d) is of a double-sided mounting type using a ceramic substrate provided with a wiring metal 2 made of an aluminum-based metal on both sides of an insulating ceramic substrate 12. The structure is substantially the same as that shown in FIG. 5C except that a ceramic substrate is used.

図６（ａ）は、絶縁性セラミックス基板１２の両面に備えた配線金属２の上面側に半導体チップ３を備えた素子をベースプレート１３の上に接合した構造を有する半導体装置の形態例を示すものであって、絶縁性セラミックス基板１２の下面側の配線金属２とベースプレート１３の接合に際しても、同様の接合方法を採用することができる。
すなわち、ベースプレート１３としては、アルミニウム系金属製あるいは少なくとも接合面をアルミニウム系金属とし、これらの間にインサート材を介在させ、配線金属及びベースプレートの接合面、インサート材表面の少なくとも一部に微細凹凸を設け、共晶溶融を生じさせることによって接合することができる。FIG. 6A shows an example of a semiconductor device having a structure in which an element having a semiconductor chip 3 is joined on a base plate 13 on the upper surface side of a wiring metal 2 provided on both surfaces of an insulating ceramic substrate 12. Thus, the same joining method can be adopted when joining the wiring metal 2 on the lower surface side of the insulating ceramic substrate 12 and the base plate 13.
That is, the base plate 13 is made of an aluminum-based metal or at least a joining surface is made of an aluminum-based metal, and an insert material is interposed between them. It can be joined by providing and causing eutectic melting.

このとき、図６（ｂ）に示すように、配線金属とベースプレートの双方に微細凹凸を設けることが望ましく、これによって接合性が向上して、加圧力が低くても接合が可能になり、絶縁性セラミックス基板１２の両面の配線金属２をベースプレート１３及び半導体チップ３に同時に接合する場合に好適な方法と言える。なお、配線金属２と半導体チップ３及びベースプレート１３の間には、インサート材が介在するが、図中には、省略されている。   At this time, as shown in FIG. 6 (b), it is desirable to provide fine irregularities on both the wiring metal and the base plate. This improves the bondability and enables bonding even when the applied pressure is low. This can be said to be a suitable method when the wiring metal 2 on both surfaces of the conductive ceramic substrate 12 is bonded to the base plate 13 and the semiconductor chip 3 at the same time. An insert material is interposed between the wiring metal 2, the semiconductor chip 3, and the base plate 13, but is omitted in the drawing.

以下、本発明を実施例に基づいて具体的に説明する。   Hereinafter, the present invention will be specifically described based on examples.

（実施例１）
純度９９．９９％の高純度アルミニウムから成る配線金属２を備えたバスバーを使用し、これに半導体チップ３として、厚さ１７０μｍのＳｉから成るＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）を片側実装した半導体装置を作製した（図５（ａ）参照）。Example 1
A semiconductor device using a bus bar provided with a wiring metal 2 made of high-purity aluminum having a purity of 99.99% and mounting an IGBT (insulated gate bipolar transistor) made of Si having a thickness of 170 μm on one side as a semiconductor chip 3 (See FIG. 5A).

このとき、上記ＩＧＢＴ（半導体チップ）３の接合面側には、予め、チタンから成る厚さ０．５μｍの密着層３ａと、ニッケルから成る厚さ１μｍのバリヤ層３ｂを介して、最表層にアルミニウム層３ｃを６μｍの厚さに蒸着した。
また、配線金属２の接合面には、高さ１００μｍ、アスペクト比１．０、ピッチ１００μｍの三角形溝の周期構造を有する微細凹凸２ｒ（図２（ｂ）参照）を切削加工によって形成した。At this time, on the joint surface side of the IGBT (semiconductor chip) 3, the outermost layer is formed in advance through an adhesion layer 3 a made of titanium having a thickness of 0.5 μm and a barrier layer 3 b made of nickel having a thickness of 1 μm. An aluminum layer 3c was deposited to a thickness of 6 μm.
Further, fine irregularities 2r (see FIG. 2B) having a triangular groove periodic structure with a height of 100 μm, an aspect ratio of 1.0, and a pitch of 100 μm were formed on the bonding surface of the wiring metal 2 by cutting.

次に、配線金属２と半導体チップ３の接合面間にＺｎ−３．５％Ａｌ−２．５％Ｍｇ合金から成る厚さ１００μｍのインサート材４を挟み、この状態で、接合面間に常時５ＭＰａの加圧力が掛かるように治具を用いて固定した。そして、ろう付け炉内に収納し、４００℃に１分間保持することによって、配線金属２と半導体チップ３を接合した。
その結果、配線金属２と半導体チップ３のアルミニウム系金属同士が脆弱な反応層を形成することなく、直接的に、強固に接合され、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度（３００℃以上）、長期信頼性に優れた実装ダイボンド構造を得ることができた。Next, an insert material 4 made of a Zn-3.5% Al-2.5% Mg alloy and having a thickness of 100 μm is sandwiched between the joint surfaces of the wiring metal 2 and the semiconductor chip 3, and in this state, always between the joint surfaces. Fixing was performed using a jig so that a pressure of 5 MPa was applied. And it accommodated in the brazing furnace and was hold | maintained at 400 degreeC for 1 minute, and the wiring metal 2 and the semiconductor chip 3 were joined.
As a result, the wiring metal 2 and the aluminum metal of the semiconductor chip 3 are directly and firmly joined without forming a fragile reaction layer, Pb-free, low cost, less strength variation, high temperature strength (300 C. or higher), and a mounting die bond structure with excellent long-term reliability was obtained.

（実施例２）
上記実施例１と同様の片側実装した半導体装置を作製するに際し、銅合金から成り、その接合面に上記同様に微細凹凸２ｒを形成した後、厚さ３μｍのアルミニウム層２ｃを蒸着した配線金属２を備えたバスバーを用いた。これ以外は、上記実施例１と同様の操作を繰り返すことによって、配線金属２と半導体チップ３のアルミニウム層２ｃ、３ｃを接合した。
その結果、同様に、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を得ることができた。(Example 2)
When producing a semiconductor device mounted on one side similar to the first embodiment, the wiring metal 2 is made of a copper alloy, and after forming the fine irregularities 2r on the joint surface in the same manner as described above, the aluminum layer 2c having a thickness of 3 μm is deposited. A bus bar equipped with was used. Except for this, the wiring metal 2 and the aluminum layers 2c and 3c of the semiconductor chip 3 were joined by repeating the same operation as in the first embodiment.
As a result, it was possible to obtain a mounting die-bonding structure that was similarly Pb-free, low cost, low in strength variation, and excellent in high-temperature strength and long-term reliability.

（実施例３）
上記実施例１と同様の片側実装した半導体装置を作製するに際し、銅合金に厚さ５０μｍの純度９９．９９％の高純度アルミニウムがクラッドされ、この上に上記同様に微細凹凸２ｒを形成した板材から成る配線金属２を備えたバスバーを用いた。これ以外は、上記実施例１と同様の操作を繰り返すことによって、配線金属２のアルミニウムクラッド層２ｃと半導体チップ３のアルミニウム層３ｃを接合した。
その結果、同様に、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を得ることができた。(Example 3)
When producing a semiconductor device mounted on one side similar to Example 1, a copper alloy is clad with a high purity aluminum having a thickness of 50 μm and a purity of 99.99%, and a fine unevenness 2r is formed on the copper material in the same manner as above. A bus bar provided with a wiring metal 2 made of Except for this, the same operation as in Example 1 was repeated to join the aluminum clad layer 2c of the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3 together.
As a result, it was possible to obtain a mounting die-bonding structure that was similarly Pb-free, low cost, low in strength variation, and excellent in high-temperature strength and long-term reliability.

（実施例４）
厚さ６３５μｍのＡｌＮから成り、厚さ５００μｍの純度９９．９９％の高純度アルミニウム製の配線金属２を備えたセラミックス基板を使用し、この配線金属２ａに上記同様に微細凹凸２ｒを形成した。これ以外は、上記実施例１と同様の操作を繰り返して、配線金属２と半導体チップ３のアルミニウム層３ｃを接合し、セラミックス基板上に、同様の半導体チップ３を片側実装した半導体装置を作製した（図５（ｂ）参照）。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。Example 4
Using a ceramic substrate made of AlN having a thickness of 635 μm and having a wiring metal 2 made of high-purity aluminum having a thickness of 500 μm and a purity of 99.99%, fine irregularities 2r were formed on the wiring metal 2a as described above. Except for this, the same operation as in Example 1 was repeated, the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3 were joined, and a semiconductor device in which the same semiconductor chip 3 was mounted on one side on the ceramic substrate was produced. (See FIG. 5 (b)).
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例５）
上記実施例４と同様の片側実装した半導体装置を作製するに際して、厚さ６３５μｍのＡｌＮから成り、厚さ５００μｍの銅合金製であって、その接合面に微細凹凸２ｒを上記同様に形成した後、厚さ３μｍのアルミニウム層２ｃを蒸着した配線金属２を備えたセラミックス基板を使用した。これ以外は、上記実施例１と同様の操作を繰り返して、配線金属２のアルミニウム層２ｃと半導体チップ３のアルミニウム層３ｃを接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。(Example 5)
When manufacturing a semiconductor device mounted on one side similar to the above-described Example 4, after being formed of AlN having a thickness of 635 μm and made of a copper alloy having a thickness of 500 μm, the fine unevenness 2r is formed on the joint surface in the same manner as described above. A ceramic substrate provided with a wiring metal 2 on which an aluminum layer 2c having a thickness of 3 μm was deposited was used. Except for this, the same operation as in Example 1 was repeated to join the aluminum layer 2c of the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3 together.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例６）
上記半導体チップ３に、上記実施例１で用いたバスバー、すなわち同様の微細凹凸２ｒを有するアルミニウム系金属製の配線金属２を備えたバスバーを両側実装した半導体装置を作製した（図５（ｃ）参照）。すなわち、半導体チップ３の両面それぞれに、密着層３ａ、バリヤ層３ｂを介して、最表層にアルミニウム層３ｃを同様の厚さに蒸着すると共に、その両面に、同様のインサート材４を介して上記バスバーをそれぞれ配置し、同様の操作を繰り返した。これによって、半導体チップ３の両面に備えたアルミニウム層３ｃをアルミニウム系金属製配線金属２にそれぞれ接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。(Example 6)
A semiconductor device was produced in which the bus bar used in Example 1 above, that is, the bus bar provided with the wiring metal 2 made of aluminum metal having the same fine irregularities 2r was mounted on both sides of the semiconductor chip 3 (FIG. 5C). reference). That is, the aluminum layer 3c is vapor-deposited on the both surfaces of the semiconductor chip 3 with the same thickness through the adhesion layer 3a and the barrier layer 3b, and the above-described material is inserted into the both surfaces with the same insert material 4 on the both surfaces. Each bus bar was placed and the same operation was repeated. Thus, the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 were joined to the aluminum metal wiring metal 2, respectively.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例７）
上記実施例６と同様の両側実装した半導体装置を作製するに際し、銅合金から成り、その接合面に上記同様の微細凹凸２ｒを形成した後、厚さ３μｍのアルミニウム層２ｃを蒸着した配線金属２を備えた上記実施例２と同様のバスバーを用いた。これ以外は、上記実施例６と同様の操作を繰り返すことによって、半導体チップ３の両面に備えたアルミニウム層３ｃを配線金属２のアルミニウム層２ｃにそれぞれ接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。(Example 7)
When producing a semiconductor device mounted on both sides similar to Example 6, the wiring metal 2 is made of a copper alloy, and the fine irregularities 2r similar to the above are formed on the joint surface, and then an aluminum layer 2c having a thickness of 3 μm is deposited. A bus bar similar to that in Example 2 above was used. Except for this, the same operation as in Example 6 was repeated to join the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 to the aluminum layers 2c of the wiring metal 2, respectively.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例８）
上記実施例６と同様の両側実装した半導体装置を作製するに際し、銅合金に厚さ５０μｍのアルミニウム系金属がクラッドされ、この表面に微細凹凸２ｒを同様に形成した板材から成る配線金属２を備えた上記実施例３と同様のバスバーを用いた。これ以外は、上記実施例６と同様の操作を繰り返すことによって、半導体チップ３の両面に備えたアルミニウム層３ｃを配線金属２のアルミニウム層２ｃにそれぞれ接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。(Example 8)
When producing a semiconductor device mounted on both sides similar to that of Example 6, a copper metal is clad with an aluminum-based metal having a thickness of 50 μm and a wiring metal 2 made of a plate material in which fine irregularities 2r are similarly formed is provided on this surface. The same bus bar as in Example 3 was used. Except for this, the same operation as in Example 6 was repeated to join the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 to the aluminum layers 2c of the wiring metal 2, respectively.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例９）
上記半導体チップ３に、上記実施例４で用いたセラミックス基板、すなわち表面に同様の微細凹凸２ｒを有する厚さ５００μｍのアルミニウム系金属製の配線金属２を備えた厚さ６３５μｍのＡｌＮから成るセラミックス基板を両側実装した半導体装置を作製した（図５（ｄ）参照）。すなわち、密着層３ａ、バリヤ層３ｂ、アルミニウム層３ｃを両面に備えた半導体チップ３の両側に、同様のインサート材４を介して上記セラミックス基板をそれぞれ配置し、同様の操作を繰り返すことによって、半導体チップ３の両面に備えたアルミニウム層３ｃをアルミニウム系金属製配線金属２にそれぞれ接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。Example 9
A ceramic substrate made of AlN having a thickness of 635 μm provided with a ceramic substrate used in the above-mentioned embodiment 4 on the semiconductor chip 3, that is, a wiring metal 2 made of aluminum-based metal having a thickness of 500 μm having the same fine irregularities 2 r on the surface. Was fabricated on both sides (see FIG. 5D). In other words, the ceramic substrate is disposed on both sides of the semiconductor chip 3 having the adhesion layer 3a, the barrier layer 3b, and the aluminum layer 3c on both sides through the same insert material 4, and the same operation is repeated. The aluminum layers 3c provided on both surfaces of the chip 3 were joined to the aluminum metal wiring metal 2, respectively.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（実施例１０）
上記実施例９と同様の両側実装した半導体装置を作製するに際し、上記実施例５で用いたセラミックス基板、すなわち厚さ５００μｍの銅合金製であって、その接合面に微細凹凸２ｒを同様に形成した後、厚さ３μｍのアルミニウム層２ｃを蒸着した配線金属２を備えたセラミックス基板を使用した。これ以外は、上記実施例９と同様の操作を繰り返して、半導体チップ３の両面に備えたアルミニウム層３ｃを配線金属２のアルミニウム層２ｃにそれぞれ接合した。
その結果、Ｐｂフリー、低コスト、強度バラツキが少ない、高温強度、長期信頼性に優れた実装ダイボンド構造を同様に得ることができた。(Example 10)
When producing a semiconductor device mounted on both sides similar to that in Example 9, the ceramic substrate used in Example 5 above, that is, made of a copper alloy having a thickness of 500 μm, is similarly formed with fine irregularities 2r on the joint surface. Then, a ceramic substrate provided with a wiring metal 2 on which an aluminum layer 2c having a thickness of 3 μm was deposited was used. Except for this, the same operation as in Example 9 was repeated, and the aluminum layers 3 c provided on both surfaces of the semiconductor chip 3 were joined to the aluminum layer 2 c of the wiring metal 2, respectively.
As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.

（比較例１）
銅合金から成る配線金属２を備えたバスバーを使用し、厚さ１７０μｍのＳｉから成るＩＧＢＴ（半導体チップ）３を片側実装した半導体装置を作製した（図５（ａ）参照）。 このとき、上記ＩＧＢＴ（半導体チップ）３の接合面側には、はんだの濡れ性向上のために、厚さ０．５μｍのチタン密着層３ａと、厚さ１μｍのニッケルバリヤ層３ｂを介して、最表層に銀を１μｍの厚さに成膜した。また、配線金属２の接合面にも、同様の目的で、厚さ５μｍのニッケル層を介して銀を１μｍの厚さに成膜した。(Comparative Example 1)
Using a bus bar provided with a wiring metal 2 made of a copper alloy, a semiconductor device in which an IGBT (semiconductor chip) 3 made of Si having a thickness of 170 μm was mounted on one side was manufactured (see FIG. 5A). At this time, on the joint surface side of the IGBT (semiconductor chip) 3, in order to improve the wettability of the solder, a titanium adhesion layer 3 a having a thickness of 0.5 μm and a nickel barrier layer 3 b having a thickness of 1 μm are provided. A silver film having a thickness of 1 μm was formed on the outermost layer. Further, for the same purpose, a silver film having a thickness of 1 μm was formed on the joint surface of the wiring metal 2 through a nickel layer having a thickness of 5 μm.

そして、Ｐｂ−Ｓｎはんだを用いて、配線金属２と半導体チップ３とをろう付けした。
なお、接合後のはんだの厚さは２００μｍであった。
当該比較例１においては、Ｐｂ（鉛）を含有するはんだを使用しているため、環境保全を観点とする社会要請にそぐわない。また、はんだの融点が１８４℃であって高温耐久性に乏しい。さらに、接合界面に金属間化合物層やカーケンダルボイドの生成が認められ、長期信頼性にも乏しいことが判明した。And the wiring metal 2 and the semiconductor chip 3 were brazed using Pb-Sn solder.
In addition, the thickness of the solder after joining was 200 micrometers.
In the comparative example 1, since the solder containing Pb (lead) is used, it does not meet social demands from the viewpoint of environmental protection. Further, the melting point of the solder is 184 ° C., and the high temperature durability is poor. Furthermore, it was found that intermetallic compound layers and Kirkendall voids were formed at the bonding interface, and the long-term reliability was poor.

（比較例２）
図５（ａ）に示すような片側実装した半導体装置を作製するに際し、Ｓｎ−Ａｇ−Ｃｕはんだを用いたこと以外は、上記比較例１と同様の操作を繰り返して、配線金属２と半導体チップ３とをろう付けした。
当該比較例２においては、Ｓｎ−Ａｇ−Ｃｕはんだは、上記Ｐｂ−Ｓｎはんだに比べて融点が２１０〜２１７℃と高いものの、将来型パワーモジュールに適用するには、高温耐久信頼性にも乏しい。また、Ｐｂ−Ｓｎはんだ同様に、界面に金属間化合物層やカーケンダルボイドが生成することがあり、長期信頼性にも乏しい。(Comparative Example 2)
When manufacturing a semiconductor device mounted on one side as shown in FIG. 5A, the same operation as in Comparative Example 1 was repeated except that Sn—Ag—Cu solder was used, and the wiring metal 2 and the semiconductor chip were used. 3 was brazed.
In Comparative Example 2, Sn—Ag—Cu solder has a melting point as high as 210 to 217 ° C. compared to the Pb—Sn solder, but it is poor in high-temperature durability reliability to be applied to future type power modules. . Further, like the Pb—Sn solder, an intermetallic compound layer or a Kirkendall void may be generated at the interface, and the long-term reliability is poor.

（比較例３）
図５（ａ）に示すような片側実装した半導体装置を作製するに際し、有機分子が粒子の表面を修飾した銀ナノ粒子を用いたこと以外は、上記比較例１と同様の操作を繰り返して、配線金属２と半導体チップ３とを接合した。
銀ナノ粒子による接合は、ナノ粒子表面に修飾した有機分子が接合プロセスでガス化する際にボイドを発生させたり、粒子の凝集にバラツキが生じたりすることから、継手強度にバラツキが生じることが判明した。また、貴金属であるＡｇを使っていることや、有機分子を修飾させるという複雑な構造をとっているため、高コストであり、量産には不向きと言える。(Comparative Example 3)
When producing a semiconductor device mounted on one side as shown in FIG. 5 (a), the same operation as in Comparative Example 1 was repeated, except that silver nanoparticles whose organic molecules modified the surface of the particles were used, The wiring metal 2 and the semiconductor chip 3 were joined.
Bonding with silver nanoparticles may cause voids when organic molecules modified on the surface of the nanoparticles are gasified during the bonding process, and there may be variations in particle aggregation, resulting in variations in joint strength. found. In addition, since it uses Ag, which is a noble metal, and has a complicated structure that modifies organic molecules, it is expensive and unsuitable for mass production.

（比較例４）
図５（ａ）に示すような片側実装した半導体装置を作製するに際し、Ａｇ−Ｇｅはんだを使用したこと以外は、上記比較例１と同様の操作を繰り返して、配線金属２と半導体チップ３とをろう付けした。
Ａｇ−Ｇｅはんだは、貴金属であるＡｕを含んでいるため、高コストであり、量産を伴う産業上の用途には向かない。また、上記Ｐｂ−ＳｎはんだやＳｎ−Ａｇ−Ｃｕはんだと同様に、接合界面に金属間化合物層を生成したり、カーケンダルボイドを生成したりするため、長期信頼性も乏しい。(Comparative Example 4)
When producing a semiconductor device mounted on one side as shown in FIG. 5A, the same operation as in Comparative Example 1 was repeated except that Ag—Ge solder was used, and the wiring metal 2 and the semiconductor chip 3 Brazed.
Since Ag—Ge solder contains Au, which is a noble metal, it is expensive and unsuitable for industrial applications involving mass production. Further, similarly to the Pb—Sn solder and Sn—Ag—Cu solder, since an intermetallic compound layer is generated at the joint interface or a Kirkendall void is generated, long-term reliability is poor.

以上の本実施例と比較例における材料や構造の組合せを表１に纏めて示す。   Table 1 shows a combination of materials and structures in the present example and the comparative example.

Figure 0005733466
Figure 0005733466

１ 半導体装置
２ 配線金属
２ｒ 微細凹凸
２ｆ 酸化皮膜
３ 半導体チップ
３ｃ アルミニウム層（アルミニウム系金属）
３ｆ 酸化皮膜
４ インサート材
１２ 絶縁性セラミックス基材DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Wiring metal 2r Fine unevenness 2f Oxide film 3 Semiconductor chip 3c Aluminum layer (aluminum metal)
3f Oxide film 4 Insert material 12 Insulating ceramic substrate

Claims (9)

半導体チップの接合面に備えたアルミニウム系金属と、配線金属の少なくとも接合面に備えたアルミニウム系金属との間に、Ａｌと共晶反応を生じるＺｎを主成分とする金属を含むインサート材を介在させると共に、上記アルミニウム系金属表面の酸化皮膜を破壊するための微細凹凸を上記接合面及びインサート材表面の少なくとも一部に設け、上記半導体チップと配線金属を相対的に加圧しつつＡｌと上記インサート材との共晶反応が生じる温度に加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップと配線金属のアルミニウム系金属同士を直接接合することを特徴とする半導体装置の製造方法。 An insert material containing a metal mainly composed of Zn that causes a eutectic reaction with Al is interposed between the aluminum-based metal provided on the bonding surface of the semiconductor chip and the aluminum-based metal provided on at least the bonding surface of the wiring metal. In addition, fine irregularities for breaking the oxide film on the surface of the aluminum-based metal are provided on at least a part of the bonding surface and the surface of the insert material, and Al and the insert are pressed while relatively pressing the semiconductor chip and the wiring metal. Heating to a temperature at which a eutectic reaction with the material occurs , discharging the eutectic reaction melt produced at the bonding interface together with the oxide film, and at least part of the bonding interface between the semiconductor chip and the aluminum metal of the wiring metal A method for manufacturing a semiconductor device, characterized in that: 上記インサート材がＺｎと、Ｚｎと共晶反応を生じる金属との合金であることを特徴とする請求項１に記載の製造方法。   2. The manufacturing method according to claim 1, wherein the insert material is an alloy of Zn and a metal that causes a eutectic reaction with Zn. 上記インサート材がＺｎ及びＡｌ、Ｚｎ及びＭｇ、Ｚｎ及びＣｕ、Ｚｎ及びＳｎ、Ｚｎ及びＡｇ、Ｚｎ及びＭｇ及びＡｌ、Ｚｎ及びＣｕ及びＡｌ、Ｚｎ及びＳｎ及びＡｌ、又はＺｎ及びＡｇ及びＡｌを主成分とする合金であることを特徴とする請求項１に記載の製造方法。   The insert material is mainly Zn and Al, Zn and Mg, Zn and Cu, Zn and Sn, Zn and Ag, Zn and Mg and Al, Zn and Cu and Al, Zn and Sn and Al, or Zn and Ag and Al. The manufacturing method according to claim 1, wherein the alloy is an alloy as a component. 配線金属が絶縁性セラミックス基板上に配置されていることを特徴とする請求項１〜３のいずれか１つの項に記載の製造方法。 The manufacturing method according to any one of claims 1 to 3 , wherein the wiring metal is disposed on an insulating ceramic substrate. 上記絶縁性セラミックス基板の反半導体チップ側に備えた配線金属をベースプレート上に接合するに際して、少なくとも接合面にアルミニウム系金属を備えた上記配線金属とベースプレートの間に、Ａｌと共晶反応を生じるＺｎを主成分とする金属を含むインサート材を介在させると共に、上記アルミニウム系金属表面の酸化皮膜を破壊するための微細凹凸を上記接合面及びインサート材表面の少なくとも一部に設け、上記配線金属とベースプレートを相対的に加圧しつつＡｌと上記インサート材との共晶反応が生じる温度に加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して接合することを特徴とする請求項４に記載の製造方法。 Zn that causes a eutectic reaction with Al between the wiring metal provided with an aluminum-based metal at least on the bonding surface and the base plate when bonding the wiring metal provided on the anti-semiconductor chip side of the insulating ceramic substrate to the base plate In addition to interposing an insert material containing a metal containing as a main component , fine irregularities for breaking the oxide film on the surface of the aluminum-based metal are provided on at least a part of the bonding surface and the surface of the insert material, and the wiring metal and the base plate while applying relatively pressurized heated to a temperature at which the eutectic reaction takes place between Al and the insert material, the eutectic reaction melt generated in the bonding interface, characterized in that bonding is discharged together with the oxide film claims Item 5. The production method according to Item 4 . 上記配線金属とベースプレート双方の接合面に微細凹凸を設けることを特徴とする請求項４に記載の製造方法。 5. The manufacturing method according to claim 4 , wherein fine irregularities are provided on the joint surfaces of both the wiring metal and the base plate. 配線金属がアルミニウム系金属、又は銅系金属から成る基材の表面にアルミニウム系金属を配置して成るものであることを特徴とする請求項１〜６のいずれか１つの項に記載の製造方法。 The manufacturing method according to any one of claims 1 to 6 , wherein the wiring metal is formed by arranging an aluminum-based metal on a surface of a base material made of an aluminum-based metal or a copper-based metal. . 半導体チップの接合面に備えたアルミニウム系金属と、配線金属の少なくとも接合面に備えたアルミニウム系金属との間に、Ａｌと共晶反応を生じるＺｎを主成分とする金属を含むインサート材を介在させると共に、上記アルミニウム系金属表面の酸化皮膜を破壊するための微細凹凸を上記接合面及びインサート材表面の少なくとも一部に設け、上記半導体チップと配線金属を相対的に加圧しつつＡｌと上記インサート材との共晶反応が生じる温度に加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップと配線金属のアルミニウム系金属同士を直接接合して成ることを特徴とする半導体装置。 An insert material containing a metal mainly composed of Zn that causes a eutectic reaction with Al is interposed between the aluminum-based metal provided on the bonding surface of the semiconductor chip and the aluminum-based metal provided on at least the bonding surface of the wiring metal. In addition, fine irregularities for breaking the oxide film on the surface of the aluminum-based metal are provided on at least a part of the bonding surface and the surface of the insert material, and Al and the insert are pressed while relatively pressing the semiconductor chip and the wiring metal. Heating to a temperature at which a eutectic reaction with the material occurs , discharging the eutectic reaction melt produced at the bonding interface together with the oxide film, and at least part of the bonding interface between the semiconductor chip and the aluminum metal of the wiring metal A semiconductor device characterized by being joined directly. 半導体チップと配線金属とが接合されて成る半導体装置であって、
上記半導体チップはアルミニウム系金属を接合面に備え、
上記配線金属は、少なくとも接合面にアルミニウム系金属を備え、
上記半導体チップと配線金属のアルミニウム系金属同士が、接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＡｌとＺｎの共晶組成物と、Ａｌの酸化物を含む排出物が介在していることを特徴とする半導体装置。 A semiconductor device formed by bonding a semiconductor chip and a wiring metal,
The semiconductor chip includes an aluminum-based metal on the bonding surface,
The wiring metal includes an aluminum-based metal at least on the bonding surface,
The semiconductor chip and the aluminum metal of the wiring metal are directly bonded to each other at at least a part of the bonding interface, and an eutectic composition containing Al and Zn and an oxide of Al are formed around the direct bonding portion. A semiconductor device characterized by being interposed.
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