JP5726377B2 - Solar cell and manufacturing method thereof - Google Patents

Solar cell and manufacturing method thereof Download PDF

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JP5726377B2
JP5726377B2 JP2014512507A JP2014512507A JP5726377B2 JP 5726377 B2 JP5726377 B2 JP 5726377B2 JP 2014512507 A JP2014512507 A JP 2014512507A JP 2014512507 A JP2014512507 A JP 2014512507A JP 5726377 B2 JP5726377 B2 JP 5726377B2
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thin film
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古畑　武夫
武夫 古畑
幹雄 山向
幹雄 山向
友宏 品川
友宏 品川
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02E10/00—Energy generation through renewable energy sources
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    • Y02E10/548—Amorphous silicon PV cells

Description

本発明は、太陽電池及びその製造方法に係り、特に結晶系半導体基板と非晶質半導体層との接合構造に関する。   The present invention relates to a solar cell and a manufacturing method thereof, and more particularly to a junction structure between a crystalline semiconductor substrate and an amorphous semiconductor layer.

従来、結晶系半導体基板と非晶質半導体層との間で接合を形成した構造の太陽電池技術が開示されている。このような太陽電池では、発電層として結晶系半導体基板を用い、基板の両側の真性非晶質半導体層で基板表面でのキャリアの再結合を低減し、さらにその両側の導電型半導体層で高い内蔵電界を形成することで、光電変換効率の向上をはかっている。   Conventionally, a solar cell technology in which a junction is formed between a crystalline semiconductor substrate and an amorphous semiconductor layer has been disclosed. In such a solar cell, a crystalline semiconductor substrate is used as a power generation layer, carrier recombination on the substrate surface is reduced by the intrinsic amorphous semiconductor layers on both sides of the substrate, and the conductive semiconductor layers on both sides are high. By forming a built-in electric field, the photoelectric conversion efficiency is improved.

特許文献１では、真性非晶質半導体層を２層構造とし、基板側から外側に向かって順に光学的バンドギャップを広げた構成をとる。これにより、真性非晶質半導体層で発生する光吸収を減らすとしている。   In Patent Document 1, an intrinsic amorphous semiconductor layer has a two-layer structure, and an optical band gap is increased in order from the substrate side to the outside. Thereby, light absorption generated in the intrinsic amorphous semiconductor layer is reduced.

特許第３４９０９６４号公報Japanese Patent No. 3490964

しかしながら、上記従来の技術によっても十分な光電変換効率を得ることは困難であり、さらなる光電変換効率の向上が求められている。   However, it is difficult to obtain sufficient photoelectric conversion efficiency even by the above conventional technique, and further improvement in photoelectric conversion efficiency is demanded.

本発明は、上記に鑑みてなされたもので、基板上の導電型半導体層における光吸収を低減することで、光吸収損失を低減し、光電変換効率の高い太陽電池を得ることを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to reduce a light absorption loss by reducing light absorption in a conductive semiconductor layer on a substrate and obtain a solar cell with high photoelectric conversion efficiency. .

上述した課題を解決し、目的を達成するために、本発明の太陽電池は、片面に凹凸構造を有する一導電型の結晶系シリコン基板上に、凹凸構造を有する片面に接するように真性シリコン系薄膜層と、導電型結晶系シリコン系薄膜層とが順次積層された太陽電池であって、真性シリコン系薄膜層は、結晶系シリコン基板側から順に非晶質層と結晶系層の２層を備え、導電型結晶系シリコン系薄膜層に接するように凹凸構造の凸部に選択的に形成され、導電型結晶系シリコン系薄膜層の結晶化率より高い導電型結晶系シリコン系薄膜層からなるキャップ層を備えている。そして、導電型結晶系シリコン系薄膜層は、真性シリコン系薄膜層と接する部分において隣接する真性シリコン系薄膜層より結晶化率が低いことを特徴としている。 To solve the above problems and achieve the object, a solar cell of the present invention, the one conductivity type crystalline silicon substrate having an uneven structure on one side, an intrinsic silicon in contact with the one surface having the uneven structure and the thin film layer, a solar cell conductivity type crystalline silicon-based thin film layer and are sequentially stacked, a true silicon-based thin film layer, two layers of the crystalline silicon substrate side and an amorphous layer are sequentially crystal-based layer From the conductive crystalline silicon thin film layer that is selectively formed on the convex portion of the concavo-convex structure so as to be in contact with the conductive crystalline silicon thin film layer and has a higher crystallization rate than the conductive crystalline silicon thin film layer. A cap layer is provided. The conductivity-type crystalline silicon-based thin film layer is characterized in that the crystallization rate is lower than the true silicon-based thin film layer you adjacent in a portion which is in contact with the true silicon-based thin film layer.

本発明によれば、２層構造の真性シリコン系薄膜層のうちの結晶系層と接することによって導電型結晶系シリコン系薄膜層の結晶化が容易となる。また、前記導電型結晶系シリコン系薄膜層は、前記真性シリコン系薄膜層と接する部分において隣接する前記真性シリコン系薄膜層より結晶化率が低くなるようにすることで、バンドギャップ差の増大を抑制でき、界面での欠陥の発生を抑制可能となる。従って、本発明の構造を有する太陽電池によれば、導電型シリコン系薄膜層の結晶性を高めることができ、光吸収の低減が可能となり、光電変換効率を向上することができるという効果を奏する。   According to the present invention, the conductive crystal silicon thin film layer can be easily crystallized by being in contact with the crystal layer of the intrinsic silicon thin film layer having a two-layer structure. In addition, the conductivity type crystalline silicon thin film layer has a lower crystallization rate than the adjacent intrinsic silicon thin film layer in a portion in contact with the intrinsic silicon thin film layer, thereby increasing the band gap difference. It is possible to suppress the occurrence of defects at the interface. Therefore, according to the solar cell having the structure of the present invention, the crystallinity of the conductive silicon thin film layer can be increased, light absorption can be reduced, and the photoelectric conversion efficiency can be improved. .

図１は、本発明の実施の形態１の太陽電池を示す模式的断面図である。FIG. 1 is a schematic cross-sectional view showing the solar cell according to Embodiment 1 of the present invention. 図２は、微結晶シリコン層のラマンスペクトルの一例を示す図である。FIG. 2 is a diagram illustrating an example of a Raman spectrum of a microcrystalline silicon layer. 図３は、アモルファスシリコン層のラマンスペクトルの一例を示す図である。FIG. 3 is a diagram illustrating an example of a Raman spectrum of an amorphous silicon layer. 図４−１は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-1 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. FIGS. 図４−２は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-2 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. FIGS. 図４−３は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-3 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. FIGS. 図４−４は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-4 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. 図４−５は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-5 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. 図４−６は、本発明の実施の形態１の太陽電池を示す工程断面図である。FIGS. 4-6 is process sectional drawing which shows the solar cell of Embodiment 1 of this invention. 図５は、本発明の実施の形態１の太陽電池の製造工程を示すフローチャートである。FIG. 5 is a flowchart showing manufacturing steps of the solar cell according to Embodiment 1 of the present invention. 図６は、本発明にかかる実施の形態１の比較例の太陽電池を示す模式的断面図である。FIG. 6 is a schematic cross-sectional view showing a solar cell of a comparative example of the first embodiment according to the present invention. 図７は、真性シリコン層とそれに接するｐ型のシリコン層の結晶化率の関係を示す図である。FIG. 7 is a diagram showing the relationship between the crystallization ratios of the intrinsic silicon layer and the p-type silicon layer in contact therewith. 図８は、本発明にかかる実施の形態１の太陽電池の各層の結晶化率を示す図である。FIG. 8 is a diagram showing the crystallization ratio of each layer of the solar cell according to the first embodiment of the present invention. 図９は、本発明にかかる実施の形態２の太陽電池を示す模式的断面図を示す図である。FIG. 9: is a figure which shows typical sectional drawing which shows the solar cell of Embodiment 2 concerning this invention. 図１０は、本発明にかかる実施の形態３の太陽電池を示す模式的断面図を示す図である。FIG. 10: is a figure which shows typical sectional drawing which shows the solar cell of Embodiment 3 concerning this invention. 図１１は、本発明にかかる実施の形態４の太陽電池を示す模式的断面図を示す図である。FIG. 11: is a figure which shows typical sectional drawing which shows the solar cell of Embodiment 4 concerning this invention. 図１２−１は、本発明にかかる実施の形態４の太陽電池の製造工程を示す要部拡大断面図である。12-1 is a principal part expanded sectional view which shows the manufacturing process of the solar cell of Embodiment 4 concerning this invention. 図１２−２は、本発明にかかる実施の形態４の太陽電池の製造工程を示す要部拡大断面図である。FIG. 12-2 is an enlarged cross-sectional view of a relevant part showing the manufacturing process of the solar cell according to the fourth embodiment of the present invention. 図１３は、本発明にかかる実施の形態４の太陽電池の凸部に形成された各層の結晶化率の関係を示す図である。FIG. 13: is a figure which shows the relationship of the crystallization rate of each layer formed in the convex part of the solar cell of Embodiment 4 concerning this invention. 図１４は、本発明にかかる実施の形態４の太陽電池を上からみた時に、凸部に形成したｎ型微結晶シリコン層が基板を占める領域を示す図である。FIG. 14 is a diagram showing a region in which the n-type microcrystalline silicon layer formed on the convex portion occupies the substrate when the solar cell according to the fourth embodiment of the present invention is viewed from above. 図１５は、本発明にかかる実施の形態４の太陽電池の特性を示す図である。FIG. 15 is a diagram showing characteristics of the solar cell according to the fourth embodiment of the present invention. 図１６−１は、本発明にかかる実施の形態５の太陽電池を示す模式的断面図を示す図である。FIG. 16-1 is a schematic cross-sectional view showing the solar cell according to the fifth embodiment of the present invention. 図１６−２は、本発明にかかる実施の形態５の太陽電池を示す要部拡大断面図である。FIG. 16-2 is an essential part enlarged cross-sectional view showing the solar cell according to the fifth embodiment of the present invention. 図１７は、本発明にかかる実施の形態５の太陽電池の凸部に形成された各層の結晶化率の関係を示す図である。FIG. 17 is a diagram showing the relationship between the crystallization ratios of the respective layers formed on the convex portion of the solar cell according to the fifth embodiment of the present invention. 図１８は、本発明にかかる実施の形態５の太陽電池の凸部以外の領域に形成された各層の結晶化率の関係を示す図である。FIG. 18 is a diagram showing the relationship between the crystallization ratios of the respective layers formed in a region other than the convex portion of the solar cell according to the fifth embodiment of the present invention.

以下に、本発明にかかる太陽電池及びその製造方法の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。また、以下の実施の形態で用いられる太陽電池の断面図は模式的なものであり、層の厚みと幅との関係や各層の厚みの比率などは現実のものとは異なる場合もある。   Embodiments of a solar cell and a method for manufacturing the solar cell according to the present invention will be described below in detail based on the drawings. Note that the present invention is not limited to the embodiments. In addition, the cross-sectional views of the solar cell used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thickness of each layer, and the like may be different from the actual ones.

実施の形態１．
図１は、本発明にかかる太陽電池の実施の形態１の模式的断面図である。以下、図１を参照して本実施の形態１の太陽電池について説明する。この太陽電池１０は、一導電型の結晶系シリコン基板として、ｎ型の単結晶シリコン基板１１を用いる。本実施の形態１の太陽電池は、ｎ型の単結晶シリコン基板１１と接するように、非晶質層としての真性の非晶質シリコン層１２と、結晶系層としての真性の微結晶シリコン層１３とが順次積層され、この上層に導電型結晶系シリコン系薄膜層として、ホウ素（Ｂ）をドープしたｐ型の微結晶シリコン層１４を有することを特徴とする。ここで、ホウ素(Ｂ)の代わりにＡｌをドープしたｐ型の微結晶シリコン層でもよい。そしてこのｐ型の微結晶シリコン層１４上には透光性電極１５が形成され、表面には銀層からなる集電電極１６が形成されている。一方、ｎ型の単結晶シリコン基板１１の裏面側については、真性の非晶質シリコン層１７、ｎ型の非晶質シリコン層１８が順次積層されている。そして裏面側についてもこのｎ型の非晶質シリコン層１８上には透光性電極２５が形成されている。なお、真性の非晶質シリコン層１７とｎ型の非晶質シリコン層１８からＢＳＦ（Ｂａｃｋ Ｓｕｒｆａｃｅ Ｆｉｅｌｄ）領域が形成される。その外側に反射層1９を備えており、この反射層１９上に裏面側の集電電極２６が設けられる。Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view of a first embodiment of a solar cell according to the present invention. Hereinafter, the solar cell of the first embodiment will be described with reference to FIG. This solar cell 10 uses an n-type single crystal silicon substrate 11 as a single conductivity type crystalline silicon substrate. The solar cell of the first embodiment includes an intrinsic amorphous silicon layer 12 as an amorphous layer and an intrinsic microcrystalline silicon layer as a crystalline layer so as to be in contact with the n-type single crystal silicon substrate 11. And a p-type microcrystalline silicon layer 14 doped with boron (B) as a conductive crystalline silicon-based thin film layer. Here, instead of boron (B), a p-type microcrystalline silicon layer doped with Al may be used. A translucent electrode 15 is formed on the p-type microcrystalline silicon layer 14, and a collecting electrode 16 made of a silver layer is formed on the surface. On the other hand, on the back side of the n-type single crystal silicon substrate 11, an intrinsic amorphous silicon layer 17 and an n-type amorphous silicon layer 18 are sequentially stacked. A translucent electrode 25 is also formed on the n-type amorphous silicon layer 18 on the back side. A BSF (Back Surface Field) region is formed from the intrinsic amorphous silicon layer 17 and the n-type amorphous silicon layer 18. A reflective layer 19 is provided on the outer side, and a collecting electrode 26 on the back side is provided on the reflective layer 19.

ここで、ｎ型の単結晶シリコン基板１１としてはインゴットからスライスにより切り出されたものを用いる。切断面は研磨され表面の平坦化がなされている。さらに、切断面には結晶のひずみが残っているため、ＨＦ＋ＨＮＯ3やＮａＯＨなどを用いて表面を１０〜２０μｍ程度エッチングする。また、ゲッタリングにより基板内の不純物を除去することが好ましい。ゲッタリングには、リンを熱拡散し、形成されたリンガラス層に不純物を偏析させる方法がある。Here, as the n-type single crystal silicon substrate 11, a substrate cut out from an ingot is used. The cut surface is polished and the surface is flattened. Further, since crystal distortion remains on the cut surface, the surface is etched by about 10 to 20 μm using HF + HNO 3 or NaOH. Further, it is preferable to remove impurities in the substrate by gettering. In gettering, there is a method in which phosphorus is thermally diffused and impurities are segregated in the formed phosphorus glass layer.

また、ｎ型の単結晶シリコン基板１１はｐ型の単結晶シリコン基板でもよい。また、結晶系シリコン基板としては、ｎ型の多結晶シリコン基板表面に所望の厚さのｎ型の単結晶シリコン層を形成した基板あるいはｎ型の多結晶シリコン基板など、少なくとも表面が一導電型の結晶系シリコン層を構成するものであればよい。   The n-type single crystal silicon substrate 11 may be a p-type single crystal silicon substrate. In addition, as the crystalline silicon substrate, at least the surface has one conductivity type, such as a substrate in which an n-type single crystal silicon layer having a desired thickness is formed on an n-type polycrystalline silicon substrate surface or an n-type polycrystalline silicon substrate. Any material may be used as long as it constitutes the crystalline silicon layer.

反射防止あるいは散乱による基板内の光路長の増大のため、基板表面に凹凸（テクスチャー）が形成されていることが好ましい。テクスチャーは、単結晶シリコン基板の（１００）面を用いて、（１００）面と（１１１）面のエッチングレートが異なることを利用した異方性エッチングによって形成できる。薬液にはアルカリ溶液及び添加剤を用い、アルカリ溶液には水酸化カリウム、水酸化ナトリウム等を、添加剤にはイソプロピルアルコール等を用いる。   In order to increase the optical path length in the substrate due to antireflection or scattering, it is preferable that irregularities (textures) are formed on the substrate surface. The texture can be formed by anisotropic etching using the (100) plane of the single crystal silicon substrate and utilizing the different etching rates of the (100) plane and the (111) plane. An alkaline solution and an additive are used for the chemical solution, potassium hydroxide, sodium hydroxide and the like are used for the alkaline solution, and isopropyl alcohol and the like are used for the additive.

ｎ型の単結晶シリコン基板１１の光入射側つまり受光面側に、真性非晶質シリコン系薄膜層として真性の非晶質シリコン層１２を備える。真性の非晶質シリコン層１２は基板表面の欠陥を修復し光電変換効率を向上することができる。この真性の非晶質シリコン層１２が結晶化すると、表面の欠陥の修復効果の低下やこの膜自体の欠陥の増加により、光電変換効率を低下させるため、ｎ型の単結晶シリコン基板１１に接する真性のシリコン層には非晶質層を用いる。   An intrinsic amorphous silicon layer 12 is provided as an intrinsic amorphous silicon thin film layer on the light incident side of the n-type single crystal silicon substrate 11, that is, on the light receiving surface side. The intrinsic amorphous silicon layer 12 can repair defects on the substrate surface and improve photoelectric conversion efficiency. When this intrinsic amorphous silicon layer 12 is crystallized, it is in contact with the n-type single crystal silicon substrate 11 in order to reduce the photoelectric conversion efficiency due to a reduction in the repair effect of surface defects and an increase in defects in the film itself. An amorphous layer is used as the intrinsic silicon layer.

そして、この真性の非晶質シリコン層１２の上に真性の結晶系シリコン系薄膜層として真性の微結晶シリコン層１３を備える。ラマン分光法で微結晶シリコン層を測定すると、単結晶シリコン基板と同様に結晶のピーク（５２０ｃｍ-1）が見られる。微結晶シリコンは、膜中に結晶を含み結晶のピークがみられることから結晶系に分類する。Then, an intrinsic microcrystalline silicon layer 13 is provided on the intrinsic amorphous silicon layer 12 as an intrinsic crystalline silicon thin film layer. When a microcrystalline silicon layer is measured by Raman spectroscopy, a crystal peak (520 cm −1 ) is observed as in the case of a single crystal silicon substrate. Microcrystalline silicon is classified into a crystal system because it contains crystals in the film and has a crystal peak.

微結晶シリコンのラマンスペクトルの一例を図２に示す。微結晶シリコンは、非晶質と結晶が混在しているため、結晶のピーク（５２０ｃｍ-1）以外に非晶質のピーク（４８０ｃｍ-1）も見られる。この他、結晶系シリコン系薄膜層としては、単結晶シリコン、多結晶シリコンなどがある。An example of the Raman spectrum of microcrystalline silicon is shown in FIG. In microcrystalline silicon, since amorphous and crystalline are mixed, an amorphous peak (480 cm −1 ) is also observed in addition to the crystalline peak (520 cm −1 ). In addition, examples of the crystalline silicon thin film layer include single crystal silicon and polycrystalline silicon.

ピーク強度の求め方を以下に述べる。４００ｃｍ-1と５５０ｃｍ-1の測定点を結び、これをベースラインとし、ベースラインに対して、４８０ｃｍ-1付近の非晶質のピーク強度及び５２０ｃｍ-1付近の結晶のピーク強度を、それぞれＩａ、Ｉｃとする。結晶化率をこのピーク強度比Ｉｃ／Ｉａで定義する。The method for obtaining the peak intensity is described below. Conclusion The measurement points 400 cm -1 and 550 cm -1, which was used as a baseline, the base line, the amorphous peak intensity of the crystalline peak intensity and 520cm around -1 around 480 cm -1, respectively Ia , Ic. The crystallization rate is defined by this peak intensity ratio Ic / Ia.

非晶質シリコンのラマンスペクトルの一例を図３に示す。非結晶シリコンは、非晶質のピークが４８０ｃｍ-1に見られ、ピーク幅が広いために５２０ｃｍ-1に強度として観測される。このため、この場合、結晶化率Ｉｃ／Ｉａは０．２となり、非晶質シリコンでも、結晶化率Ｉｃ／Ｉａは０より高い値を示す場合がある。An example of the Raman spectrum of amorphous silicon is shown in FIG. In amorphous silicon, an amorphous peak is observed at 480 cm −1 , and since the peak width is wide, an intensity is observed at 520 cm −1 . For this reason, in this case, the crystallization rate Ic / Ia is 0.2, and the crystallization rate Ic / Ia may be higher than 0 even in amorphous silicon.

その上に、導電型の結晶系シリコン薄膜層としてｐ型の微結晶シリコン層１４を備える。ｐ型の微結晶シリコン層１４の上には、透光性電極１５を備え、この上に集電電極１６が設けられている。   Further, a p-type microcrystalline silicon layer 14 is provided as a conductive crystalline silicon thin film layer. A translucent electrode 15 is provided on the p-type microcrystalline silicon layer 14, and a current collecting electrode 16 is provided thereon.

次に、このような太陽電池１０の製造方法について図４−１〜図４−６を参照して説明する。図５は、実施の形態１にかかる太陽電池１０の製造工程を示すフローチャートである。   Next, a method for manufacturing such a solar cell 10 will be described with reference to FIGS. FIG. 5 is a flowchart showing manufacturing steps of the solar cell 10 according to the first embodiment.

まず、主面の面方位が（１００）で、リン(Ｐ)を含有するｎ型の単結晶シリコン基板１１を用意した（図４−１）。ｎ型の単結晶シリコン基板１１の大きさは、１０ｃｍ×１０ｃｍ〜２０ｃｍ×２０ｃｍ程度で、厚みが１３０〜２００μｍ程度である。アルカリ溶液中に浸漬してｎ型の単結晶シリコン基板１１の表面をエッチングし、スライス時のワイヤーソーダメージを除去する。断面には結晶のひずみが残っているため、ＨＦ＋ＨＮＯ3やＮａＯＨなどを用いて表面を１０〜２０μｍ程度エッチングする。First, an n-type single crystal silicon substrate 11 having a main surface of (100) and containing phosphorus (P) was prepared (FIG. 4A). The n-type single crystal silicon substrate 11 has a size of about 10 cm × 10 cm to 20 cm × 20 cm and a thickness of about 130 to 200 μm. The surface of the n-type single crystal silicon substrate 11 is etched by dipping in an alkaline solution to remove wire saw damage during slicing. Since crystal distortion remains in the cross section, the surface is etched by about 10 to 20 μm using HF + HNO 3 or NaOH.

また、ゲッタリングにより基板内の不純物を除去した後、光閉じ込め構造により反射損失を低減するため、テクスチャー構造の凹凸が形成される。テクスチャー構造の凹凸を形成する方法としてイソプロピルアルコールを含有したアルカリ溶液を用いる（ステップＳ１）。   In addition, after removing impurities in the substrate by gettering, unevenness of the texture structure is formed in order to reduce reflection loss by the light confinement structure. An alkali solution containing isopropyl alcohol is used as a method for forming textured irregularities (step S1).

また、ここではワイヤーソーダメージにおける金属汚染の影響を減らすためにワイヤーソーダメージ除去工程後にテクスチャーを形成したが、ワイヤーソーにおける金属汚染の影響が少ない場合には、ワイヤーソーダメージの除去とテクスチャーの形成とを兼ねてもよい。この場合は、ワイヤーソーダメージ除去を行うことなくｎ型の単結晶シリコン基板１１を、イソプロピルアルコールを含有したアルカリ溶液でエッチングを行うことにより、ワイヤーソーダメージの除去とテクスチャーの形成とを兼ねることができる。また、テクスチャー構造の形成方法としては、反応性イオンエッチング（ＲＩＥ）法等のドライエッチングによって形成してもよい。   Also, here, the texture was formed after the wire saw damage removal process to reduce the influence of metal contamination on the wire saw damage, but when the influence of metal contamination on the wire saw is small, the removal of the wire saw damage and the formation of the texture. It may also serve as. In this case, by removing the n-type single crystal silicon substrate 11 with an alkaline solution containing isopropyl alcohol without removing the wire saw damage, the wire saw damage can be removed and the texture can be formed. it can. Moreover, as a formation method of a texture structure, you may form by dry etching, such as the reactive ion etching (RIE) method.

次に、ｎ型の単結晶シリコン基板１１をＲＣＡ洗浄によりクリーニングし、製膜直前に希フッ酸で表面酸化膜除去を施し、１３．５６〜６０ＭＨｚのプラズマＣＶＤチャンバで、プラズマＣＶＤ法により、真性の非晶質シリコン層１２（ステップＳ２（図４−２））及び真性の微結晶シリコン層１３（ステップＳ３（図４−３））を受光面側に順次形成した。真性の非晶質シリコン層１２は、プラズマＣＶＤ法により、ＳｉＨ4 ガス流量６０ｓｃｃｍ、Ｈ2 ガス６０ｓｃｃｍとし、圧力１００Ｐａ、基板温度１７０℃、及びＲＦパワー３０Ｗの条件で形成される。膜厚は３ｎｍである。なお、膜厚は１ｎｍ以上１０ｎｍ以下が好ましい。真性の微結晶シリコン層１３は、プラズマＣＶＤ法により、ＳｉＨ4 ガス流量１０ｓｃｃｍ、Ｈ2 ガス流量１０００ｓｃｃｍ、圧力２００Ｐａ、基板温度１７０℃、及びＲＦパワー２００Ｗの条件で形成される。Next, the n-type single crystal silicon substrate 11 is cleaned by RCA cleaning, the surface oxide film is removed with dilute hydrofluoric acid immediately before the film formation, and the intrinsic property is obtained by plasma CVD in a 13.56-60 MHz plasma CVD chamber. The amorphous silicon layer 12 (step S2 (FIG. 4-2)) and the intrinsic microcrystalline silicon layer 13 (step S3 (FIG. 4-3)) were sequentially formed on the light receiving surface side. The intrinsic amorphous silicon layer 12 is formed by a plasma CVD method under conditions of SiH 4 gas flow rate of 60 sccm, H 2 gas of 60 sccm, pressure of 100 Pa, substrate temperature of 170 ° C., and RF power of 30 W. The film thickness is 3 nm. The film thickness is preferably 1 nm or more and 10 nm or less. The intrinsic microcrystalline silicon layer 13 is formed by plasma CVD under the conditions of SiH 4 gas flow rate 10 sccm, H 2 gas flow rate 1000 sccm, pressure 200 Pa, substrate temperature 170 ° C., and RF power 200 W.

その結晶化率をラマン分光法で評価した。非晶質のピーク（４８０ｃｍ-1付近）Ｉａに対する結晶のピーク（５２０ｃｍ-1付近）Ｉｃの比で結晶化率を表すとＩｃ／Ｉａ＝２．０であった。なお、結晶化率の評価はすべて、太陽電池の作製中に基板上に実際に形成した膜を測定した。表面から深さ数ｎｍの範囲に集光して測定を行った。膜厚は４ｎｍである。なお、膜厚は、１ｎｍ以上１０ｎｍ以下が好ましい。The crystallization rate was evaluated by Raman spectroscopy. When the crystallization ratio was expressed by the ratio of the crystal peak (near 520 cm −1 ) Ic to the amorphous peak (near 480 cm −1 ) Ia, Ic / Ia = 2.0. In addition, all evaluation of the crystallization rate measured the film | membrane actually formed on the board | substrate during preparation of a solar cell. Measurement was conducted by focusing light from the surface to a depth of several nanometers. The film thickness is 4 nm. The film thickness is preferably 1 nm or more and 10 nm or less.

こののち、ｐ型の微結晶シリコン層１４をプラズマＣＶＤ法により、形成する（ステップＳ４（図４−４））。製膜条件は、ＳｉＨ4ガス流量１０ｓｃｃｍ、Ｈ2ガス流量１０００ｓｃｃｍ、Ｂ2Ｈ6ガス（１％Ｈ2 ベース）流量２ｓｃｃｍ、圧力２００Ｐａ、基板温度１７０℃、及びＲＦパワー２００Ｗの条件とする。膜厚は４ｎｍである。なお、１ｎｍ以上１０ｎｍ以下が好ましい。光吸収を減らすためにｐ型シリコン層の膜厚は、Ｖoc、フィルファクターＦＦを低下させずに薄くすることが好ましい。Thereafter, a p-type microcrystalline silicon layer 14 is formed by plasma CVD (step S4 (FIG. 4-4)). The film forming conditions are as follows: SiH 4 gas flow rate 10 sccm, H 2 gas flow rate 1000 sccm, B 2 H 6 gas (1% H 2 base) flow rate 2 sccm, pressure 200 Pa, substrate temperature 170 ° C., and RF power 200 W. The film thickness is 4 nm. In addition, 1 nm or more and 10 nm or less are preferable. In order to reduce light absorption, it is preferable to reduce the thickness of the p-type silicon layer without lowering Voc and fill factor FF.

このとき、膜の結晶化率は、Ｉｃ／Ｉａ＝１．５であった。従来、ｐ型シリコン層の製膜初期は特に非晶質になりやすく、薄膜のｐ型シリコン層の結晶化率を増加させるのが難しいという問題があった。しかし、比較的容易に作製可能な膜である、真性の微結晶シリコン層１３を下地に形成することで、薄膜のｐ型の微結晶シリコン層１４を得ることができた。これは、下地の結晶成分が結晶核となって、その上に堆積する膜の結晶化を促進することができるからである。これにより、ｐ型の非晶質シリコンより光吸収の少ないｐ型の微結晶シリコン膜を形成することができ、その結果、光電変換効率を向上できる。   At this time, the crystallization ratio of the film was Ic / Ia = 1.5. Conventionally, there has been a problem in that the p-type silicon layer is likely to be amorphous in the initial stage, and it is difficult to increase the crystallization rate of the thin p-type silicon layer. However, a thin p-type microcrystalline silicon layer 14 can be obtained by forming an intrinsic microcrystalline silicon layer 13, which is a film that can be manufactured relatively easily, as a base. This is because the underlying crystal component serves as a crystal nucleus and can promote crystallization of a film deposited thereon. Accordingly, a p-type microcrystalline silicon film that absorbs less light than p-type amorphous silicon can be formed, and as a result, photoelectric conversion efficiency can be improved.

次に、裏面側の真性の非晶質シリコン層１７（ステップＳ５）、ｎ型の非晶質シリコン層１８を順次積層する（ステップＳ６（図４−５））。ここで真性の非晶質シリコン層１７は、プラズマＣＶＤ法により、ＳｉＨ4ガス流量６０ｓｃｃｍ、Ｈ2 ガス流量６０ｓｃｃｍ、圧力１００Ｐａ、基板温度１７０℃、及びＲＦパワー３０Ｗの条件で形成している。膜厚は４ｎｍである。なお、１ｎｍ〜１０ｎｍの範囲が好ましい。Next, an intrinsic amorphous silicon layer 17 on the back surface side (step S5) and an n-type amorphous silicon layer 18 are sequentially stacked (step S6 (FIG. 4-5)). Here, the intrinsic amorphous silicon layer 17 is formed by plasma CVD under the conditions of SiH 4 gas flow rate 60 sccm, H 2 gas flow rate 60 sccm, pressure 100 Pa, substrate temperature 170 ° C., and RF power 30 W. The film thickness is 4 nm. In addition, the range of 1 nm-10 nm is preferable.

ｎ型の非晶質シリコン膜１８は、プラズマＣＶＤ法により、ＳｉＨ4ガス流量４０ｓｃｃｍ、ＰＨ3ガス（２％Ｈ2ベース）流量２０ｓｃｃｍ、圧力１００Ｐａ、基板温度１７０℃、ＲＦパワー３０Ｗの条件で形成している。膜厚は２０ｎｍである。１ｎｍ〜４０ｎｍの範囲が好ましい。The n-type amorphous silicon film 18 is formed by plasma CVD under the conditions of SiH 4 gas flow rate of 40 sccm, PH 3 gas (2% H 2 base) flow rate of 20 sccm, pressure of 100 Pa, substrate temperature of 170 ° C., and RF power of 30 W. doing. The film thickness is 20 nm. A range of 1 nm to 40 nm is preferable.

次に、受光面側に透光性電極１５を形成する（ステップＳ７）。透光性電極１５としては、透光性の導電性酸化膜が用いられる。スパッタリング法により、酸化インジウム錫（ＩＴＯ）が形成される。形成条件は、基板温度１８０℃、Ａｒガス流量７０ｓｃｃｍ、Ｏ2 ガス流量（５％Ａｒベース）５ｓｃｃｍ、圧力０．７Ｐａ、ＲＦパワー８００Ｗの条件で形成され、その膜厚は１００ｎｍである。なお、透光性電極１５の膜厚としては、光閉じ込めの観点から６０ｎｍ〜１２０ｎｍの膜厚とするのが好ましい。Next, the translucent electrode 15 is formed on the light receiving surface side (step S7). As the translucent electrode 15, a translucent conductive oxide film is used. Indium tin oxide (ITO) is formed by sputtering. The formation conditions are a substrate temperature of 180 ° C., an Ar gas flow rate of 70 sccm, an O 2 gas flow rate (5% Ar base) of 5 sccm, a pressure of 0.7 Pa, and an RF power of 800 W, and the film thickness is 100 nm. In addition, as a film thickness of the translucent electrode 15, it is preferable to set it as a film thickness of 60 nm-120 nm from a viewpoint of optical confinement.

このほか、透光性電極１５としては、ＳｎＯ2、Ｉｎ2Ｏ3、ＺｎＯ、ＣｄＯ、ＣｄＩｎ2Ｏ4、ＣｄＳｎＯ3、ＭｇＩｎ2Ｏ4、ＣｄＧａ2Ｏ4、ＧａＩｎＯ3、ＩｎＧａＺｎＯ4、Ｃｄ2Ｓｂ2Ｏ7、Ｃｄ2ＧｅＯ4、ＣｕＡｌＯ2、ＣｕＧａＯ2、ＳｒＣｕ2Ｏ2、ＴｉＯ2、Ａｌ2Ｏ3などを使用することができ、またこれらを積層して形成した透光性導電膜を使用することもできる。また、ドーパントとしては、Ａｌ、Ｇａ、Ｉｎ、Ｂ、Ｙ、Ｓｉ、Ｚｒ、Ｔｉ、Ｆ、Ｃｅから選択した１種類以上の元素を用いてもよい。形成方法として、これ以外に、蒸着、イオンプレーティングなどがある。In addition, as the transparent electrode 15, SnO 2, In 2 O 3, ZnO, CdO, CdIn 2 O 4, CdSnO 3, MgIn 2 O 4, CdGa 2 O 4, GaInO 3, InGaZnO 4, Cd 2 Sb 2 O 7 , Cd 2 GeO 4 , CuAlO 2 , CuGaO 2 , SrCu 2 O 2 , TiO 2 , Al 2 O 3, etc. can be used, and a translucent conductive film formed by laminating these is used. You can also As the dopant, one or more elements selected from Al, Ga, In, B, Y, Si, Zr, Ti, F, and Ce may be used. Other forming methods include vapor deposition and ion plating.

続いて、裏面側に透光性電極２５を形成する（ステップＳ８（図４−６））。透光性電極２５は、透光性導電性酸化膜が用いられ、スパッタリング法により、酸化インジウム錫（ＩＴＯ）が形成される。透光性電極２５は、光に対し基板の裏面側に位置するため透光性電極１５より短波長側の光の透過性は低くてもよく、より長波長側の光の吸収を減らすような膜を選択することが好ましい。形成方法、形成材料は透光性電極１５で記載した内容と同様のものが考えられる。   Subsequently, the translucent electrode 25 is formed on the back side (step S8 (FIGS. 4-6)). The translucent electrode 25 uses a translucent conductive oxide film, and indium tin oxide (ITO) is formed by a sputtering method. Since the translucent electrode 25 is located on the back side of the substrate with respect to the light, the transmissivity of the light on the short wavelength side may be lower than that of the translucent electrode 15, and the absorption of the light on the longer wavelength side is reduced. It is preferred to select a membrane. The formation method and the formation material may be the same as those described for the translucent electrode 15.

こののち、裏面側の透光性電極２５上に反射層１９を形成する（ステップＳ９）。反射層１９は、入射した光をより有効活用するために形成することが好ましい。スパッタリングにより形成したＡｇ層を用いる。このほか、反射層１９としては、蒸着などで形成してもよいし、材料としてＡｌを用いてもよい。   After that, the reflective layer 19 is formed on the translucent electrode 25 on the back side (step S9). The reflective layer 19 is preferably formed in order to make more effective use of incident light. An Ag layer formed by sputtering is used. In addition, the reflective layer 19 may be formed by vapor deposition or the like, or Al may be used as a material.

このほか、金属酸化物の微粒子からなる白色高反射材料を用いてもよい。例えば、ＭｇＯ、Ａｌ2Ｏ3、白色亜鉛などがある。この場合、当該材料が絶縁体であるため、透光性電極２５の上に集電電極２６を形成した後に反射層１９が形成される。In addition, a white highly reflective material made of metal oxide fine particles may be used. For example, there are MgO, Al 2 O 3 and white zinc. In this case, since the material is an insulator, the reflective layer 19 is formed after the collector electrode 26 is formed on the translucent electrode 25.

そして受光面側の集電電極１６、裏面側の集電電極２６が順次受光面側及び裏面側に形成される（ステップＳ１０，ステップＳ１１）。集電電極１６、２６は、インクジェット、スクリーン印刷、銅線接着、スプレーなどによって形成される。生産性の観点からスクリーン印刷が好ましい。スクリーン印刷は、Ａｇなどの金属粒子と樹脂バインダーからなる導電ペーストを用いて形成される。   The current collecting electrode 16 on the light receiving surface side and the current collecting electrode 26 on the back surface side are sequentially formed on the light receiving surface side and the back surface side (step S10, step S11). The collecting electrodes 16 and 26 are formed by inkjet, screen printing, copper wire bonding, spraying, or the like. Screen printing is preferable from the viewpoint of productivity. Screen printing is formed using a conductive paste made of metal particles such as Ag and a resin binder.

以上のようにして図１に示した太陽電池１０が得られる。この太陽電池を実施例１とする。   The solar cell 10 shown in FIG. 1 is obtained as described above. This solar cell is referred to as Example 1.

ここで、比較例として、図６に示すような構造の太陽電池を作製した。本実施の形態では、ｎ型の単結晶シリコン基板１１上に形成した、膜厚７ｎｍの真性の非晶質シリコン層１２の上にｐ型のシリコン層を前記実施の形態１の太陽電池１０と同じ条件で製膜した。この時、ｐ型のシリコン層は、結晶化せずにｐ型の非晶質シリコン層２４が形成された。   Here, as a comparative example, a solar cell having a structure as shown in FIG. 6 was produced. In the present embodiment, a p-type silicon layer is formed on the 7-nm thick intrinsic amorphous silicon layer 12 formed on the n-type single crystal silicon substrate 11 and the solar cell 10 of the first embodiment. A film was formed under the same conditions. At this time, the p-type silicon layer was not crystallized, and the p-type amorphous silicon layer 24 was formed.

表１に、実施例１の太陽電池と比較例の太陽電池について、太陽電池のＪＶ特性である、開放電圧Ｖoc及び短絡電流Ｊsc、フィルファクターＦＦを測定した結果を示す。   Table 1 shows the results of measuring the open-circuit voltage Voc, the short-circuit current Jsc, and the fill factor FF, which are the JV characteristics of the solar cell, for the solar cell of Example 1 and the solar cell of the comparative example.

さらに、実施例２として、真性の微結晶シリコン層１３の製膜条件において、Ｈ2流量を２０００ｓｃｃｍに変えて形成した。この時の結晶化率がＩｃ／Ｉａ＝３．０であった。Further, as Example 2, the intrinsic microcrystalline silicon layer 13 was formed by changing the H 2 flow rate to 2000 sccm under the film forming conditions. The crystallization rate at this time was Ic / Ia = 3.0.

次に、この上に、ｐ型の微結晶シリコン層を実施例１と同じ製膜条件で形成した。この結晶化率がＩｃ／Ｉａ＝２．５であった。   Next, a p-type microcrystalline silicon layer was formed thereon under the same film forming conditions as in Example 1. The crystallization rate was Ic / Ia = 2.5.

さらに、実施例３として、Ｈ2流量を３０００ｓｃｃｍに変えて形成した。この時の結晶化率がＩｃ／Ｉａ＝４．０であった。次に、この上に、ｐ型の微結晶シリコン層を実施例１と同じ製膜条件で形成した。この結晶化率がＩｃ／Ｉａ＝３．０であった。Further, as Example 3, the H 2 flow rate was changed to 3000 sccm. The crystallization rate at this time was Ic / Ia = 4.0. Next, a p-type microcrystalline silicon layer was formed thereon under the same film forming conditions as in Example 1. The crystallization rate was Ic / Ia = 3.0.

ここで、真性シリコン層の結晶化率とこの上に形成されたｐ型シリコン層の結晶化率の関係を図７に示す。図７において、真性非晶質シリコン層の結晶化率Ｉｃ／Ｉａが０．２であった。それに接してｐ型シリコン層を実施例１と同じ条件で形成すると、この結晶化率Ｉｃ／Ｉａも０．２で、これも非晶質であった。また、真性シリコン層の結晶化率の増加に伴い、ｐ型シリコン層の結晶化率が増加し結晶化が促進されている。なお、非晶質の結晶化率Ｉｃ／Ｉａが０．２と、０より高い値を示すのは、既に記載し図３に示した通り、非晶質の４８０ｃｍ-1のピークが５２０ｃｍ-1のところまで及んでいるためである。FIG. 7 shows the relationship between the crystallization rate of the intrinsic silicon layer and the crystallization rate of the p-type silicon layer formed thereon. In FIG. 7, the crystallization rate Ic / Ia of the intrinsic amorphous silicon layer was 0.2. When a p-type silicon layer was formed in contact therewith under the same conditions as in Example 1, the crystallization rate Ic / Ia was 0.2, which was also amorphous. Further, with the increase in the crystallization rate of the intrinsic silicon layer, the crystallization rate of the p-type silicon layer is increased and the crystallization is promoted. Note that the amorphous crystallization ratio Ic / Ia is 0.2, which is higher than 0, as already described and shown in FIG. 3, the amorphous 480 cm −1 peak is 520 cm −1. It is because it has extended to the place.

実施例２，３の太陽電池について、ＪＶ特性を測定した結果を表１に示す。   Table 1 shows the results of measuring the JV characteristics of the solar cells of Examples 2 and 3.

Figure 0005726377
Figure 0005726377

表１から明らかなように、比較例に比べ、実施例１の太陽電池は、短絡電流（Ｊsc）が向上し、光電変換効率が高められている。また、実施例１〜３の結果から明らかなように、ｐ型シリコン層の結晶化率の増加に伴い、Ｊscが向上し、光電変換効率が向上している。   As is apparent from Table 1, the solar cell of Example 1 has improved short circuit current (Jsc) and increased photoelectric conversion efficiency as compared with the comparative example. Further, as is apparent from the results of Examples 1 to 3, Jsc is improved and the photoelectric conversion efficiency is improved as the crystallization rate of the p-type silicon layer is increased.

すなわち、真性の非晶質シリコン層上に真性の微結晶シリコン層を形成することで、その上のｐ型シリコン層を結晶化させることができ、その結果、ｐ型シリコン層の光吸収が低減でき光電変換効率の向上をはかることができた。   That is, by forming an intrinsic microcrystalline silicon layer on an intrinsic amorphous silicon layer, the p-type silicon layer thereon can be crystallized, and as a result, light absorption of the p-type silicon layer is reduced. It was possible to improve the photoelectric conversion efficiency.

また、真性シリコン層の結晶化率Ｉｃ／Ｉａを２．０から４．０の範囲で制御し、ｐ型シリコン層の結晶化率Ｉｃ／Ｉａを１．５から３．０の範囲で制御することで、Ｊsc及び光電変換効率を向上できるため、この範囲に結晶化率を制御することが好ましい。なお、ｐ型シリコン層の結晶化率を制御するには、ｐ型シリコン層の製膜条件において、ＳｉＨ4ガス流量、Ｈ2ガス流量、Ｂ2Ｈ6ガス流量、圧力、基板温度、及びＲＦパワーを調整することで可能である。例えば、ＳｉＨ4ガス流量を減らす、Ｈ2ガス流量を増やす、Ｂ2Ｈ6ガス流量を減らす、圧力を上げる、基板温度を上げる、及びＲＦパワーを上げる方向で結晶化率を上げることができる。なお、ｐ型シリコン層の膜厚は、１ｎｍ以上１０ｎｍ以下が好ましい。Further, the crystallization rate Ic / Ia of the intrinsic silicon layer is controlled in the range of 2.0 to 4.0, and the crystallization rate Ic / Ia of the p-type silicon layer is controlled in the range of 1.5 to 3.0. Thus, since Jsc and photoelectric conversion efficiency can be improved, it is preferable to control the crystallization rate within this range. In order to control the crystallization rate of the p-type silicon layer, the SiH 4 gas flow rate, the H 2 gas flow rate, the B 2 H 6 gas flow rate, the pressure, the substrate temperature, and the RF are used under the conditions for forming the p-type silicon layer. This is possible by adjusting the power. For example, the crystallization rate can be increased by decreasing the SiH 4 gas flow rate, increasing the H 2 gas flow rate, decreasing the B 2 H 6 gas flow rate, increasing the pressure, increasing the substrate temperature, and increasing the RF power. The thickness of the p-type silicon layer is preferably 1 nm or more and 10 nm or less.

なお、さらに真性シリコン層の結晶化率をあげようとすると、製膜時の水素流量をさらに増やす必要があり、この場合、製膜時のダメージにより光電変換効率が低下する懸念がある。   In order to further increase the crystallization rate of the intrinsic silicon layer, it is necessary to further increase the hydrogen flow rate during film formation. In this case, there is a concern that the photoelectric conversion efficiency is lowered due to damage during film formation.

次に、結晶化率Ｉｃ／Ｉａ＝２．０の真性の微結晶シリコン層を実施例１と同様の製膜条件で形成し、この上に、ｐ型の微結晶シリコン層を、より結晶化率の高いｐ型の微結晶シリコン層を形成するため、製膜条件のＨ2流量を４０００ｓｃｃｍに変えて形成した。この時、ｐ型の微結晶シリコン層の結晶化率Ｉｃ／Ｉａ＝３．０が得られた。これを用いて、太陽電池を作製した。これを実施例４とし、その結果を表１に示す。Next, an intrinsic microcrystalline silicon layer having a crystallization ratio Ic / Ia = 2.0 is formed under the same film forming conditions as in Example 1, and a p-type microcrystalline silicon layer is further crystallized thereon. In order to form a p-type microcrystalline silicon layer with a high rate, it was formed by changing the H 2 flow rate under the film forming conditions to 4000 sccm. At this time, the crystallization ratio Ic / Ia = 3.0 of the p-type microcrystalline silicon layer was obtained. Using this, a solar cell was produced. This is Example 4 and the results are shown in Table 1.

実施例４の太陽電池の場合、比較例の太陽電池に比べ、Ｊsc、変換効率は増加するが、Ｖocの低下が見られるため、実施例３の太陽電池に比べて変換効率は低下する。これは、真性の微結晶シリコン層より高い結晶化率のｐ型の微結晶シリコン層を用いたためである。   In the case of the solar cell of Example 4, although Jsc and conversion efficiency increase compared with the solar cell of a comparative example, since the fall of Voc is seen, conversion efficiency falls compared with the solar cell of Example 3. This is because a p-type microcrystalline silicon layer having a higher crystallization rate than the intrinsic microcrystalline silicon layer is used.

原因として、ｐ型シリコン層の結晶化率の増加に伴い、ｐ型シリコン層のバンドギャップは狭くなり、この結果、ｐ型の微結晶シリコン膜と、これに接する真性の微結晶シリコン層とのバンドギャップ差が拡大し、両者の界面での欠陥が増加したと考えられる。言い換えれば、真性の微結晶シリコン層より低い結晶化率のｐ型の微結晶シリコン層を形成することで両者のバンドギャップを等しくすることができ、両者の界面での欠陥を低減できる。   As a cause, as the crystallization rate of the p-type silicon layer increases, the band gap of the p-type silicon layer becomes narrower. As a result, the p-type microcrystalline silicon film and an intrinsic microcrystalline silicon layer in contact with the p-type silicon layer It is considered that the band gap difference has expanded and defects at the interface between the two have increased. In other words, by forming a p-type microcrystalline silicon layer with a crystallization rate lower than that of the intrinsic microcrystalline silicon layer, the band gap between the two can be made equal, and defects at the interface between the two can be reduced.

従って、ｐ型の微結晶シリコン層は、真性の微結晶シリコン層より低い結晶化率を有することで、光電変換効率の高い太陽電池を得ることができる。真性の非晶質シリコン層からｐ型シリコン層までの結晶化率の関係を図８に示す。図８に示すように、結晶化率ＣＲ＝Ｉｃ／Ｉａは、真性の非晶質シリコン層１２の結晶化率をＣＲia、真性の微結晶シリコン層１３の結晶化率をＣＲic、ｐ型の微結晶シリコン層１４の結晶化率をＣＲpcとしたとき、ＣＲia＜ＣＲic＞ＣＲpcとなっている。このように、真性の非晶質シリコン層１２から真性の微結晶シリコン層１３で結晶性が高くなり、この真性の微結晶シリコン層１３よりもやや結晶性が低下したｐ型の微結晶シリコン層１４を形成することで、光電変換効率の高い太陽電池を得ることができる。Therefore, the p-type microcrystalline silicon layer has a lower crystallization rate than the intrinsic microcrystalline silicon layer, whereby a solar cell with high photoelectric conversion efficiency can be obtained. FIG. 8 shows the relationship of the crystallization rate from the intrinsic amorphous silicon layer to the p-type silicon layer. As shown in FIG. 8, the crystallization rate CR = Ic / Ia is such that the crystallization rate of the intrinsic amorphous silicon layer 12 is CR ia , the crystallization rate of the intrinsic microcrystalline silicon layer 13 is CR ic , and p-type. When the crystallization rate of the microcrystalline silicon layer 14 is CR pc , CR ia <CR ic > CR pc . Thus, the p-type microcrystalline silicon layer whose crystallinity is higher from the intrinsic amorphous silicon layer 12 to the intrinsic microcrystalline silicon layer 13 and whose crystallinity is slightly lower than that of the intrinsic microcrystalline silicon layer 13. By forming 14, a solar cell with high photoelectric conversion efficiency can be obtained.

以上のように、本実施の形態の太陽電池によれば、真性シリコン系薄膜層を、単結晶シリコン基板側から順に非晶質層と結晶系層の２層構造とし、導電型シリコン系薄膜層の下地となる真性シリコン系薄膜層を微結晶化した結晶系層としている。これは真性シリコン系薄膜層の方が結晶化しやすいため、まず真性シリコン系薄膜層を結晶化し、この結晶化した真性層上に導電型の結晶系層を形成している。特にｐ型の導電型シリコン系薄膜層としてホウ素（Ｂ）をドープしたシリコン層は、低温で微結晶化することが困難であるが、本実施の形態のように、下地となる真性シリコン系薄膜層を微結晶化し結晶系層としたため、ホウ素（Ｂ）をドープしたシリコン層（導電型シリコン系薄膜層）の結晶化が促進され、その結果、光吸収が低減し光電変換効率が向上する。   As described above, according to the solar cell of the present embodiment, the intrinsic silicon thin film layer has a two-layer structure of an amorphous layer and a crystal layer in order from the single crystal silicon substrate side, and a conductive silicon thin film layer. The intrinsic silicon-based thin film layer that is the base of the substrate is a crystallized layer that is microcrystallized. Since the intrinsic silicon thin film layer is easier to crystallize, the intrinsic silicon thin film layer is first crystallized, and a conductive crystalline layer is formed on the crystallized intrinsic layer. In particular, a silicon layer doped with boron (B) as a p-type conductive silicon-based thin film layer is difficult to be microcrystallized at a low temperature. However, as in this embodiment, an intrinsic silicon-based thin film serving as a base is used. Since the layer is microcrystallized into a crystalline layer, crystallization of the boron (B) -doped silicon layer (conducting silicon thin film layer) is promoted, and as a result, light absorption is reduced and photoelectric conversion efficiency is improved.

また、本実施の形態１の太陽電池の製造方法によれば、前述したように、ｎ型の単結晶シリコン基板１１上に、真性の非晶質シリコン層１２を形成する工程、その上に、真性の微結晶シリコン層１３を形成する工程、その上に、ｐ型の微結晶シリコン層１４を形成する工程を備える。そして次に、ｎ型の単結晶シリコン基板１１の反対側つまり裏面側に、真性の非晶質シリコン層１７を形成する工程、この上にｎ型の非晶質シリコン層１８を形成する工程、を備える。   Further, according to the method for manufacturing the solar cell of the first embodiment, as described above, the step of forming the intrinsic amorphous silicon layer 12 on the n-type single crystal silicon substrate 11, A step of forming intrinsic microcrystalline silicon layer 13 and a step of forming p-type microcrystalline silicon layer 14 thereon are provided. Then, a step of forming an intrinsic amorphous silicon layer 17 on the opposite side of the n-type single crystal silicon substrate 11, that is, a back side, a step of forming an n-type amorphous silicon layer 18 thereon, Is provided.

これにより、ｐ型の微結晶シリコン層１４をより効率よく結晶化させることができ、その結果、光吸収の低減をはかることができ、光電変換効率を向上することができる。   Thereby, the p-type microcrystalline silicon layer 14 can be crystallized more efficiently. As a result, light absorption can be reduced and the photoelectric conversion efficiency can be improved.

実施の形態２．
次に、実施の形態２の太陽電池について説明する。図９は、実施の形態２の太陽電池を示す模式的断面図である。本実施の形態においては、実施の形態１に示した太陽電池１０において、ｐ型の微結晶シリコン層１４と透光性電極１５の間に、ｐ型の非晶質シリコン層３４を追加したものである。ここでｐ型の微結晶シリコン層１４の膜厚を３ｎｍ、ｐ型の非晶質シリコン層３４の膜厚を１ｎｍとし、ｐ型導電性層全体の膜厚は実施例１と同様４ｎｍとした。他の構成については前記実施の形態１の太陽電池と同様であるため、ここでは説明を省略する。同一部位には同一符号を付した。また、ＪＶ特性の結果を実施例５として表１に示す。表１に示すように、実施例５は、比較例や実施例１に比べて、太陽電池特性のフィルファクターＦＦが増加し光電変換効率が向上している。Embodiment 2. FIG.
Next, the solar cell of Embodiment 2 is demonstrated. FIG. 9 is a schematic cross-sectional view showing the solar cell of the second embodiment. In the present embodiment, the solar cell 10 shown in the first embodiment is obtained by adding a p-type amorphous silicon layer 34 between the p-type microcrystalline silicon layer 14 and the translucent electrode 15. It is. Here, the thickness of the p-type microcrystalline silicon layer 14 is 3 nm, the thickness of the p-type amorphous silicon layer 34 is 1 nm, and the thickness of the entire p-type conductive layer is 4 nm as in the first embodiment. . Since other configurations are the same as those of the solar cell of the first embodiment, description thereof is omitted here. The same symbols are assigned to the same parts. The results of JV characteristics are shown in Table 1 as Example 5. As shown in Table 1, in Example 5, the fill factor FF of solar cell characteristics is increased and the photoelectric conversion efficiency is improved as compared with the comparative example and Example 1.

実施例１の太陽電池に比べて、実施例５の太陽電池のフィルファクターＦＦが増加したのは抵抗を低減した効果によるもので、抵抗が低減する理由は、ｐ型シリコン層と透光性電極の間のコンタクト抵抗が、ｐ型の非晶質シリコン層３４を介在させることによって低減できるからである。これは、ｐ型の非晶質シリコン層３４はｐ型の微結晶シリコン層１４より酸化されにくく、透光性電極形成時に製膜室に存在する酸素元素による酸化、あるいは透光性電極を構成する酸素の拡散による酸化を、ｐ型の非晶質シリコン層３４で低減できるからである。   Compared with the solar cell of Example 1, the increase in the fill factor FF of the solar cell of Example 5 is due to the effect of reducing the resistance. The reason for the reduction of the resistance is the p-type silicon layer and the translucent electrode. This is because the contact resistance can be reduced by interposing the p-type amorphous silicon layer 34. This is because the p-type amorphous silicon layer 34 is less likely to be oxidized than the p-type microcrystalline silicon layer 14, and is formed by oxidation by oxygen elements existing in the film forming chamber at the time of forming the translucent electrode, or constituting the translucent electrode. This is because oxidation due to diffusion of oxygen can be reduced by the p-type amorphous silicon layer 34.

また、比較例の太陽電池よりも実施例５の太陽電池のフィルファクターＦＦが増加している理由は、ｐ型の微結晶シリコン層１４の方がｐ型の非晶質シリコン層２４より膜自身の導電率が高いため、これを反映して太陽電池における抵抗が低減したためである。   The reason why the fill factor FF of the solar cell of Example 5 is larger than that of the solar cell of the comparative example is that the p-type microcrystalline silicon layer 14 is more film than the p-type amorphous silicon layer 24 itself. This is because the resistance of the solar cell is reduced to reflect this.

実際、ガラス上にｐ型の微結晶シリコン層とｐ型の非晶質シリコン層とをそれぞれ１０ｎｍ製膜して、膜の導電率を比較すると、それぞれ、１Ｅ−４Ｓ／ｃｍ、１Ｅ−５Ｓ／ｃｍが得られ、ｐ型の微結晶シリコン層の導電率の方が高いことが分かる。   Actually, when a p-type microcrystalline silicon layer and a p-type amorphous silicon layer are formed on glass to a thickness of 10 nm, and the conductivity of the films is compared, 1E-4S / cm, 1E-5S / cm is obtained, and it can be seen that the conductivity of the p-type microcrystalline silicon layer is higher.

また、本実施の形態２の太陽電池の製造方法によれば、前記実施の形態１の製造方法に加え、ｐ型の微結晶シリコン層１４の形成の後、ｐ型の非晶質シリコン層３４を形成する工程を追加することで容易に形成可能である。つまり、ｎ型の単結晶シリコン基板１１上に、真性の非晶質シリコン層１２を形成する工程、その上に、真性の微結晶シリコン層１３を形成する工程、その上に、ｐ型の微結晶シリコン層１４を形成する工程、ｐ型の非晶質シリコン層３４を形成する工程を備える。そして次に、ｎ型の単結晶シリコン基板１１の反対側つまり裏面側に、真性の非晶質シリコン層１７を形成する工程、この上にｎ型非晶質シリコン層１８を形成する工程、を備えることを特徴とする。   Further, according to the method of manufacturing the solar cell of the second embodiment, in addition to the manufacturing method of the first embodiment, the p-type amorphous silicon layer 34 is formed after the formation of the p-type microcrystalline silicon layer 14. It can be easily formed by adding a step of forming the film. That is, a step of forming an intrinsic amorphous silicon layer 12 on an n-type single crystal silicon substrate 11, a step of forming an intrinsic microcrystalline silicon layer 13 thereon, and a p-type microcrystalline silicon layer 13 thereon. A step of forming the crystalline silicon layer 14 and a step of forming the p-type amorphous silicon layer 34 are provided. Then, a step of forming an intrinsic amorphous silicon layer 17 on the opposite side of the n-type single crystal silicon substrate 11, that is, a back side, and a step of forming an n-type amorphous silicon layer 18 thereon. It is characterized by providing.

これにより、ｐ型微結晶シリコン層をより結晶化させることができ、その結果、光吸収の低減をはかることができ、光電変換効率を向上することができる。更に、透光性電極１５の形成に先立ち、ｐ型の非晶質シリコン層３４を形成することで、透光性電極に接触するｐ型シリコン層の酸化を抑えることができ、その結果、両者の界面のコンタクト抵抗を低減でき、フィルファクターＦＦが向上し光電変換効率の向上をはかることができる。フィルファクターＦＦは、理論出力に対する最大出力の割合を表す数値であって、太陽電池モジュールの品質の目安の一つとされている。理論出力は、開放電圧及び短絡電流の積に相当する。ＦＦは、最大出力が理論出力と同一である場合を最大値１とし、数値が１に近いほど発電効率が高いことを表す。   As a result, the p-type microcrystalline silicon layer can be further crystallized. As a result, light absorption can be reduced, and the photoelectric conversion efficiency can be improved. Further, by forming the p-type amorphous silicon layer 34 prior to the formation of the translucent electrode 15, the oxidation of the p-type silicon layer in contact with the translucent electrode can be suppressed. The contact resistance at the interface can be reduced, the fill factor FF can be improved, and the photoelectric conversion efficiency can be improved. The fill factor FF is a numerical value indicating the ratio of the maximum output to the theoretical output, and is regarded as one of the quality standards of the solar cell module. The theoretical output corresponds to the product of open circuit voltage and short circuit current. FF represents the case where the maximum output is the same as the theoretical output, with the maximum value being 1, and the closer the value is to 1, the higher the power generation efficiency.

上記では両面に真性シリコン系薄膜層と導電型シリコン系薄膜層とが形成された構造について説明したが、真性シリコン系薄膜層と導電型シリコン系薄膜層とが片面のみにある構成としても有効である。   In the above description, the structure in which the intrinsic silicon-based thin film layer and the conductive silicon-based thin film layer are formed on both sides has been described. However, the configuration in which the intrinsic silicon-based thin film layer and the conductive silicon-based thin film layer are only on one side is also effective. is there.

実施の形態３．
図１０は、本発明にかかる太陽電池の実施の形態３の模式的断面図である。以下、図１０を参照して本実施の形態３の太陽電池について説明する。実施の形態３では、光の入射面側にｎ型層を配置した場合について説明する。この太陽電池は、一導電型の結晶系シリコン基板として、ｎ型の単結晶シリコン基板１１を用いる。なお、ｐ型の単結晶シリコン基板でもよい。ｎ型の単結晶シリコン基板１１と接するように、非晶質層としての真性の非晶質シリコン層１７と、結晶系層としての真性の微結晶シリコン層１３とが順次積層され、この上層に導電型結晶系シリコン系薄膜層として、リン（Ｐ）をドープしたｎ型の微結晶シリコン層２８を有する。そしてこのｎ型の微結晶シリコン層２８上には透光性電極１５が形成され、表面には銀層からなる集電電極１６が形成されている。Embodiment 3 FIG.
FIG. 10 is a schematic cross-sectional view of a third embodiment of the solar cell according to the present invention. Hereinafter, the solar cell of the third embodiment will be described with reference to FIG. In Embodiment 3, a case where an n-type layer is disposed on the light incident surface side will be described. In this solar cell, an n-type single crystal silicon substrate 11 is used as a single conductivity type crystalline silicon substrate. A p-type single crystal silicon substrate may be used. An intrinsic amorphous silicon layer 17 as an amorphous layer and an intrinsic microcrystalline silicon layer 13 as a crystalline layer are sequentially stacked so as to be in contact with the n-type single crystal silicon substrate 11. An n-type microcrystalline silicon layer 28 doped with phosphorus (P) is provided as a conductive crystalline silicon-based thin film layer. A translucent electrode 15 is formed on the n-type microcrystalline silicon layer 28, and a collecting electrode 16 made of a silver layer is formed on the surface.

一方、ｎ型の単結晶シリコン基板１１の裏面側については、真性の非晶質シリコン層１２、ｐ型の非晶質シリコン層２４が順次積層されている。その外側には透光性電極２５が形成され、その外側に反射層１９を備えており、この反射層１９上に裏面側の集電電極２６が設けられる。   On the other hand, on the back side of the n-type single crystal silicon substrate 11, an intrinsic amorphous silicon layer 12 and a p-type amorphous silicon layer 24 are sequentially stacked. A translucent electrode 25 is formed on the outer side, and a reflective layer 19 is provided on the outer side. A current collecting electrode 26 on the back side is provided on the reflective layer 19.

ｎ型の微結晶シリコン層２８は、プラズマＣＶＤ法により形成する。製膜条件は、ＳｉＨ4 ガス流量１０ｓｃｃｍ、Ｈ２ガス流量１０００ｓｃｃｍ、ＰＨ3ガス（２％Ｈ2 ベース）流量１ｓｃｃｍ、圧力２００Ｐａ、基板温度１７０℃、ＲＦパワー２００Ｗの条件で形成した。Ｈ２ガス流量、ＲＦパワー、圧力を変えることで結晶化率を調整できる。膜厚は４ｎｍである。なお、１ｎｍ以上１５ｎｍ以下が好ましい。光吸収を減らすためにｎ型微結晶シリコン層２８の膜厚は、Ｖoc、フィルファクターＦＦを低下させない程度に薄くすることが好ましい。The n-type microcrystalline silicon layer 28 is formed by a plasma CVD method. The film forming conditions were as follows: SiH 4 gas flow rate 10 sccm, H 2 gas flow rate 1000 sccm, PH 3 gas (2% H 2 base) flow rate 1 sccm, pressure 200 Pa, substrate temperature 170 ° C., RF power 200 W. The crystallization rate can be adjusted by changing the H 2 gas flow rate, RF power, and pressure. The film thickness is 4 nm. In addition, 1 nm or more and 15 nm or less are preferable. In order to reduce light absorption, it is preferable to reduce the film thickness of the n-type microcrystalline silicon layer 28 to such an extent that Voc and fill factor FF are not lowered.

このとき、ｎ型の微結晶シリコン層２８の結晶化率は、Ｉｃ／Ｉａ＝１．５であった。従来、ｎ型シリコン層の製膜初期は特に非晶質になりやすく、薄膜のｎ型シリコン層の結晶化率を増加させるのが難しいという問題があった。しかし、比較的容易に作製可能な膜である、真性の微結晶シリコン層１３を下地に形成することで、薄膜のｎ型の微結晶シリコン層２８を得ることができた。これは、下地の結晶成分が結晶核となって、その上に堆積する膜の結晶化を促進することができるからである。これにより、ｎ型の非晶質シリコンより光吸収の少ないｎ型の微結晶シリコン膜を形成することができ、その結果、光電変換効率を向上することができる。   At this time, the crystallization ratio of the n-type microcrystalline silicon layer 28 was Ic / Ia = 1.5. Conventionally, there has been a problem that the initial stage of the formation of the n-type silicon layer tends to be amorphous, and it is difficult to increase the crystallization rate of the thin n-type silicon layer. However, a thin n-type microcrystalline silicon layer 28 can be obtained by forming the intrinsic microcrystalline silicon layer 13, which is a film that can be manufactured relatively easily, as a base. This is because the underlying crystal component serves as a crystal nucleus and can promote crystallization of a film deposited thereon. Thus, an n-type microcrystalline silicon film that absorbs less light than n-type amorphous silicon can be formed, and as a result, photoelectric conversion efficiency can be improved.

また、結晶系層としての真性の微結晶シリコン層１３の結晶化率は２．０で、ｎ型の微結晶シリコン膜の結晶化率の方が真性の微結晶シリコン層の結晶化率に比べ低い。これによって、両者のバンドギャップを等しくすることができ、両者の界面での欠陥を低減できる。   In addition, the crystallization rate of the intrinsic microcrystalline silicon layer 13 as a crystalline layer is 2.0, and the crystallization rate of the n-type microcrystalline silicon film is higher than that of the intrinsic microcrystalline silicon layer. Low. Thereby, both band gaps can be equalized, and defects at the interface between the two can be reduced.

このようにして作製した太陽電池を実施例６とし、表２にそのＪＶ特性の結果を示す。表２から明らかなように、比較例に比べ、実施例６の太陽電池は、短絡電流（Ｊsc）が向上し、光電変換効率が高められている。   The solar cell thus fabricated was taken as Example 6, and Table 2 shows the results of the JV characteristics. As apparent from Table 2, the solar cell of Example 6 has improved short circuit current (Jsc) and increased photoelectric conversion efficiency as compared with the comparative example.

なお、裏面のｐ層側にも、実施の形態１の受光面側のｐ層に用いたような、真性の結晶系シリコン層及びｐ型の結晶系シリコン層を用いてもよい。   Note that an intrinsic crystalline silicon layer and a p-type crystalline silicon layer as used for the p-layer on the light-receiving surface side in Embodiment 1 may also be used on the p-layer side on the back surface.

Figure 0005726377
Figure 0005726377

実施の形態４．
図１１は、本発明にかかる太陽電池の実施の形態４の模式的断面図である。図１２−１及び図１２−２は、本発明にかかる実施の形態４の太陽電池の製造工程を示す要部拡大断面図である。図１２−１及び図１２−２では、説明を容易にするために、受光面側の基板表面の凹凸構造（テクスチャー）も拡大して模式的に示した。なお、基板の裏面側は、実施の形態３と同様である。基板の受光面側については、ｎ型の単結晶シリコン基板１１、非晶質層としての真性の非晶質シリコン層１７と、結晶系層としての真性の微結晶シリコン層１３とが順次積層され、実施の形態３の太陽電池の構成と同様、この上に導電型結晶系シリコン系薄膜層として、リン（Ｐ）をドープしたｎ型の微結晶シリコン層２８を有する。Embodiment 4 FIG.
FIG. 11: is typical sectional drawing of Embodiment 4 of the solar cell concerning this invention. 12-1 and 12-2 are principal part expanded sectional views which show the manufacturing process of the solar cell of Embodiment 4 concerning this invention. In FIGS. 12A and 12B, in order to facilitate the description, the uneven structure (texture) on the substrate surface on the light receiving surface side is also schematically illustrated. Note that the back side of the substrate is the same as that of the third embodiment. On the light-receiving surface side of the substrate, an n-type single crystal silicon substrate 11, an intrinsic amorphous silicon layer 17 as an amorphous layer, and an intrinsic microcrystalline silicon layer 13 as a crystalline layer are sequentially laminated. Similar to the configuration of the solar cell of the third embodiment, an n-type microcrystalline silicon layer 28 doped with phosphorus (P) is provided thereon as a conductive crystalline silicon-based thin film layer.

そして、図１２−２に示すように、その上に、凸部にのみ、導電型結晶系シリコン系薄膜層として、リン（Ｐ）をドープしたｎ型の微結晶シリコン層３８からなるキャップ層を有する。ｎ型の微結晶シリコン層３８は、ｎ型の微結晶シリコン層２８より結晶化率が高いという特徴を有する。そしてさらにこの上には、透光性電極１５が形成され、表面には銀層からなる集電電極１６が形成されている。 Then, as shown in FIG. 12-2, a cap layer composed of an n-type microcrystalline silicon layer 38 doped with phosphorus (P) is formed only on the convex portion as a conductive crystalline silicon-based thin film layer. Have. The n-type microcrystalline silicon layer 38 is characterized by a higher crystallization rate than the n-type microcrystalline silicon layer 28. Further, a translucent electrode 15 is formed thereon, and a current collecting electrode 16 made of a silver layer is formed on the surface.

次に、この太陽電池の製造方法について説明する。他の層については通例の方法で形成されるが、ｎ型の微結晶シリコン層２８の凸部にのみ選択的に、リン（Ｐ）をドープしたｎ型の微結晶シリコン層３８を形成する点が特徴である。ここではこのｎ型の微結晶シリコン層３８の形成方法について説明する。実施の形態３の太陽電池の構成と同様、図１２−１に示すように、ｎ型の単結晶シリコン基板１１に、非晶質層としての真性の非晶質シリコン層１７と、結晶系層としての真性の微結晶シリコン層１３とを順次積層する。そして、この上層に導電型結晶系シリコン系薄膜層として、リン（Ｐ）をドープしたｎ型の微結晶シリコン層２８を形成する。   Next, the manufacturing method of this solar cell is demonstrated. The other layers are formed by a usual method, but the n-type microcrystalline silicon layer 38 doped with phosphorus (P) is selectively formed only on the protrusions of the n-type microcrystalline silicon layer 28. Is a feature. Here, a method for forming the n-type microcrystalline silicon layer 38 will be described. Similar to the configuration of the solar cell of Embodiment 3, as shown in FIG. 12A, an n-type single crystal silicon substrate 11 has an intrinsic amorphous silicon layer 17 as an amorphous layer, and a crystalline layer. The intrinsic microcrystalline silicon layer 13 is sequentially laminated. Then, an n-type microcrystalline silicon layer 28 doped with phosphorus (P) is formed as a conductive crystalline silicon-based thin film layer on the upper layer.

そして、図１２−２に示すように、ｎ型の微結晶シリコン層２８の凸部にのみ選択的に、リン（Ｐ）をドープしたｎ型の微結晶シリコン層３８を形成する。製膜条件は、ＳｉＨ4ガス流量６ｓｃｃｍ、Ｈ２ガス流量１０００ｓｃｃｍ、ＰＨ3ガス（２％Ｈ2 ベース）流量１ｓｃｃｍ、圧力２００Ｐａ、基板温度１７０℃、ＲＦパワー２００Ｗの条件で形成している。膜厚は最大で４ｎｍ、これにより凸部にのみ形成される。ここで、ＳｉＨ4ガス流量を６ｓｃｃｍと小さくすることで、凸部にのみ選択的に製膜することができた。このほか、Ｈ2ガス流量を増やす、ＲＦパワーを上げることで凸部にのみ選択的に製膜することができる。また、Ｈ2ガス流量、ＰＨ3ガス流量、圧力、ＲＦパワーなどの製膜条件を調整することでｎ型の微結晶シリコン層３８の結晶化率や凸部を占める割合を制御することができる。Then, as shown in FIG. 12B, an n-type microcrystalline silicon layer 38 doped with phosphorus (P) is selectively formed only on the convex portions of the n-type microcrystalline silicon layer 28. The film forming conditions are as follows: SiH 4 gas flow rate 6 sccm, H 2 gas flow rate 1000 sccm, PH 3 gas (2% H 2 base) flow rate 1 sccm, pressure 200 Pa, substrate temperature 170 ° C., RF power 200 W. The film thickness is 4 nm at maximum, thereby forming only the convex part. Here, by reducing the SiH 4 gas flow rate to 6 sccm, it was possible to selectively form a film only on the convex portion. In addition, it is possible to selectively form a film only on the convex portion by increasing the H 2 gas flow rate and increasing the RF power. Further, by adjusting the film forming conditions such as the H 2 gas flow rate, the PH 3 gas flow rate, the pressure, and the RF power, the crystallization rate of the n-type microcrystalline silicon layer 38 and the proportion of the convex portions can be controlled. .

そして、裏面側の各層に加え、受光面側及び裏面側の各電極を形成し、図１２に示した太陽電池が形成される。   Then, in addition to the respective layers on the back surface side, the electrodes on the light receiving surface side and the back surface side are formed, and the solar cell shown in FIG. 12 is formed.

図１３は、この太陽電池の凸部に積層された各層の結晶化率の関係を示す図である。ｎ型微結晶シリコン層２８の上に、ｎ型微結晶シリコン層２８に比べて結晶化率の高いｎ型微結晶シリコン層３８が形成されている。図１４は、実施の形態４の太陽電池を上からみた時に、ｎ型の微結晶シリコン層３８が基板を占める領域を示す図である。この時の基板に対してのｎ型の微結晶シリコン層３８の面積割合は１１％である。図１５に、面積割合と太陽電池のＪＶ特性の関係を示す。すなわち、効率が向上するのは、面積割合は１％から２５％の間で、この範囲にすることが好ましい。   FIG. 13 is a diagram showing the relationship between the crystallization ratios of the layers stacked on the convex portion of the solar cell. An n-type microcrystalline silicon layer 38 having a higher crystallization rate than the n-type microcrystalline silicon layer 28 is formed on the n-type microcrystalline silicon layer 28. FIG. 14 is a diagram showing a region in which the n-type microcrystalline silicon layer 38 occupies the substrate when the solar cell of the fourth embodiment is viewed from above. The area ratio of the n-type microcrystalline silicon layer 38 to the substrate at this time is 11%. FIG. 15 shows the relationship between the area ratio and the solar cell JV characteristics. That is, it is preferable that the area ratio is in the range of 1% to 25% for improving the efficiency.

このようにして作製した太陽電池を実施例７とし、表２にそのＪＶ特性を測定した結果を示す。表２から明らかなように、比較例に比べ、実施例７の太陽電池は、ＦＦが向上し、光電変換効率が高められている。   The solar cell thus fabricated was taken as Example 7, and Table 2 shows the results of measuring its JV characteristics. As apparent from Table 2, the solar cell of Example 7 has improved FF and increased photoelectric conversion efficiency as compared with the comparative example.

すなわち、ｎ型の微結晶シリコン層３８と透光性電極１５との界面抵抗を抑えることができ、太陽電池のＪＶ特性におけるＦＦが向上する。これは、ｎ型の微結晶シリコン層の結晶化率をあげることで、この層自身の抵抗が低くなり、この層と接触する層との接触抵抗も低減できるためである。一方、凸部にのみｎ型の微結晶シリコン層３８を形成しているために、ｎ型層での太陽光の吸収損失を抑えることができ、その結果、太陽電池特性のＪscの低下を抑えることができる。   That is, the interface resistance between the n-type microcrystalline silicon layer 38 and the translucent electrode 15 can be suppressed, and the FF in the JV characteristics of the solar cell is improved. This is because by increasing the crystallization rate of the n-type microcrystalline silicon layer, the resistance of this layer itself is lowered, and the contact resistance with the layer in contact with this layer can also be reduced. On the other hand, since the n-type microcrystalline silicon layer 38 is formed only on the convex portion, the absorption loss of sunlight in the n-type layer can be suppressed, and as a result, the decrease in Jsc of solar cell characteristics can be suppressed. be able to.

なお、ここではｎ層側を受光面としたが、ｐ層側を受光面とした場合には、ｐ型の結晶系シリコン層として、ボロン(Ｂ)をドープした微結晶シリコン層を用い、その上に、結晶化率がそれより高く、凸部にのみ形成されたボロン(Ｂ)をドープしたｐ型の微結晶シリコン層を用いることで、ＦＦが向上し、光電変換効率の高い太陽電池を得ることができる。   Here, the n-layer side is the light-receiving surface, but when the p-layer side is the light-receiving surface, a microcrystalline silicon layer doped with boron (B) is used as the p-type crystalline silicon layer. On top of that, by using a p-type microcrystalline silicon layer doped with boron (B) formed only on the convex portion, the FF is improved, and a solar cell with high photoelectric conversion efficiency is obtained. Can be obtained.

実施の形態５．
図１６−１及び図１６−２は、本発明にかかる太陽電池の実施の形態５の模式的断面図および要部拡大断面図である。なお、基板の裏面側は、実施の形態３と同様である。受光面側では、ｎ型の単結晶シリコン基板１１、非晶質層としての真性の非晶質シリコン層１７と、結晶系層としての真性の微結晶シリコン層１３とが順次積層される。実施の形態５では、実施の形態４に対してｎ型の微結晶シリコン層２８とｎ型の微結晶シリコン層３８の順番を入れ替えて形成した。すなわち、結晶系層としての真性の微結晶シリコン層１３の上に、凸部にのみ、導電型結晶系シリコン系薄膜層としてリン（Ｐ）をドープしたｎ型の微結晶シリコン層３８を有する。真性の微結晶シリコン層１３及びｎ型の微結晶シリコン層３８上に、導電型結晶系シリコン系薄膜層として、リン（Ｐ）をドープしたｎ型の微結晶シリコン層２８を有する。ｎ型の微結晶シリコン層３８の製膜条件としては前記実施の形態４と同様とした。Embodiment 5 FIG.
FIGS. 16A and 16B are a schematic cross-sectional view and a main part enlarged cross-sectional view of a fifth embodiment of the solar cell according to the present invention. Note that the back side of the substrate is the same as that of the third embodiment. On the light-receiving surface side, an n-type single crystal silicon substrate 11, an intrinsic amorphous silicon layer 17 as an amorphous layer, and an intrinsic microcrystalline silicon layer 13 as a crystalline layer are sequentially laminated. In the fifth embodiment, the order of the n-type microcrystalline silicon layer 28 and the n-type microcrystalline silicon layer 38 is changed from that in the fourth embodiment. That is, an n-type microcrystalline silicon layer 38 doped with phosphorus (P) is provided as a conductive crystalline silicon thin film layer only on the convex portions on the intrinsic microcrystalline silicon layer 13 as a crystalline layer. On the intrinsic microcrystalline silicon layer 13 and the n-type microcrystalline silicon layer 38, an n-type microcrystalline silicon layer 28 doped with phosphorus (P) is provided as a conductive crystalline silicon-based thin film layer. The conditions for forming the n-type microcrystalline silicon layer 38 were the same as those in the fourth embodiment.

図１７に凸部での各層の結晶化率の関係を示す。結晶化率３．５のｎ型微結晶シリコン層３８上に、結晶化率３.０のｎ型微結晶シリコン層２８が形成されている。一方、凸部以外の領域では、図１８に示すように、結晶化率２．０の真性微結晶シリコン層１３上に結晶化率１．５のｎ型微結晶シリコン層２８が形成されている。凸部でｎ型微結晶シリコン層２８の結晶化率が凸部以外の領域のｎ型微結晶シリコン層２８に比べ増加したのは、下にこれと接するように結晶化率３．５と高いｎ型微結晶シリコン層３８があり、これにより結晶化が促進されたためである。   FIG. 17 shows the relationship between the crystallization ratios of the layers at the protrusions. An n-type microcrystalline silicon layer 28 having a crystallization rate of 3.0 is formed on an n-type microcrystalline silicon layer 38 having a crystallization rate of 3.5. On the other hand, in a region other than the convex portion, as shown in FIG. 18, an n-type microcrystalline silicon layer 28 having a crystallization rate of 1.5 is formed on intrinsic microcrystalline silicon layer 13 having a crystallization rate of 2.0. . The reason why the crystallization rate of the n-type microcrystalline silicon layer 28 at the convex portion is higher than that of the n-type microcrystalline silicon layer 28 in the region other than the convex portion is as high as a crystallization ratio of 3.5 so as to be in contact with the bottom. This is because there is an n-type microcrystalline silicon layer 38, which promotes crystallization.

さらに、ｎ型微結晶シリコン層２８上に、透光性電極１５が形成され、表面には銀層からなる集電電極１６が形成されている。   Further, a translucent electrode 15 is formed on the n-type microcrystalline silicon layer 28, and a collecting electrode 16 made of a silver layer is formed on the surface.

これにより、光吸収の少ないｎ型の微結晶シリコン膜が形成できるとともに、ｎ層自身の抵抗の低減及び透光性電極との接触抵抗の低減を図ることができるためＦＦが向上する。一方、真性の微結晶シリコン層１３とこれよりも結晶化率の高いｎ型微結晶シリコン層３８が凸部で接することになるが、接している領域は基板表面の全面積に対して１１％程度と少ないため、太陽電池特性のＶocへの低下を招くことはほとんどない。   Accordingly, an n-type microcrystalline silicon film with little light absorption can be formed, and the resistance of the n layer itself and the contact resistance with the light-transmitting electrode can be reduced, so that FF is improved. On the other hand, the intrinsic microcrystalline silicon layer 13 and the n-type microcrystalline silicon layer 38 having a higher crystallization rate are in contact with each other at the convex portion, but the contacting area is 11% with respect to the total area of the substrate surface. Due to the low degree, the solar cell characteristics are hardly reduced to Voc.

このようにして作製した太陽電池を実施例８とし、表２にそのＪＶ特性の結果を示す。表２から明らかなように比較例に比べ、実施例８の太陽電池は、ＦＦが向上し、光電変換効率が高められていることがわかる。   The solar cell thus fabricated was taken as Example 8, and Table 2 shows the results of the JV characteristics. As is clear from Table 2, it can be seen that the solar cell of Example 8 has improved FF and higher photoelectric conversion efficiency than the comparative example.

なお、本発明において、結晶系シリコン基板とは、単結晶又は多結晶シリコン基板をいうものとする。また真性シリコン系薄膜層とは、真性シリコン薄膜又は真性シリコン化合物半導体薄膜をいうものとする。また導電型結晶系シリコン系薄膜層は、不純物を含み、ｐ型又はｎ型の微結晶又は多結晶シリコン薄膜層あるいは、微結晶又は多結晶シリコン化合物半導体薄膜層をいうものとする。   In the present invention, the crystalline silicon substrate means a single crystal or polycrystalline silicon substrate. The intrinsic silicon-based thin film layer refers to an intrinsic silicon thin film or an intrinsic silicon compound semiconductor thin film. The conductive crystalline silicon-based thin film layer includes an impurity and refers to a p-type or n-type microcrystalline or polycrystalline silicon thin film layer, or a microcrystalline or polycrystalline silicon compound semiconductor thin film layer.

以上のように、本発明にかかる太陽電池及びその製造方法は、結晶系基板上に導電型薄膜を形成した太陽電池に有用であり、特に、低温で微結晶化することが困難であるボロンドープのシリコン系薄膜を用いた太陽電池に適している。   As described above, the solar cell and the method for manufacturing the solar cell according to the present invention are useful for a solar cell in which a conductive thin film is formed on a crystalline substrate, and in particular, boron-doped that is difficult to microcrystallize at a low temperature. Suitable for solar cells using silicon-based thin films.

１１ ｎ型の単結晶シリコン基板、１２ 真性の非晶質シリコン層、１３ 真性の微結晶シリコン層、１４ ｐ型の微結晶シリコン層、１５，２５ 透光性電極、１６，２６ 集電電極、１７ 真性の非晶質シリコン層、１８ ｎ型の非晶質シリコン層、１９ 反射層、２４，３４ ｐ型の非晶質シリコン層、２８，３８ ｎ型の微結晶シリコン層。   11 n-type single crystal silicon substrate, 12 intrinsic amorphous silicon layer, 13 intrinsic microcrystalline silicon layer, 14 p-type microcrystalline silicon layer, 15, 25 translucent electrode, 16, 26 collector electrode, 17 Intrinsic amorphous silicon layer, 18 n-type amorphous silicon layer, 19 reflective layer, 24, 34 p-type amorphous silicon layer, 28, 38 n-type microcrystalline silicon layer.

Claims (8)

片面に凹凸構造を有する一導電型の結晶系シリコン基板上に、
前記凹凸構造を有する前記片面に接するように真性シリコン系薄膜層と、導電型結晶系シリコン系薄膜層とが順次積層された太陽電池であって、
前記真性シリコン系薄膜層は前記結晶系シリコン基板側から順に非晶質層と結晶系層の２層を備え、
前記導電型結晶系シリコン系薄膜層に接するように前記凹凸構造の凸部に選択的に形成され、前記導電型結晶系シリコン系薄膜層の結晶化率より高い導電型結晶系シリコン系薄膜層からなるキャップ層を備え、
前記導電型結晶系シリコン系薄膜層は、前記真性シリコン系薄膜層と接する部分において隣接する前記真性シリコン系薄膜層より結晶化率が低いことを特徴とする太陽電池。 On one conductivity type crystalline silicon substrate having a concavo-convex structure on one side ,
A solar cell in which an intrinsic silicon-based thin film layer and a conductive crystalline silicon-based thin film layer are sequentially stacked so as to be in contact with the one surface having the uneven structure ,
The intrinsic silicon thin film layer comprises two layers of an amorphous layer and a crystalline layer in order from the crystalline silicon substrate side,
From the conductive crystalline silicon thin film layer selectively formed on the convex portion of the concavo-convex structure so as to be in contact with the conductive crystalline silicon thin film layer and having a higher crystallization rate than the conductive crystalline silicon thin film layer With a cap layer
The solar cell according to claim 1, wherein the conductive crystalline silicon-based thin film layer has a lower crystallization rate than the adjacent intrinsic silicon-based thin film layer in a portion in contact with the intrinsic silicon-based thin film layer. 前記キャップ層が前記片面において占める面積の割合は１％から２５％であることを特徴とする請求項１に記載の太陽電池。 The solar cell according to claim 1 , wherein a ratio of an area occupied by the cap layer on the one surface is 1% to 25%. 前記キャップ層は、前記真性シリコン系薄膜層の前記結晶系層と前記導電型結晶系シリコン系薄膜層とに挟まれて形成されており、
前記導電型結晶系シリコン系薄膜層は、前記キャップ層に接する部分の結晶化率が前記キャップ層に接しない部分の結晶化率より高いことを特徴とする請求項１または２に記載の太陽電池。 The cap layer is formed by being sandwiched between the crystalline layer of the intrinsic silicon thin film layer and the conductive crystalline silicon thin film layer,
The conductive type crystalline silicon-based thin film layer, a solar cell according to claim 1 or 2, the crystallization rate of the portion in contact with the cap layer is equal to or higher than the crystallization rate of the portion not in contact with the cap layer . 前記一導電型の結晶系シリコン基板は、ｎ型単結晶シリコンあるいはｐ型単結晶シリコンであり、前記真性シリコン系薄膜層の結晶層は真性微結晶シリコンであり、
前記導電型結晶系シリコン系薄膜層及び前記キャップ層は、ｐ型微結晶シリコンあるいはｎ型微結晶シリコンであることを特徴とする請求項１から３のいずれか１項に記載の太陽電池。 The one-conductivity-type crystalline silicon substrate is n-type single-crystal silicon or p-type single-crystal silicon, and the intrinsic silicon-based thin film layer is intrinsic microcrystalline silicon,
The conductive type crystalline silicon-based thin film layer and the cap layer, the solar cell according to any one of claims 1 to 3, characterized in that the p-type microcrystalline silicon or n-type microcrystalline silicon. 片面に凹凸構造を有する一導電型の結晶系シリコン基板の片面に接するように真性シリコン系薄膜層を形成する工程と、
前記真性シリコン系薄膜層上に導電型結晶系シリコン系薄膜層を形成する工程と、
を含む太陽電池の製造方法であって、
前記真性シリコン系薄膜層を形成する工程は、
前記結晶系シリコン基板に接して非晶質層を形成する工程と、
前記非晶質層上に結晶系層を形成する工程と、
を含み、
前記導電型結晶系シリコン系薄膜層を形成する工程に先立ち、前記凹凸構造の凸部に選択的に、前記導電型結晶系シリコン系薄膜層の結晶化率より高い導電型結晶系シリコン系薄膜層からなるキャップ層を形成する工程を含み、
前記導電型結晶系シリコン系薄膜層は、前記真性シリコン系薄膜層と接する部分において隣接する前記真性シリコン系薄膜層より結晶化率を低く形成することを特徴とする太陽電池の製造方法。 Forming an intrinsic silicon-based thin film layer so as to be in contact with one surface of one conductivity type crystalline silicon substrate having a concavo-convex structure on one surface;
Forming a conductive crystalline silicon thin film layer on the intrinsic silicon thin film layer;
A method for producing a solar cell comprising:
The step of forming the intrinsic silicon-based thin film layer includes
Forming an amorphous layer in contact with the crystalline divorced substrate,
Forming a crystalline layer on the amorphous layer;
Including
Prior to the step of forming the conductive crystalline silicon-based thin film layer, the conductive crystalline silicon-based thin film layer having a higher crystallization rate than the conductive crystalline silicon-based thin film layer is selectively formed on the convex portion of the concavo-convex structure. Forming a cap layer comprising:
The method of manufacturing a solar cell, wherein the conductive crystalline silicon-based thin film layer is formed at a lower crystallization rate than the adjacent intrinsic silicon-based thin film layer at a portion in contact with the intrinsic silicon-based thin film layer. 一導電型の結晶系シリコン基板は、ｎ型単結晶シリコンあるいはｐ型単結晶シリコンであり、
前記結晶系層は、真性の微結晶シリコン層であり、
前記導電型結晶系シリコン系薄膜層は、ホウ素（Ｂ）をドープしたｐ型の微結晶シリコン層を形成する工程あるいは、リン（Ｐ）をドープしたｎ型の微結晶シリコン層を形成する工程であることを特徴とする請求項５に記載の太陽電池の製造方法。 One conductivity type crystalline silicon substrate is n-type single crystal silicon or p-type single crystal silicon,
The crystalline layer is an intrinsic microcrystalline silicon layer,
The conductive crystalline silicon thin film layer is formed by a step of forming a p-type microcrystalline silicon layer doped with boron (B) or a step of forming an n-type microcrystalline silicon layer doped with phosphorus (P). The method for producing a solar cell according to claim 5 , wherein the method is provided. 片面に凹凸構造を有する一導電型の結晶系シリコン基板の片面に接するように真性シリコン系薄膜層を形成する工程と、
前記真性シリコン系薄膜層上に導電型結晶系シリコン系薄膜層を形成する工程と、
を含む太陽電池の製造方法であって、
前記真性シリコン系薄膜層を形成する工程は、
前記結晶系シリコン基板に接して非晶質層を形成する工程と、
前記非晶質層上に結晶系層を形成する工程と、
を含み、
前記導電型結晶系シリコン系薄膜層を形成する工程後、前記凹凸構造の凸部に選択的に、前記導電型結晶系シリコン系薄膜層の結晶化率より高い導電型結晶系シリコン系薄膜層からなるキャップ層を形成する工程を含み、
前記導電型結晶系シリコン系薄膜層は、前記真性シリコン系薄膜層と接する部分において隣接する前記真性シリコン系薄膜層より結晶化率を低く形成することを特徴とする太陽電池の製造方法。 Forming an intrinsic silicon-based thin film layer so as to be in contact with one surface of one conductivity type crystalline silicon substrate having a concavo-convex structure on one surface;
Forming a conductive crystalline silicon thin film layer on the intrinsic silicon thin film layer;
A method for producing a solar cell comprising:
The step of forming the intrinsic silicon-based thin film layer includes
Forming an amorphous layer in contact with the crystalline silicon substrate;
Forming a crystalline layer on the amorphous layer;
Including
After the step of forming the conductive crystalline silicon-based thin film layer, the conductive crystalline silicon-based thin film layer having a higher crystallization rate than the conductive crystalline silicon-based thin film layer is selectively formed on the convex portion of the concavo-convex structure. Forming a cap layer comprising:
The conductive type crystalline silicon-based thin film layer, wherein the method of manufacturing that solar cells to characterized in that from the intrinsic silicon-based thin film layer to form a low crystallization rate that is adjacent in a portion which is in contact with intrinsic silicon-based thin film layer. 一導電型の結晶系シリコン基板は、ｎ型単結晶シリコンあるいはｐ型単結晶シリコンであり、
前記結晶系層は、真性の微結晶シリコン層であり、
前記導電型結晶系シリコン系薄膜層は、ホウ素（Ｂ）をドープしたｐ型の微結晶シリコン層を形成する工程あるいは、リン（Ｐ）をドープしたｎ型の微結晶シリコン層を形成する工程であることを特徴とする請求項７に記載の太陽電池の製造方法。 One conductivity type crystalline silicon substrate is n-type single crystal silicon or p-type single crystal silicon,
The crystalline layer is an intrinsic microcrystalline silicon layer,
The conductive crystalline silicon thin film layer is formed by a step of forming a p-type microcrystalline silicon layer doped with boron (B) or a step of forming an n-type microcrystalline silicon layer doped with phosphorus (P). The method for producing a solar cell according to claim 7 , wherein the method is provided.
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