JP5713650B2 - LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - Google Patents
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- 238000000034 method Methods 0.000 description 26
- 239000004065 semiconductor Substances 0.000 description 15
- 229910002704 AlGaN Inorganic materials 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 239000010931 gold Substances 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 7
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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Description
この発明は、ＬＥＤ等として用いられる発光素子およびその製造方法に関する。 The present invention relates to a light emitting device used as an LED or the like and a method for manufacturing the same.
近年、ＬＥＤを始めとする半導体発光素子の進歩は著しい。具体的には、発光強度の上昇を初めとする試みが進められている。 In recent years, the progress of semiconductor light emitting devices including LEDs has been remarkable. Specifically, attempts such as an increase in light emission intensity are underway.
例えば、特許文献１には、発光強度の上昇に伴うリーク電流の減少を目的として、活性層へのダメージを減らして活性層の成膜時のクラックを防止し、ウエハ全体の反りを極力少なくすることで、より均一な特性の窒化ガリウム系半導体発光素子を得る為、ボンディング電極下方のＰＮ接合と、発光部のＰＮ接合とを分離することが提案されている。
特許文献２には、発光面全体に渡って均一な電流を流す為、基板上にｎ型層、活性層及びｐ型層が積層されてなる積層体を備え、その積層体はｎ側の電極をライン状に形成するためにｎ型層表面が露出された互いに平行なｎ電極形成領域を設けられ、そのｎ電極形成領域にそれぞれｎライン電極が形成され、ｐ型層のほぼ全面に透光性電極を形成され、ｎライン電極は互いに分離して等間隔に配置され、かつ、各ｎライン電極の一端にはそれぞれｎパッド電極が形成され、透光性電極上にはｎライン電極と交互に配置されかつ隣接するｎライン電極から等距離になるようにライン状の電流拡散導体が形成され、その電流拡散導体の一端にそれぞれｐパッド電極が形成された、櫛形形状の電極が提案されている。
For example, in Patent Document 1, for the purpose of reducing a leakage current accompanying an increase in emission intensity, damage to the active layer is reduced to prevent cracks during the formation of the active layer, and the warpage of the entire wafer is minimized. Thus, in order to obtain a gallium nitride based semiconductor light emitting device with more uniform characteristics, it has been proposed to separate the PN junction below the bonding electrode and the PN junction of the light emitting portion.
Patent Document 2 includes a laminate in which an n-type layer, an active layer, and a p-type layer are laminated on a substrate in order to allow a uniform current to flow over the entire light emitting surface, and the laminate is an n-side electrode. Are formed in parallel with each other, and n-line electrodes are formed in the n-electrode formation regions, and light is transmitted over almost the entire surface of the p-type layer. The n-line electrodes are separated from each other and arranged at equal intervals, and an n-pad electrode is formed at one end of each n-line electrode. The n-line electrodes are alternately formed on the translucent electrode. A comb-shaped electrode is proposed in which a line-shaped current diffusion conductor is formed so as to be equidistant from an adjacent n-line electrode and a p-pad electrode is formed at one end of the current diffusion conductor. Yes.
しかしながら本発明者らは、当該発光強度上昇の試みに伴い素子に流れる電流量が増大することが、これが半導体素子の発光特性や寿命へ悪影響を与えることに想到した。
そこで当該悪影響を回避する為、本発明者等は、発光層を形成する半導体に均一な電流を流すことが好ましいことに想到した。そして当該観点から、特許文献１、２を検討した。
However, the present inventors have conceived that an increase in the amount of current flowing through the device accompanying the attempt to increase the light emission intensity adversely affects the light emission characteristics and lifetime of the semiconductor device.
Therefore, in order to avoid the adverse effect, the present inventors have conceived that it is preferable to pass a uniform current through the semiconductor forming the light emitting layer. And from the said viewpoint, patent document 1, 2 was examined.
当該観点から特許文献１を検討すると、当該文献は、あくまでもボンディング時のボンディング電極下の発光部ダメージ回避が目的であり、電流を分散させる方法については、ｎ電極を中央としてｐ電極の補助電極を周回させるのみであった。 Examining Patent Document 1 from this point of view, this document is only for the purpose of avoiding damage to the light emitting portion under the bonding electrode during bonding. For the method of distributing the current, the auxiliary electrode of the p electrode is used with the n electrode as the center. It was only going around.
また、特許文献２では、電流拡散導体の一端にそれぞれパッド電極が形成する櫛形形状の電極を提案している。しかし当該構成を採ると、発光層を形成する半導体に均一な電流を流す為には多数のパッド電極が必要となり、実用的でないと考えられた。 Patent Document 2 proposes a comb-shaped electrode in which a pad electrode is formed at one end of a current diffusion conductor. However, with this configuration, it was considered impractical to use a large number of pad electrodes in order to allow a uniform current to flow through the semiconductor forming the light emitting layer.
本発明は、上述の状況の下でなされたものであり、その解決しようとする課題は、パッド電極の数を増やしたりすることなく、発光層を形成する半導体に分散して電流を流すことのできる発光素子およびその製造方法を提供することである。 The present invention has been made under the above-described circumstances, and the problem to be solved is that a current is distributed to the semiconductor forming the light emitting layer without increasing the number of pad electrodes. It is providing the light emitting element which can be manufactured, and its manufacturing method.
ここで本発明者らはさらに研究を進めた。そして、ｎ型パッド電極および補助電極が全てｎ型層上に形成されている場合、電流が広がるように補助電極を延伸させても、ｎコンタクト部とｎ型層との間のコンタクト抵抗が低くなるにつれ、結局ｎ型パッド電極に近い部分とｐ電極との距離の短いところに電流が集中して流れ易くなることを知見した。この結果、電流が所望のようには拡散しないこと、および、その電流が拡散しない原因が、ｎ型層とのコンタクト部がｎ電極全体におよんでいる為であることに想到した。 Here, the inventors have further studied. When the n-type pad electrode and the auxiliary electrode are all formed on the n-type layer, the contact resistance between the n-contact portion and the n-type layer is low even if the auxiliary electrode is extended so that the current spreads. As a result, it has been found that current tends to flow in a concentrated manner at a short distance between the portion near the n-type pad electrode and the p-electrode. As a result, it was conceived that the current does not diffuse as desired, and that the current does not diffuse because the contact portion with the n-type layer extends over the entire n-electrode.
当該知見に基づき、本発明者らは、パット電極の数を増やすのではなく、２以上の第１導電型電極のコンタクト部を効果的に非連続に分散して配置し、それぞれの第１導電型電極のコンタクト部へ、導体配線を用いて独立に電流を供給すれば、発光層を形成する半導体に分散して電流を流すことが出来ることに想到し、本発明を完成した。 Based on this knowledge, the present inventors do not increase the number of pad electrodes, but disperse and dispose the contact portions of two or more first conductivity type electrodes effectively in a discontinuous manner. The inventors of the present invention have completed the present invention by conceiving that current can be distributed to the semiconductor forming the light-emitting layer by supplying current independently to the contact portion of the mold electrode using conductor wiring.
即ち、上述の課題を解決するための第１の発明は、
発光層を挟んで第１導電型層、第２導電型層が設けられた積層構造を有し、
前記第２導電型層と発光層を大小２部分に分断する溝構造を有し、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
当該第１導電型の電極パッドを起点として前記第１導電型層へ延伸する導電配線により、前記第１導電型層と接続し互いに独立した２箇所以上の電気的コンタクトを有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子である。
That is, the first invention for solving the above-described problem is
Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
A groove structure that divides the second conductivity type layer and the light emitting layer into two parts,
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
The conductive wiring extending from the first conductive type electrode pad to the first conductive type layer has two or more electrical contacts connected to the first conductive type layer and independent from each other ,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
In the light emitting device, the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads are X <Y and X + Y ≧ 3 .
第２の発明は、
発光層を挟んで第１導電型層、第２導電型層が設けられた積層構造を有し、
前記第２導電型層が、前記第１導電型層の露出部を形成する溝構造により、大小２部分に分断されており、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
前記分断された小さい方の第２導電型層上および分断部側面に、前記第１導電型の電極パッドを起点とし、前記第１導電型層の露出部に設けられた互いに独立した２箇所以上の電気的コンタクトへ向けて延伸する導電配線を有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子である。
The second invention is
Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
The second conductivity type layer is divided into two parts by a groove structure that forms an exposed portion of the first conductivity type layer;
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
Two or more independent portions provided on the exposed portion of the first conductivity type layer, starting from the electrode pad of the first conductivity type, on the divided second conductive type layer and on the side surface of the divided portion. It has a conductive wire which extends towards to the electrical contact,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
In the light emitting device, the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads are X <Y and X + Y ≧ 3 .
第３の発明は、
発光層を挟んで第１導電型層、第２導電型層が設けられた積層構造を有し、
前記第２導電型層が、前記第１導電型層の露出部を形成する溝構造により、大小２部分に分断されており、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
当該第１導電型の電極パッドを起点として前記露出した第１導電型層へ延伸する導電配線により、前記第１導電型層の露出部に設けられた互いに独立した２箇所以上の電気的コンタクトを有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子である。
The third invention is
Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
The second conductivity type layer is divided into two parts by a groove structure that forms an exposed portion of the first conductivity type layer;
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
Two or more independent electrical contacts provided on the exposed portion of the first conductivity type layer are formed by conductive wiring extending from the first conductivity type electrode pad to the exposed first conductivity type layer. Have
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
In the light emitting device, the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads are X <Y and X + Y ≧ 3 .
第４の発明は、
基板上に、当該基板側から順に、第１導電型層、発光層、第２導電型層を有する積層構造を形成する工程と、
前記第２導電型層側からエッチングにより第１導電型層を露出させて、前記第２導電型層を大小２部分に分断する溝構造を形成する工程と、
前記分断された大きい方の第２導電型層上に、第２導電型の電極パッドを形成する工程と、
前記分断された小さい方の第２導電型層上から、前記第１導電型層の露出部へ延伸する導電配線を形成する工程と、
前記分断された小さい方の第２導電型層上に、第１導電型の電極パッドを形成する工程を有し、
前記導電配線は、第１導電型層の露出部の一部に対し延伸しない部分を有し、
前記第１導電型の電極パッドを起点として、前記第１導電型層の露出部に対して互いに独立した２箇所以上の電気的コンタクトを形成し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとを等しくし、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとを、Ｘ＜ＹかつＸ＋Ｙ≧３とする発光素子の製造方法である。
The fourth invention is:
Forming a laminated structure having a first conductivity type layer, a light emitting layer, and a second conductivity type layer on the substrate in order from the substrate side;
A step of exposing the first conductivity type layer by etching from the second conductivity type layer side to form a groove structure that divides the second conductivity type layer into two parts,
Forming a second conductivity type electrode pad on the divided second conductivity type layer; and
Forming a conductive wiring extending from the divided second conductive type layer to the exposed portion of the first conductive type layer;
Forming a first conductive type electrode pad on the divided second conductive type layer;
The conductive wiring has a portion not extending with respect to a part of the exposed portion of the first conductivity type layer,
Starting from the first conductive type electrode pad, two or more independent electrical contacts are formed with respect to the exposed portion of the first conductive type layer ,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is made equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
In this method, the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads are X <Y and X + Y ≧ 3 .
本発明によると、発光層を形成する半導体層中を、電流が分散して流れるので、電流集中による特性劣化や、寿命短縮が少なく、さらに実装不良も少ない発光素子を得ることができた。 According to the present invention, since the current flows in a distributed manner in the semiconductor layer forming the light emitting layer, it is possible to obtain a light emitting element with less characteristic deterioration due to current concentration, less life shortening, and fewer mounting defects.
以下、図面を参照しながら、本発明に係る発光体素子およびその製造方法について説明する。尚、当該発光体素子およびその製造方法は代表的な例を示したものであって、本発明はこの実施形態に限定されるものではない。
図１の（ａ）〜（ｅ）は、本発明に係る発光素子チップの加工例における工程毎の模式的な平面図である。
図１（ａ）は加工前の平面図であり、（ｂ）はドライエッチングにてパターンを形成した後の平面図であり、（ｃ）は第２電極を成膜した後の平面図であり、（ｄ）は第１電極を成膜した後の平面図であり、（ｅ）は電極パッドを成膜した後の平面図である。
図２は、図１（ｅ）のＩ−Ｉ断面図であり、図３は、図１（ｅ）のII−II断面図であり、図４（ｅ）のIII−III断面図である。
Hereinafter, a light emitting device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. In addition, the said light-emitting device and its manufacturing method showed the typical example, Comprising: This invention is not limited to this embodiment.
(A)-(e) of FIG. 1 is a schematic plan view for every process in the processing example of the light emitting element chip based on this invention.
FIG. 1A is a plan view before processing, FIG. 1B is a plan view after forming a pattern by dry etching, and FIG. 1C is a plan view after forming a second electrode. (D) is a top view after forming a first electrode, (e) is a plan view after forming an electrode pad.
2 is a cross-sectional view taken along the line II in FIG. 1 (e), FIG. 3 is a cross-sectional view taken along the line II-II in FIG. 1 (e), and a cross-sectional view taken along the line III-III in FIG.
図１（ａ）は、本発明に係る発光素子チップ１００の加工前の平面図であり、第２導電型層１１１が見えている。そして、当該第２導電型層１１１の下層には後述する発光層１１２（図示していない。）、さらにその下層には第１導電型層１１３が成膜されている。これらの層は、サファイア基板等の成長基板（図示していない。）上に成膜された半導体層である。
本実施の形態では、第１導電型層がｎ型のＡｌＧａＮ、第２導電型層がｐ型のＡｌＧａＮ、発光層がＡｌＩｎＧａＮのIII−Ｖ族半導体であるが、ｎとｐとは逆転していても良く、半導体としてもＡｌＧａＮ以外の、ＧａＮ、ＩｎＧａＮ等であっても良い。
FIG. 1A is a plan view of the light emitting device chip 100 according to the present invention before processing, and the second conductivity type layer 111 can be seen. A light emitting layer 112 (not shown) to be described later is formed below the second conductivity type layer 111, and a first conductivity type layer 113 is further formed below the light emission layer 112. These layers are semiconductor layers formed on a growth substrate (not shown) such as a sapphire substrate.
In this embodiment, the first conductivity type layer is an n-type AlGaN, the second conductivity type layer is a p-type AlGaN, and the light emitting layer is an AlInGaN group III-V semiconductor. However, n and p are reversed. Alternatively, the semiconductor may be GaN, InGaN, or the like other than AlGaN.
図１（ｂ）は、本発明に係る発光素子チップ１００に、フォトリソグラフィーによるマスクパターン形成後のドライエッチング（本発明において、「ＲＩＥ」と記載する場合がある。）にて溝パターンを形成した後の平面図である。
発光素子チップ１００の第２導電型層１１１へＣＶＤによりＳｉＯ２マスクを形成し、フォトリソグラフィーによりマスクパターンを形成する。その後、ＲＩＥにて、当該マスクが設けられていない箇所の第２導電型層１１１および発光層１１２および第１導電型層１１３の途中までをエッチング除去し、第１導電型層の露出部１１５を形成し、第１導電型層１１３を露出させた。
また、図示しないが、隣り合う発光素子チップ１００の間を、後に分離させるに十分な幅をもって、同様にして第１導電型層１１３を露出させて分離溝を形成した。
以上、第１導電型層１１３の途中までをエッチング除去し、第１導電型層の露出部１１５を形成し、第１導電型層１１３を露出させる場合を例示した。尤も、当該第１導電型層１１３の途中までをエッチング除去に限られず、第１導電型層が露出した時点でエッチングを止めても良いし、第１導電型層を完全に除去しても良い。そして、第１導電型層を完全に除去した場合は、露出した第１導電型層の側面へのコンタクトをとるか、または、第１導電型層を導電性の基板等で支持する構成を採れば良い。
In FIG. 1B, a groove pattern is formed on the light emitting element chip 100 according to the present invention by dry etching after forming a mask pattern by photolithography (in the present invention, it may be described as “RIE”). FIG.
A SiO 2 mask is formed by CVD on the second conductivity type layer 111 of the light emitting element chip 100, and a mask pattern is formed by photolithography. After that, by RIE, the second conductive type layer 111, the light emitting layer 112, and the first conductive type layer 113 at portions where the mask is not provided are etched away, and the exposed portion 115 of the first conductive type layer is removed. Then, the first conductivity type layer 113 was exposed.
In addition, although not shown, the first conductive type layer 113 was exposed in the same manner with a sufficient width to separate the adjacent light emitting element chips 100 later to form separation grooves.
As described above, the case where the first conductive type layer 113 is partially removed by etching, the exposed portion 115 of the first conductive type layer is formed, and the first conductive type layer 113 is exposed is illustrated. However, the etching is not limited to the middle of the first conductivity type layer 113, and the etching may be stopped when the first conductivity type layer is exposed, or the first conductivity type layer may be completely removed. . When the first conductivity type layer is completely removed, contact the exposed side surface of the first conductivity type layer or support the first conductivity type layer with a conductive substrate or the like. It ’s fine.
当該溝パターンは、個々の発光素子チップ１００間および発光素子チップ１００のｎ電極とｐ電極とを分離し、ｎ電極を第２導電型層１１１に形成させる為のもので、上述したように、電流が第１導電型層を均一に拡散して流れる効果をねらったものである。当該溝パターンにより第２導電型層１１１は、相対的に小さい第２導電型層１１１ａと相対的に大きい第２導電型層１１１ｂとに分断される。
ＲＩＥ終了後、ＳｉＯ２マスクをエッチング除去するが、第２導電型層１１１ａ上のＳｉＯ２マスクは後述する絶縁膜として使用出来る為、残しても良い。
The groove pattern is for separating the n-electrode and the p-electrode between the individual light-emitting element chips 100 and the light-emitting element chip 100 and forming the n-electrode in the second conductivity type layer 111. As described above, This is for the effect that the current flows by uniformly diffusing through the first conductivity type layer. The second conductivity type layer 111 is divided into a relatively small second conductivity type layer 111a and a relatively large second conductivity type layer 111b by the groove pattern.
After the RIE, the SiO 2 mask is removed by etching. However, the SiO 2 mask on the second conductivity type layer 111a may be used because it can be used as an insulating film described later.
図１（ｃ）は、本発明に係る発光素子チップ１００へ、第２電極１２１を成膜した後の平面図である。
第２電極１２１は、例えば（Ｎｉ／Ａｕ）層を第２導電型層１１１ｂ上に成膜したものである。電極は既知の金属構成から選択できる。なお図面では、第２電極１２１が、第２導電型層１１１ｂ上の全面に形成されており、全面電極であることが好ましい。全面電極とは、第２導電型層１１１ｂとのコンタクトを形成すると共にパッド電極からの電流を拡散し、さらに発光層の発光を透過または反射する機能を有するものである。
FIG. 1C is a plan view after the second electrode 121 is formed on the light emitting element chip 100 according to the present invention.
The second electrode 121 is formed, for example, by forming a (Ni / Au) layer on the second conductivity type layer 111b. The electrodes can be selected from known metal configurations. In the drawing, the second electrode 121 is formed on the entire surface of the second conductivity type layer 111b, and is preferably a full surface electrode. The full-surface electrode has a function of forming a contact with the second conductivity type layer 111b, diffusing a current from the pad electrode, and transmitting or reflecting light emitted from the light emitting layer.
図１（ｄ）は、本発明に係る発光素子チップ１００へ、第１電極１３１を成膜した後の平面図である。
第１電極１３１は、例えば（Ｔｉ／Ａｌ／Ｔｉ）層を、第２導電型層１１１ａから第１導電型層の露出部１１５へかけて成膜するものである。電極は既知の金属構成から選択できる。当該第１導電型層の露出部１１５へかけての第１電極１３１の成膜の詳細は後述するが、第２導電型層１１１ａであって凸部上の第１電極１３１の成膜である１３１ａは、当該凸部から第１導電型層の露出部１１５へかけて成膜される。この結果、当該凸部の周辺に第１電極１３１の成膜である１３１ａと第１導電型層１１３との接触部１３５が形成された。
また、第２導電型層１１１ａ上であって凸部でない部分における第１電極の成膜１３１ｂは、第１導電型層の露出部１１５と接触しない。つまり、第１電極の成膜１３１は第１導電型層の露出部の一部に対し延伸しない部分を有する。そして第２導電型層１１１ａの凸部の両端から左右方向に向けて、第１電極１３１の成膜は第１導電型層の露出部１１５へかけて成膜され、第１導電型層の露出部１１５と接触する第１電極の成膜１３１ｃとなる。この結果、凸部の両端から左右方向に向けて第１電極１３１の成膜である１３１ｃと第１導電型層１１３との接触部１３６が形成された。
FIG. 1D is a plan view after the first electrode 131 is formed on the light emitting element chip 100 according to the present invention.
The first electrode 131 is formed, for example, by forming a (Ti / Al / Ti) layer from the second conductivity type layer 111a to the exposed portion 115 of the first conductivity type layer. The electrodes can be selected from known metal configurations. Details of the film formation of the first electrode 131 over the exposed portion 115 of the first conductivity type layer will be described later, but this is the film formation of the first electrode 131 on the convex portion of the second conductivity type layer 111a. 131a is formed from the convex portion to the exposed portion 115 of the first conductivity type layer. As a result, a contact portion 135 between 131a, which is the film formation of the first electrode 131, and the first conductivity type layer 113 was formed around the convex portion.
In addition, the first electrode film formation 131b on the second conductivity type layer 111a that is not a convex portion does not contact the exposed portion 115 of the first conductivity type layer. That is, the first electrode film formation 131 has a portion that does not extend to a part of the exposed portion of the first conductivity type layer. The first electrode 131 is formed from both ends of the convex portion of the second conductivity type layer 111a in the left-right direction to the exposed portion 115 of the first conductivity type layer, and the first conductivity type layer is exposed. Thus, the first electrode film 131 c in contact with the portion 115 is formed. As a result, a contact portion 136 between 131c, which is the film formation of the first electrode 131, and the first conductivity type layer 113 is formed from both ends of the convex portion in the left-right direction.
図１（ｅ）は、本発明に係る発光素子チップ１００へ電極パッドを成膜した後の平面図の一例である。
電極パッドは、第２導電型層１１１ａの凸部上へ第１導電体側電極パッド１４１として例えば（Ｔｉ／Ａｕ）層を成膜したものであり、第２電極１２１上の２箇所以上へ第２導電体側電極パッド１４２として例えば（Ｔｉ／Ａｕ）層を成膜したものである。パッド電極も既知の金属構成から選択できる。
FIG. 1E is an example of a plan view after electrode pads are formed on the light emitting element chip 100 according to the present invention.
The electrode pad is obtained by forming, for example, a (Ti / Au) layer as the first conductor-side electrode pad 141 on the convex portion of the second conductivity type layer 111a. For example, a (Ti / Au) layer is formed as the conductor-side electrode pad 142. The pad electrode can also be selected from known metal configurations.
ここで、例えば、第２導電体側電極パッド１４２が２つに対し、第１導電体側電極パッド１４１が１つのように、第１導電型の電極パッドの個数Ｘと、第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３とすることが好ましい。また、これら電極パッドは非直線的に配置することが好ましい。当該構成を採ることで、発光体素子チップ１００をフィリップ接合した場合においても、当該発光体素子チップが傾くことなく実装することができるからである。１個の発光体素子チップ１００において傾きを防止する為には、最低限で３箇所の電極パッド数があれば良い。
第１導電体側電極パッド１４１および第２導電体側電極パッド１４２の成膜後に、発光素子チップ１００上に例えばＳｉＯ２や樹脂などの絶縁性の保護膜を形成した後、第１および第２導電体側電極パッド１４１、１４２上の保護膜を除去する。
Here, for example, the number X of the first conductivity type electrode pads and the number of the second conductivity type electrode pads 142 are such that the number of the first conductor side electrode pads 141 is one for the two second conductor side electrode pads 142. The number Y of X is preferably set so that X <Y and X + Y ≧ 3. These electrode pads are preferably arranged non-linearly. By adopting this configuration, even when the light emitting element chip 100 is Philip bonded, the light emitting element chip can be mounted without being inclined. In order to prevent tilting in one light emitter element chip 100, it is sufficient that the number of electrode pads is three at a minimum.
After forming the first conductor side electrode pad 141 and the second conductor side electrode pad 142, an insulating protective film such as SiO 2 or resin is formed on the light emitting element chip 100, and then the first and second conductor sides are formed. The protective film on the electrode pads 141 and 142 is removed.
ここで、図１（ｅ）について、図２のＩ−Ｉ断面図、図３のII−II断面図、図１（ｅ）あり、図４（ｅ）のIII−III断面図を参照しながらさらに説明する。
図２〜４において、サファイア基板等の成長基板（図示していない）上に成膜された半導体層は、下方から第１導電型層１１３、発光層１１２および第２導電型層１１１が成膜されている。
Here, FIG. 1 (e) is a cross-sectional view taken along II in FIG. 2, a cross-sectional view taken along II-II in FIG. 3, and FIG. 1 (e), with reference to a cross-sectional view taken along III-III in FIG. Further explanation will be given.
2 to 4, the semiconductor layer formed on a growth substrate (not shown) such as a sapphire substrate has a first conductive type layer 113, a light emitting layer 112, and a second conductive type layer 111 formed from below. Has been.
当該半導体層には溝パターンが掘られ、第１導電型層の露出部１１５が形成され、第１導電型層１１３が露出している。さらに当該溝パターンは、第２導電型層１１１を第２導電型層１１１ａと第２導電型層１１１ｂとに分断する。第２導電型層１１１ｂ上には第２電極１２１が成膜されている。一方、第２導電型層１１１ａ上には第１電極１３１が成膜されているが、当該第１電極１３１は、第２導電型層１１１ａ上のみでなく溝パターンの壁に沿っても成膜され、露出している第１導電型層１１３と接触して接触部１３５、１３６を形成し、電気的コンタクトを確保している。
この際、当該第１電極１３１と第２導電型層１１１ａの上面および第２導電型層１１１ａの側面および発光層１１２の側面にも電気的接触が形成され得る。しかし、電流は第１導電体側電極パッド１４１から第１電極１３１を経由して第１導電型層のみへ流れるので、第２導電型層１１１ａや発光層１１２への電気的接触は無視出来る。そこで本発明において、これらの電気的接触を電気的コンタクトであるとは考えないこととした。
A groove pattern is dug in the semiconductor layer, an exposed portion 115 of the first conductivity type layer is formed, and the first conductivity type layer 113 is exposed. Further, the groove pattern divides the second conductivity type layer 111 into a second conductivity type layer 111a and a second conductivity type layer 111b. A second electrode 121 is formed on the second conductivity type layer 111b. On the other hand, the first electrode 131 is formed on the second conductivity type layer 111a, but the first electrode 131 is formed not only on the second conductivity type layer 111a but also along the walls of the groove pattern. The contact portions 135 and 136 are formed in contact with the exposed first conductivity type layer 113 to ensure electrical contact.
At this time, electrical contact can also be formed on the upper surface of the first electrode 131 and the second conductivity type layer 111a, the side surface of the second conductivity type layer 111a, and the side surface of the light emitting layer 112. However, since the current flows only from the first conductor side electrode pad 141 via the first electrode 131 to the first conductivity type layer, the electrical contact to the second conductivity type layer 111a and the light emitting layer 112 can be ignored. Therefore, in the present invention, these electrical contacts are not considered to be electrical contacts.
この結果、第１導電体側電極パッド１４１は、当該第１導電型の電極パッドを起点とし、前記露出した第１導電型層１１５へ互いに独立してコンタクトする３本の導電配線である第２導電型層の凸部上の第１電極の成膜１３１ａ、第２導電型層であって凸部でない部分における第１電極の成膜１３１ｂ、第１導電体の露出部接触する第１電極の成膜１３１ｃにより、前記第１導電型層の露出部１１５に設けられ互いに独立した、第１電極の成膜と第１導電型層との接触部１３５、左右２箇所の第２導電型層の凸部の両端から左右方向に向けた第１電極の成膜と第１導電型層との接触部１３６の３箇所と、それぞれ電気的にコンタクトする。
ここで、所望により、第１電極の構造を変えることで露出した第１導電型層へ互いに独立してコンタクトする導電配線を４本またはそれ以上とし、併せて、第１電極の成膜と第１導電型層との接触部、第２導電型層の凸部から各方向に向けた第１電極の成膜と第１導電型層との、互いに独立した接触部を４箇所以上設けることも好ましい構成である。
尚、島状の第２導電型層１１１ａを用いて、１つの第１導電体側電極パッド１４１に対して、２箇所以上の互いに独立した第１導電型層１１３との接触部を形成し、複数の電気的コンタクトを形成することが出来るものであれば、例示した形状に限られるものではない。
ここで、第１電極１３１は、第２導電型層１１１ａや発光層１１２とは電気的に絶縁されていることが好ましい。当該絶縁により、半導体表面に電流が漏れ流れてしまうのを防ぐことが出来るためである。
As a result, the first conductor-side electrode pad 141 is the second conductive line that is the three conductive wirings that contact the exposed first conductive type layer 115 independently from each other, starting from the first conductive type electrode pad. Film formation 131a of the first electrode on the convex portion of the mold layer, film formation 131b of the first electrode in the second conductive type layer that is not the convex portion, and formation of the first electrode in contact with the exposed portion of the first conductor The film 131c is provided on the exposed portion 115 of the first conductivity type layer and is independent of each other, the first electrode film formation and the contact portion 135 between the first conductivity type layer and the left and right second conductivity type layer protrusions. The first electrode film is formed in contact with the three portions of the contact portion 136 between the film formation of the first electrode and the first conductivity type layer from both ends of the portion in the left-right direction.
Here, if desired, there may be four or more conductive wirings that contact each other independently to the exposed first conductive type layer by changing the structure of the first electrode. It is also possible to provide four or more independent contact portions between the contact portion with the first conductivity type layer and the film formation of the first electrode and the first conductivity type layer in each direction from the convex portion of the second conductivity type layer. This is a preferred configuration.
The island-shaped second conductivity type layer 111a is used to form contact portions with two or more independent first conductivity type layers 113 with respect to one first conductor-side electrode pad 141. As long as the electrical contact can be formed, the shape is not limited to the exemplified shape.
Here, the first electrode 131 is preferably electrically insulated from the second conductivity type layer 111 a and the light emitting layer 112. This is because current can be prevented from leaking to the semiconductor surface by the insulation.
そして、第１電極１３１上には第１導電体側電極パッド１４１が成膜されている。さらに、図４に示すように第２電極１２１上には第２導電体側電極パッド１４２が成膜されている。パッド電極は第１導電体側と第２導電体側とを同時に形成することも、別の工程で厚さを変えて形成することも可能であり、第１電極１３１と、第２電極１２１との膜厚の差に合わせて、容易且つ正確に、第１導電型層１１３から第１および第２導電体側電極パッド１４１、１４２の上面までの寸法を等しく（本発明においては、寸法差２００ｎｍ以下）にすることが出来る。従来のように露出した第１導電型層上に直接第１導電体側電極パッド１４１を形成する場合には、第１導電型層１１３から第２導電体側電極パッド１４２の上面までの寸法差は例えば１．３ｕｍ以上となることから、第１導電体側電極パッド１４１の厚さを非常に厚くする以外にパッド電極の高さを合わせることは困難である。当該高さを合わせた厚さを有する第１導電体側電極パッドを形成する場合、蒸着法では生産コスト高となる為メッキ法の適用が考えられるものの、メッキ法では数ｎｍでの厚さ制御は困難である。
従って、当該構成により、相対的に小さい第２導電型層１１１ａをエッチング除去しないことで、発光体素子チップ１００のワイヤボンディング工程やフリップチップ実装工程において、ボンディング位置（高さ）をｐｎ毎に変える必要が無く、ボンディングが容易になるとともに、接続不良やチップが傾くなどの不良を抑えることを、低コスト且つ精度よく達成することができた。
A first conductor side electrode pad 141 is formed on the first electrode 131. Further, as shown in FIG. 4, a second conductor side electrode pad 142 is formed on the second electrode 121. The pad electrode can be formed on the first conductor side and the second conductor side at the same time, or can be formed by changing the thickness in a separate process, and the film of the first electrode 131 and the second electrode 121 can be formed. The dimensions from the first conductivity type layer 113 to the upper surfaces of the first and second conductor side electrode pads 141 and 142 are made equal to each other according to the thickness difference (in the present invention, the dimension difference is 200 nm or less). I can do it. When the first conductor side electrode pad 141 is formed directly on the exposed first conductivity type layer as in the prior art, the dimensional difference from the first conductivity type layer 113 to the upper surface of the second conductor side electrode pad 142 is, for example, Since the thickness is 1.3 μm or more, it is difficult to match the height of the pad electrode except that the thickness of the first conductor-side electrode pad 141 is very large. In the case of forming the first conductor side electrode pad having a thickness corresponding to the height, the plating method can be applied because the production cost is high in the vapor deposition method, but the thickness control in a few nm is possible in the plating method. Have difficulty.
Accordingly, with this configuration, the relatively small second conductivity type layer 111a is not removed by etching, so that the bonding position (height) is changed for each pn in the wire bonding process or flip chip mounting process of the light emitting element chip 100. This eliminates the need for bonding, facilitates bonding, and suppresses defects such as poor connection and tilting of the chip.
本発明に係る発光素子チップ１００に電流を流したところ、発光効率の高い発光素子であることが判明した。これは、第１導電型層１１３に均一に拡散した電流が流れ、発光層１１２において均一且つ高効率な発光が行われた為と考えられる。
当該電流の流れについて、上述したように、第１導電型層１１３がｎ型のＡｌＧａＮ、第２導電型層がｐ型のＡｌＧａＮ、発光層がＡｌＩｎＧａＮのIII−Ｖ族半導体である場合を例として説明する。
第１導電体側電極パッド１４１に流れ込む電子は、金属伝導性を有する第１電極１３１を容易に通過して、接触部１３５、１３６から第１導電型層１１３へ流れ込む。本実施の形態において、接触部１３５、１３６は第１導電型層１１３上に分散し且つ広範囲に設けられているので、電子は広範囲な第１導電型層１１３中へ、均一に流れ込む。第１導電型層１１３中へ流れ込んだ電子は、広い範囲で均一に発光層１１２を通過し、発光層１１２において均一且つ高効率な発光が行われる。その後、第２導電型層１１１から金属伝導性を有する第２電極１２１へ流れ込み、さらに第２導電体側電極パッド１４２から流れ出て行く。ここで、第２導電体側電極パッド１４２が複数箇所分散して設けられていることも、第１導電型層１１３中へ流れ込んだ電子が、広い範囲で均一に発光層１１２を通過することを担保している。つまり、（００２６）段落の説明と同様に、Ｘ＜ＹかつＸ＋Ｙ≧３とすることが好ましく、非直線的に配置することが好ましい。
When a current was passed through the light emitting element chip 100 according to the present invention, it was found that the light emitting element had high luminous efficiency. This is presumably because the uniformly diffused current flows through the first conductivity type layer 113 and the light emitting layer 112 emits light uniformly and with high efficiency.
As for the current flow, as described above, the first conductivity type layer 113 is n-type AlGaN, the second conductivity type layer is p-type AlGaN, and the light emitting layer is an AlInGaN III-V group semiconductor as an example. explain.
The electrons that flow into the first conductor-side electrode pad 141 easily pass through the first electrode 131 having metal conductivity, and flow into the first conductivity type layer 113 from the contact portions 135 and 136. In the present embodiment, since the contact portions 135 and 136 are dispersed on the first conductivity type layer 113 and provided over a wide range, electrons flow uniformly into the first conductivity type layer 113 over a wide range. The electrons that flow into the first conductivity type layer 113 uniformly pass through the light emitting layer 112 over a wide range, and the light emitting layer 112 emits light uniformly and with high efficiency. Thereafter, it flows from the second conductivity type layer 111 to the second electrode 121 having metal conductivity, and further flows out from the second conductor side electrode pad 142. Here, the second conductor-side electrode pads 142 are provided in a plurality of locations to ensure that the electrons flowing into the first conductivity type layer 113 pass through the light emitting layer 112 uniformly over a wide range. doing. That is, as in the description of the paragraph (0026), it is preferable that X <Y and X + Y ≧ 3, and it is preferable to arrange them non-linearly.
以上、詳細に説明したように本発明によれば、１つのパッド電極に対して複数に分散された接触部を配置することが出来る。その結果、第１導電型層、発光層および第２導電型層へ均一に電流を拡散させることが出来、電流集中による特性劣化や、寿命短縮の少ない発光素子を得ることができた。
さらに、本発明では第１および第２導電体側電極パッドの高さを容易に等しく出来る。この結果、ワイヤボンディングやフリップチップ実装の際、ボンディング位置を、第１および第２導電体側電極パッド毎に変える必要が無く、ボンディングが容易になるとともに、接続不良やチップが傾くなどの不良を抑えることができる。
なお、相対的に小さい第２導電型層１１１ａを残し、その上面および側面を利用して、互いに独立して分散した第１導電型層へのコンタクト部へ分岐する電極配線を形成する構成をとれば、チップサイズや第２電極パッド１４２の形状に合わせて、第１電極１３１の形状を櫛型や放射状等とすることもできる。
As described above in detail, according to the present invention, a plurality of contact portions distributed to one pad electrode can be arranged. As a result, a current can be uniformly diffused to the first conductive type layer, the light emitting layer, and the second conductive type layer, and a light emitting element with less characteristic deterioration due to current concentration and less lifespan can be obtained.
Furthermore, in the present invention, the heights of the first and second conductor side electrode pads can be easily made equal. As a result, there is no need to change the bonding position for each of the first and second conductor-side electrode pads during wire bonding or flip chip mounting, and bonding is facilitated and defects such as poor connection and tilting of the chip are suppressed. be able to.
It should be noted that the second conductive type layer 111a is relatively small, and the upper and side surfaces of the second conductive type layer 111a are used to form electrode wirings that branch to contact portions to the first conductive type layers that are dispersed independently of each other. For example, according to the chip size and the shape of the second electrode pad 142, the shape of the first electrode 131 can be a comb shape, a radial shape, or the like.
以下、実施例を用いて、本発明をより具体的に説明する。
（実施例１）
成長基板（図示していない。）としてサファイア基板にＡｌＮバッファを有するＡｌＮテンプレートを準備し、当該成長基板上に、厚さ７４５ｎｍの超格子バッファ層（図示していない。）、第１導電型層１１３として厚さ１７２２ｎｍのｎ−ＡｌＧａＮ層、発光層１１２として厚さ１８４ｎｍのＭＱＷ活性層、第２導電型層１１１として厚さ２８２ｎｍのｐ−ＡｌＧａＮ層、コンタクト層（図示していない。）として、厚さ２２ｎｍのｐ−ＧａＮを有する発光波長４６５ｎｍの発光構造サンプルを作製した。
Hereinafter, the present invention will be described more specifically with reference to examples.
Example 1
An AlN template having an AlN buffer on a sapphire substrate is prepared as a growth substrate (not shown), a superlattice buffer layer (not shown) having a thickness of 745 nm, a first conductivity type layer is formed on the growth substrate. As an n-AlGaN layer having a thickness of 1722 nm as an 113, an MQW active layer having a thickness of 184 nm as a light emitting layer 112, a p-AlGaN layer having a thickness of 282 nm as a second conductivity type layer 111, and a contact layer (not shown). A light-emitting structure sample having an emission wavelength of 465 nm and p-GaN having a thickness of 22 nm was produced.
当該発光構造サンプルに対し、適宜な表面洗浄およびアニールの後、ｐ−ＧａＮコンタクト層上にフォトリソ法を用いてＲＩＥ用のＳｉＯ２マスクを形成した。そして、当該ＳｉＯ２マスクから露出した部分を、ＲＩＥを用いてｐ−ＧａＮコンタクト層からｎ−ＡｌＧａＮ層まで、ｎ−ＡｌＧａＮ層の一部が露出するように、深さ約１．３μｍのエッチングを行った。当該エッチングにより、実施例１に係る素子を個々に分割する第１導電型層の露出部１１５である分離溝が形成され、当該分割溝によって分割された個々の実施例１に係る発光素子チップ１００において、さらに、当該分割溝により発光体となる相対的に大きい第２導電型層１１１ｂと、ｎ電極パッド形成部となる相対的に小さい第２導電型層１１１ａとを分割した。その後、ＳｉＯ２マスクを除去した。 The light emitting structure sample was subjected to appropriate surface cleaning and annealing, and then a RIE SiO 2 mask was formed on the p-GaN contact layer using a photolithography method. Then, the portion exposed from the SiO 2 mask is etched to a depth of about 1.3 μm using RIE so that a part of the n-AlGaN layer is exposed from the p-GaN contact layer to the n-AlGaN layer. went. By the etching, separation grooves that are exposed portions 115 of the first conductivity type layers that individually divide the elements according to the first embodiment are formed, and the light-emitting element chips 100 according to the first embodiment divided by the division grooves. Further, the relatively large second conductivity type layer 111b serving as a light emitter and the relatively small second conductivity type layer 111a serving as an n-electrode pad forming portion were divided by the dividing groove. Thereafter, the SiO 2 mask was removed.
まず、相対的に大きい第２導電型層１１１ｂであるｐ−ＡｌＧａＮ層上においては、ｐ−ＧａＮコンタクト層上へ、スパッタ法により第２電極１２１である厚さ５ｎｍのＮｉ層、および、厚さ２０ｎｍのＡｕ層を製膜してｐ電極を形成し、当該ｐ電極以外の部分はエッチング除去した。
一方、相対的に小さい第２導電型層１１１ａであるｐ−ＡｌＧａＮ層上においては、ｐ−ＧａＮコンタクト層から露出したｎ−ＡｌＧａＮ層上の一部（独立して分散した各々のコンタクト部）までを露出するようにフォトリソ法を用いてレジストマスクを形成する。ここで、コンタクト部が独立して分散するような電気配線形状となるように、第２導電型層１１１ａ上の一部にもレジストマスクを形成する。そしてスパッタ法により第１電極１３１として、厚さ１８ｎｍのＴｉ層、厚さ３００ｎｍのＡｌ層、厚さ５ｎｍのＴｉ層を製膜後、リフトオフして、第２導電型層の凸部より一回り大きく第１導電型層へ延伸する形状の第１電極の成膜１３１ａ、第２導電型層であって凸部でない部分において第２導電型層上のみに形成される第１電極の成膜１３１ｂ、成膜１３１ｂの電気配線を経由して第１導電体の露出部に接触する第１電極の成膜１３１ｃを有するｎ電極を一体的に形成した。この際、ｎ電極は、相対的に小さい方の第２導電型層１１１ａ上から露出したｎ−ＡｌＧａＮ層上の一部（分散した各々のコンタクト部）まで、分割部の側面を含めて延伸した電気配線となる。
First, on the p-AlGaN layer that is the relatively large second conductivity type layer 111b, a Ni layer having a thickness of 5 nm that is the second electrode 121 is formed on the p-GaN contact layer by sputtering, and the thickness is increased. A 20-nm Au layer was formed to form a p-electrode, and portions other than the p-electrode were removed by etching.
On the other hand, on the p-AlGaN layer which is the relatively small second conductivity type layer 111a, up to a part (each contact portion dispersed independently) on the n-AlGaN layer exposed from the p-GaN contact layer. A resist mask is formed using a photolithography method so as to expose the film. Here, a resist mask is also formed on a part of the second conductivity type layer 111a so as to have an electric wiring shape in which the contact portions are dispersed independently. Then, after forming a 18-nm-thick Ti layer, a 300-nm-thick Al layer, and a 5-nm-thick Ti layer as the first electrode 131 by the sputtering method, lift-off is performed, and the first electrode 131 makes a round from the convex portion of the second conductivity type layer. Film formation 131a of the first electrode largely extending to the first conductivity type layer, film formation 131b of the first electrode formed only on the second conductivity type layer in the second conductivity type layer, which is not the convex portion Then, an n electrode having a first electrode film 131c that contacts the exposed portion of the first conductor via the electric wiring of the film 131b was integrally formed. At this time, the n electrode extended from the relatively small second conductivity type layer 111a to a part (each dispersed contact portion) on the exposed n-AlGaN layer, including the side surfaces of the divided portions. Electric wiring.
ここで、５５０℃のアニールにより、相対的に大きい第２導電型層１１１ｂにおいてはｐ電極とｐコンタクト層との電気的コンタクトが形成され、相対的に小さい第２導電型層１１１ａ周辺の露出した第１導電型層１１３とｎ電極との接触部１３５および左右の接触部１３６において電気的コンタクト（オーミック接続）が形成された。
この結果、第１導電側電極パッド１４１は、当該第１導電型の電極パッドを起点とし、前記露出した第１導電型層へ延伸する導電配線である第２導電型層の凸部上の第１電極の成膜１３１ａ、第２導電型層であって凸部でない部分における第１電極の成膜１３１ｂ、第１導電体の露出部接触する第１電極の成膜１３１ｃにより、前記第１導電型層の露出部１１５に設けられ互いに独立した、第１電極の成膜と第１導電型層との接触部１３５、左右２箇所の第２導電型層の凸部の両端から左右方向に向けた第１電極の成膜と第１導電型層との接触部１３６の３箇所とで、それぞれ電気的にコンタクトした。
Here, by the annealing at 550 ° C., an electrical contact between the p electrode and the p contact layer is formed in the relatively large second conductivity type layer 111b, and the periphery of the relatively small second conductivity type layer 111a is exposed. Electrical contact (ohmic connection) was formed at the contact portion 135 between the first conductivity type layer 113 and the n-electrode and the left and right contact portions 136.
As a result, the first conductive side electrode pad 141 starts from the first conductive type electrode pad, and the first conductive side electrode pad 141 is formed on the convex portion of the second conductive type layer which is a conductive wiring extending to the exposed first conductive type layer. The first conductive film 131a, the first conductive film 131b in the second conductive type layer that is not a convex portion, and the first conductive film 131c in contact with the exposed portion of the first conductor are used for the first conductive layer. From the both ends of the contact part 135 between the film formation of the first electrode and the first conductivity type layer and the left and right convex portions of the second conductivity type layer, which are provided in the exposed portion 115 of the mold layer and are independent from each other. Further, electrical contact was made at each of the three positions of the contact portion 136 between the film formation of the first electrode and the first conductivity type layer.
その後、ｐ電極上へ、当該ｐ電極の皮膜（図示していない。）として厚さ５０ｎｍのＰｔ層、厚さ１００ｎｍのＡｕ層、厚さ５ｎｍのＴｉ層を形成した。
次に、ｐ電極上およびｎ電極上の一部が露出するようにレジストマスクを設け、ｎ電極パッドおよびｐ電極パッドとして厚さ５ｎｍのＴｉ層、厚さ５００ｎｍのＡｕ層、厚さ１０ｎｍのＴｉ層を製膜後、リフトオフによりパッド電極を形成する。次に、保護膜としてＳｉＯ２層を全面に形成し、ｐ電極パッドおよびｎ電極パッド上の一部が露出するようにレジストでマスク後、パッド上のＳｉＯ２層およびＴｉ層をＲＩＥにて除去し、第１導電体側電極パッド１４１および第２導電体側電極パッド１４２となるＡｕパッド電極を形成する。
その後、レジストマスクを除去し、洗浄後、基板の研削・研磨を経て発光素子チップ１００の周囲に設けられた分離溝をスクライブすることにより、個々に分離された発光素子チップ１００を得た。
Thereafter, a Pt layer having a thickness of 50 nm, an Au layer having a thickness of 100 nm, and a Ti layer having a thickness of 5 nm were formed on the p electrode as a film (not shown) of the p electrode.
Next, a resist mask is provided so that a part on the p electrode and the n electrode is exposed, and a Ti layer having a thickness of 5 nm, an Au layer having a thickness of 500 nm, and a Ti layer having a thickness of 10 nm are used as the n electrode pad and the p electrode pad. After forming the layer, a pad electrode is formed by lift-off. Next, a SiO 2 layer is formed over the entire surface as a protective film, masked with a resist so that part of the p electrode pad and n electrode pad is exposed, and then the SiO 2 layer and Ti layer on the pad are removed by RIE. Then, an Au pad electrode to be the first conductor side electrode pad 141 and the second conductor side electrode pad 142 is formed.
Thereafter, the resist mask was removed, and after cleaning, the substrate was ground and polished, and the separation grooves provided around the light emitting element chip 100 were scribed to obtain individually separated light emitting element chips 100.
製造した実施例１に係る発光素子の発光状態を示す、約４８．５倍の光学顕微鏡による外観写真を図５に示す。当該発光素子の発光面積は、１．０４×１０−７ｍ２であった。そして、当該発光素子に２０ｍＡの電流を流したときの順方向電圧（Ｖｆ）は３．１１Ｖ、積分球による光出力（Ｐｏ）は３．２２ｍＷであった。
さらに、当該発光素子に１〜７０ｍＡの電流を流したときの発光波長を測定した。当該測定結果を図６に示す。図６は、横軸に測定電流の値をとり、縦軸に発光波長をとり、実施例１に係る発光素子試料５個の測定結果をプロットしたグラフである。
FIG. 5 shows an external appearance photograph taken with an optical microscope of about 48.5 times, showing the light emitting state of the manufactured light emitting device according to Example 1. The light emitting area of the light emitting element was 1.04 × 10 −7 m 2 . The forward voltage (Vf) when a current of 20 mA was passed through the light emitting element was 3.11 V, and the light output (Po) by the integrating sphere was 3.22 mW.
Furthermore, the emission wavelength when a current of 1 to 70 mA was passed through the light emitting element was measured. The measurement results are shown in FIG. FIG. 6 is a graph in which measurement values of five light emitting element samples according to Example 1 are plotted with the measurement current value on the horizontal axis and the emission wavelength on the vertical axis.
（比較例１）
「発明の詳細な説明」で説明した、第１導電型層の露出部１１５、第２導電型層であって凸部でない部分における第１電極の成膜１３１ｂおよび第１導電体の露出部接触する第１電極の成膜１３１ｃを設けなかった以外は、実施例１と同様の工程を行って、比較例１に係る発光素子を製造した。
(Comparative Example 1)
The exposed portion 115 of the first conductivity type layer, the film formation 131b of the first electrode in the portion of the second conductivity type layer that is not a convex portion, and the exposed portion contact of the first conductor described in “Detailed Description of the Invention” A light emitting device according to Comparative Example 1 was manufactured by performing the same process as in Example 1 except that the first electrode film 131c was not provided.
図９（ａ）〜（ｅ）は、比較例１に係る発光体素子およびその製造方法に係る平面図である。 9A to 9E are plan views according to the light emitting device and the manufacturing method thereof according to Comparative Example 1. FIG.
図９（ｂ）に示すように、比較例１においても実施例１と同様に、第１導電型層の露出部１１５を形成し、第１導電型層１１３を露出させた。但し、実施例１に係る発光素子と異なり、第１電極１３１と第１導電型層１１３との接触部は、第１導電体側電極パッド１４１の周囲（即ち、連続する１箇所）のみとし、第１導電型層の露出部１１５、第２導電型層１１１とも左右に展開していない。 As shown in FIG. 9B, in the first comparative example, as in the first example, the exposed portion 115 of the first conductive type layer was formed, and the first conductive type layer 113 was exposed. However, unlike the light emitting device according to Example 1, the contact portion between the first electrode 131 and the first conductivity type layer 113 is only around the first conductor-side electrode pad 141 (that is, one continuous location), and Neither the exposed portion 115 of the first conductivity type layer nor the second conductivity type layer 111 is developed left and right.
図９（ｄ）に示すように、比較例１では実施例１と異なり、第１導電型層の露出部１１５が左右に展開していないので、第２導電型層１１１ａであって凸部上の第１電極１３１の成膜である１３１ａは、当該凸部から第１導電型層の露出部１１５へかけて成膜される。この結果、当該凸部の周辺に第１電極１３１の成膜である１３１ａと第１導電型層１１３との接触部１３５が形成された。 As shown in FIG. 9 (d), unlike the first embodiment, the first conductive type layer exposed portion 115 does not expand from side to side in the comparative example 1, so that the second conductive type layer 111a is formed on the convex portion. The first electrode 131 is formed from 131a to the exposed portion 115 of the first conductivity type layer. As a result, a contact portion 135 between 131a, which is the film formation of the first electrode 131, and the first conductivity type layer 113 was formed around the convex portion.
図９（ｅ）に示すように、上記工程により比較例１に係る発光素子として、発光波長４６５ｎｍの青色ＬＥＤが製造された。 As shown in FIG. 9E, a blue LED having an emission wavelength of 465 nm was manufactured as a light emitting element according to Comparative Example 1 by the above process.
製造した比較例１に係る発光素子の発光状態を示す、約４８．５倍の外観写真を図７に示す。当該発光素子の発光面積は、１．４２×１０−７ｍ２であった。
そして、当該発光素子に２０ｍＡの電流を流したときのＶｆは３．０３Ｖ、Ｐｏは３．４５ｍＷであった。
さらに、比較例１の発光素子に１〜７０ｍＡの電流を流したときの発光波長を測定した。測定結果を図８に示す。図８は、横軸に測定電流の値をとり、縦軸に発光波長をとり、比較例１に係る発光素子試料３個の測定結果を平均して−□−にてプロットしたグラフである。尚、参考のため、図８には、実施例１に係る発光素子試料から選択した１個の測定結果も−◇−にてプロットした。
FIG. 7 shows an external appearance photograph of about 48.5 times showing the light emitting state of the manufactured light emitting device according to Comparative Example 1. The light emitting area of the light emitting element was 1.42 × 10 −7 m 2 .
When a current of 20 mA was passed through the light emitting element, Vf was 3.03 V and Po was 3.45 mW.
Furthermore, the emission wavelength when a current of 1 to 70 mA was passed through the light emitting device of Comparative Example 1 was measured. The measurement results are shown in FIG. FIG. 8 is a graph in which the horizontal axis represents the measured current value, the vertical axis represents the emission wavelength, and the measurement results of three light emitting element samples according to Comparative Example 1 were averaged and plotted with − □ −. For reference, in FIG. 8, one measurement result selected from the light-emitting element sample according to Example 1 is also plotted with − ◇ −.
（比較例２）
相対的に小さい第２導電型層の形状を、比較例１と同様の形状にした以外は、実施例１と同様の操作を行って、比較例２に係る発光素子を製造した。 図１０（ａ）〜（ｅ）は、比較例２に係る発光体素子およびその製造方法に係る平面図である。
(Comparative Example 2)
A light emitting device according to Comparative Example 2 was manufactured by performing the same operation as in Example 1 except that the shape of the relatively small second conductivity type layer was changed to the same shape as in Comparative Example 1. 10A to 10E are plan views according to the light emitting device and the manufacturing method thereof according to Comparative Example 2.
図１０（ｂ）に示すように、比較例２においては相対的に小さい第２導電型層１１１ａの形状を、比較例１と同様に第１導電体側電極パッド１４１の周囲のみとし、左右の展開のない形状に形成した。 As shown in FIG. 10B, the comparatively small second conductive type layer 111a in the comparative example 2 has only the periphery of the first conductor-side electrode pad 141 as in the comparative example 1, and the left and right developments. It was formed in the shape without.
図１０（ｄ）に示すように、比較例２においては実施例１と異なり、第２導電型層１１１ａが左右に展開していないが、第１電極１３１の成膜である１３１ａは、当該凸部から第１導電型層の露出部１１５へかけて成膜される。
この結果、比較例２に係る発光素子においては、実施例１に係る発光素子と異なり、第２導電型層１１１ａの上面および側面を利用するものの、互いに独立して分散した第１導電型層のための電極配線を形成しておらず、第１電極１３１と第１導電型層１１３との接触部（電気的コンタクト）が互いに独立していない。この為、第１導電体側電極パッド１４１の周囲と、左右に延伸する配線部の全てが連続した構造を有している。
As shown in FIG. 10D, unlike Comparative Example 2, in Comparative Example 2, the second conductivity type layer 111a does not expand left and right. However, 131a, which is the film formation of the first electrode 131, is The film is formed from the portion to the exposed portion 115 of the first conductivity type layer.
As a result, in the light emitting element according to Comparative Example 2, unlike the light emitting element according to Example 1, the first conductive type layers dispersed independently of each other are used although the upper surface and the side surface of the second conductive type layer 111a are used. Therefore, the contact portion (electrical contact) between the first electrode 131 and the first conductivity type layer 113 is not independent of each other. For this reason, the circumference | surroundings of the 1st conductor side electrode pad 141 and all the wiring parts extended | stretched right and left have a continuous structure.
図１０（ｅ）に示すように、上記工程により比較例２に係る発光素子として、発光波長４６５ｎｍの青色ＬＥＤが製造された。 As shown in FIG. 10E, a blue LED having an emission wavelength of 465 nm was manufactured as a light emitting element according to Comparative Example 2 by the above process.
比較例２に係る発光素子の発光面積は、１．０４×１０−７ｍ２であった。そして、当該発光素子に２０ｍＡの電流を流したときの、Ｖｆは３．０１Ｖ、Ｐｏは３．５２ｍＷであった。
比較例２に係る発光素子試料測定結果も、図８に−△−にてプロットした。
The light emitting area of the light emitting device according to Comparative Example 2 was 1.04 × 10 −7 m 2 . When a current of 20 mA was passed through the light emitting element, Vf was 3.01 V and Po was 3.52 mW.
The light-emitting element sample measurement results according to Comparative Example 2 are also plotted in FIG.
（比較例３）
相対的に小さい第２導電型層を形成せず、比較例２の相対的に小さい第２導電型層の箇所の第１導電型層を露出させた以外は、実施例１と同様の操作を行って、比較例３に係る発光素子を製造した。
(Comparative Example 3)
The same operation as in Example 1 was performed except that the relatively small second conductivity type layer was not formed and the first conductivity type layer at the relatively small second conductivity type layer in Comparative Example 2 was exposed. As a result, a light emitting device according to Comparative Example 3 was manufactured.
図１１（ａ）〜（ｅ）は、比較例２に係る発光体素子およびその製造方法に係る平面図である。 11A to 11E are plan views according to the light emitting device and the manufacturing method thereof according to Comparative Example 2. FIG.
図１１（ｂ）に示すように、比較例３においては実施例１と異なり、相対的に小さい第２導電型層となる部分にＳｉＯ２マスクを形成せず、ＲＩＥにより露出部形成時に他と共にエッチング除去し、相対的に小さい第２導電型層１１１ａを形成しなかった。 As shown in FIG. 11B, unlike Comparative Example 3, Comparative Example 3 does not form a SiO 2 mask in a portion that becomes a relatively small second conductivity type layer, and together with others when forming an exposed portion by RIE. Etching was removed, and the relatively small second conductivity type layer 111a was not formed.
図１１（ｄ）に示すように、比較例３においては実施例１と異なり、第２導電型層１１１ａが形成されていないが、第１電極１３１の成膜である１３１ａは、当該凸部から第１導電型層の露出部１１５へかけて成膜される。
この結果、実施例１と同様の形状の第１電極１３１の形成が、第１導電型層１１３上に直接行なわれた構造を有している。そして、第１電極１３１と第１導電型層１１５との接触部（電気的コンタクト）が互いに独立しておらず、第１導電体側電極パッド１４１の周囲と、左右に延伸する配線部の全てが連続した構造である点は、比較例２と同様である。
As shown in FIG. 11 (d), the second conductive type layer 111a is not formed in the comparative example 3 unlike the first example, but the first electrode 131 is formed from the convex portion 131a. The film is formed over the exposed portion 115 of the first conductivity type layer.
As a result, the first electrode 131 having the same shape as that of the first embodiment is directly formed on the first conductivity type layer 113. Further, the contact portion (electrical contact) between the first electrode 131 and the first conductivity type layer 115 is not independent from each other, and the entire periphery of the first conductor side electrode pad 141 and the wiring portion extending to the left and right are The point which is a continuous structure is the same as that of the comparative example 2.
図１１（ｅ）に示すように、上記工程により比較例３に係る発光素子として、発光波長４６５ｎｍの青色ＬＥＤが製造された。 As shown in FIG. 11E, a blue LED having an emission wavelength of 465 nm was manufactured as a light emitting element according to Comparative Example 3 by the above process.
（まとめ）
実施例１に係る発光素子と比較例１に係る発光素子とでは、第１導電型層の形状が異なる。当該形状の違いにより第２電極の形状と発光面積が異なり、比較例１に係る発光素子の方が発光面積は広い。発光面積が広いため、比較例１に係る発光素子の方が、わずかにＶｆが低くＰｏも高い。しかしながら比較例１に係る発光素子は、図８に示すように当該発光素子に流す電流量の変化による発光波長のシフト量が多い。これは、比較例１に係る発光素子においては、電流が発光層の一部に集中して流れる為、当該集中部に発熱が起こり、当該発熱により発光波長が変化するのであると考えられる。
(Summary)
The light emitting element according to Example 1 and the light emitting element according to Comparative Example 1 have different shapes of the first conductivity type layer. Due to the difference in shape, the shape of the second electrode and the light emitting area are different, and the light emitting element according to Comparative Example 1 has a larger light emitting area. Since the light emitting area is wide, the light emitting element according to Comparative Example 1 has a slightly lower Vf and a higher Po. However, the light emitting element according to Comparative Example 1 has a large shift amount of the emission wavelength due to the change in the amount of current passed through the light emitting element as shown in FIG. This is presumably because, in the light emitting element according to Comparative Example 1, the current flows in a concentrated manner in a part of the light emitting layer, so that heat is generated in the concentrated portion, and the emission wavelength is changed by the heat generation.
また、実施例１に係る発光素子と比較例２に係る発光素子とを比較すると、両者とも発光面積は同じである。しかし、実施例１に係る発光素子では電気的コンタクトが互いに独立するのに対し、比較例２に係る発光素子では当該電気的コンタクトが連続するとの差異がある。当該電気的コンタクトの差異の為、２０ｍＡ通電時において比較例２に係る発光素子は、実施例１に係る発光素子に比べ、わずかにＶｆが低くＰｏも高い。しかし、比較例２に係る発光素子は、図８に示すように上述した比較例１に係る発光素子と同様に、発光素子に流す電流量の変化による発光波長のシフト量が多い。なお、比較例３に係る発光素子は、比較例２に係る発光素子と同様の傾向を示した（図８には図示していない。）。
これは、比較例２に係る発光素子においても、上述した比較例１に係る発光素子と同様にパッド電極周辺からの電流の流れが優先され、電流が発光層の一部に集中して流れる結果、当該電流集中部に発熱が起こり、当該発熱により発光波長が変化したものであると考えられる。当該状況は、比較例３に係る発光素子においても同様であると考えられる。
さらに、当該発熱による発光効率の低下により、電流量が５０ｍＡを超えると、実施例１に係る発光素子および比較例２に係る発光素子のＰｏは同水準となる。
室温下における電流量４０ｍＡでの通電寿命試験で、実施例１に係る発光素子は１０００時間において初期出力の９２％の出力が維持されたが、比較例２に係る発光素子は１０００時間において初期出力の８８％の出力となった。
以上のことから、実施例１に係る発光素子は、比較例１、２および３に係る発光素子に比べ、電流集中による特性劣化がなく、寿命の長い優れた発光素子であることが判明した。
Further, when the light emitting device according to Example 1 and the light emitting device according to Comparative Example 2 are compared, both have the same light emitting area. However, in the light emitting element according to Example 1, the electrical contacts are independent from each other, whereas in the light emitting element according to Comparative Example 2, there is a difference that the electrical contacts are continuous. Due to the difference in electrical contact, the light emitting device according to Comparative Example 2 has a slightly lower Vf and a higher Po than the light emitting device according to Example 1 when the current is applied at 20 mA. However, as shown in FIG. 8, the light emitting element according to Comparative Example 2 has a large shift amount of the emission wavelength due to the change in the amount of current passed through the light emitting element, like the light emitting element according to Comparative Example 1 described above. In addition, the light emitting element which concerns on the comparative example 3 showed the tendency similar to the light emitting element which concerns on the comparative example 2 (not shown in FIG. 8).
This is because, in the light emitting element according to Comparative Example 2, as in the light emitting element according to Comparative Example 1 described above, priority is given to the flow of current from the periphery of the pad electrode, and the current flows concentrated in a part of the light emitting layer. It is considered that heat is generated in the current concentration portion and the emission wavelength is changed by the heat generation. This situation is considered to be the same for the light emitting device according to Comparative Example 3.
Furthermore, when the amount of current exceeds 50 mA due to a decrease in light emission efficiency due to the heat generation, the Po of the light emitting element according to Example 1 and the light emitting element according to Comparative Example 2 becomes the same level.
In an energization life test at a current amount of 40 mA at room temperature, the light emitting device according to Example 1 maintained 92% of the initial output at 1000 hours, whereas the light emitting device according to Comparative Example 2 had an initial output at 1000 hours. The output was 88%.
From the above, it was found that the light-emitting element according to Example 1 is an excellent light-emitting element with no long-term lifetime and no deterioration in characteristics due to current concentration as compared with the light-emitting elements according to Comparative Examples 1, 2, and 3.
一方、比較例３に係る発光素子においては、第１電極と第２電極との間の寸法差は１．３μｍとなった。この結果、後工程であるフリップチップ実装工程において、第１導電体側電極パッドと第２導電体側電極パッド上に約１００μｍサイズの金バンプを接着後、熱圧着でチップを接着したところ、比較例３に係る発光素子には接続不良が５％発生した。
これに対し、実施例１および比較例１、２に係る発光素子においては、上述した比較例３と同じ実装方法を実施した場合においても、接続不良は発生しなかった。
以上のことから、実施例１に係る発光素子は、比較例３に係る発光素子に比べ、フリップチップ実装工程での接続不良が発生しないという、生産性に優れた発光素子であることが判明した。
以上のことから、本発明に係る発光素子は、電流集中による特性劣化や、寿命短縮が少なく、さらに実装不良も少ないという、信頼性に優れた発光素子であることが分かる。
On the other hand, in the light emitting device according to Comparative Example 3, the dimensional difference between the first electrode and the second electrode was 1.3 μm. As a result, in a flip chip mounting process, which is a subsequent process, a gold bump having a size of about 100 μm was bonded on the first conductor side electrode pad and the second conductor side electrode pad, and then the chip was bonded by thermocompression bonding. In the light emitting device according to the above, connection failure occurred 5%.
On the other hand, in the light emitting elements according to Example 1 and Comparative Examples 1 and 2, no connection failure occurred even when the same mounting method as in Comparative Example 3 was performed.
From the above, it was found that the light-emitting element according to Example 1 is a light-emitting element with excellent productivity that does not cause poor connection in the flip chip mounting process as compared with the light-emitting element according to Comparative Example 3. .
From the above, it can be seen that the light-emitting element according to the present invention is a highly reliable light-emitting element in which characteristic deterioration due to current concentration, lifetime reduction, and mounting defects are small.
１００ 発光素子チップ
１１１ 第２導電型層
１１１ａ 第２導電型層
１１１ｂ 第２導電型層
１１２ 発光層
１１３ 第１導電型層
１１５ 第１導電型層の露出部
１２１ 第２電極
１３１ 第１電極
１３１ａ 第２導電型層の凸部上の第１電極の成膜
１３１ｂ 第２導電型層であって凸部でない部分における第１電極の成膜
１３１ｃ 第１導電体の露出部接触する第１電極の成膜
１３５ 第１電極の成膜と第１導電型層との接触部
１３６ 第２導電型層の凸部の両端から左右方向に向けた第１電極の成膜と第１導電
体層との接触部
１４１ 第１導電体側電極パッド
１４２ 第２導電体側電極パッド
100 Light emitting device chip
111 2nd conductivity type layer 111a 2nd conductivity type layer 111b 2nd conductivity type layer 112 Light emitting layer 113 1st conductivity type layer 115 Exposed part of 1st conductivity type layer 121 2nd electrode 131 1st electrode 131a 2nd conductivity type layer Film formation of the first electrode on the convex portion 131b Film formation of the first electrode in the portion of the second conductivity type layer that is not the convex portion 131c Film formation of the first electrode in contact with the exposed portion of the first conductor 135 First Contact portion between electrode film formation and first conductivity type layer 136 Contact portion between first electrode film formation and first conductor layer from left and right sides of convex portion of second conductivity type layer 141 First Conductor side electrode pad 142 Second conductor side electrode pad
Claims (4)
前記第２導電型層と発光層を大小２部分に分断する溝構造を有し、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
当該第１導電型の電極パッドを起点として前記第１導電型層へ延伸する導電配線により、前記第１導電型層と接続し互いに独立した２箇所以上の電気的コンタクトを有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子。 Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
A groove structure that divides the second conductivity type layer and the light emitting layer into two parts,
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
The conductive wiring extending from the first conductive type electrode pad to the first conductive type layer has two or more electrical contacts connected to the first conductive type layer and independent from each other ,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
A light emitting device in which the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads satisfy X <Y and X + Y ≧ 3 .
前記第２導電型層が、前記第１導電型層の露出部を形成する溝構造により、大小２部分に分断されており、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
前記分断された小さい方の第２導電型層上および分断部側面に、前記第１導電型の電極パッドを起点とし、前記第１導電型層の露出部に設けられた互いに独立した２箇所以上の電気的コンタクトへ向けて延伸する導電配線を有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子。 Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
The second conductivity type layer is divided into two parts by a groove structure that forms an exposed portion of the first conductivity type layer;
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
Two or more independent portions provided on the exposed portion of the first conductivity type layer, starting from the electrode pad of the first conductivity type, on the divided second conductive type layer and on the side surface of the divided portion. It has a conductive wire which extends towards to the electrical contact,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
A light emitting device in which the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads satisfy X <Y and X + Y ≧ 3 .
前記第２導電型層が、前記第１導電型層の露出部を形成する溝構造により、大小２部分に分断されており、
当該分断された大きい方の第２導電型層上に第２導電型層と電気的に接続する第２導電型の電極パッドを有し、
当該分断された小さい方の第２導電型層上に第１導電型の電極パッドを有し、
当該第１導電型の電極パッドを起点として前記露出した第１導電型層へ延伸する導電配線により、前記第１導電型層の露出部に設けられた互いに独立した２箇所以上の電気的コンタクトを有し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとが等しく、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとが、Ｘ＜ＹかつＸ＋Ｙ≧３である発光素子。 Having a laminated structure in which a first conductivity type layer and a second conductivity type layer are provided with a light emitting layer interposed therebetween;
The second conductivity type layer is divided into two parts by a groove structure that forms an exposed portion of the first conductivity type layer;
A second conductive type electrode pad electrically connected to the second conductive type layer on the divided second conductive type layer;
A first conductivity type electrode pad on the divided second conductivity type layer;
Two or more independent electrical contacts provided on the exposed portion of the first conductivity type layer are formed by conductive wiring extending from the first conductivity type electrode pad to the exposed first conductivity type layer. Have
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
A light emitting device in which the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads satisfy X <Y and X + Y ≧ 3 .
前記第２導電型層側からエッチングにより第１導電型層を露出させて、前記第２導電型層を大小２部分に分断する溝構造を形成する工程と、
前記分断された大きい方の第２導電型層上に、第２導電型の電極パッドを形成する工程と、
前記分断された小さい方の第２導電型層上から、前記第１導電型層の露出部へ延伸する導電配線を形成する工程と、
前記分断された小さい方の第２導電型層上に、第１導電型の電極パッドを形成する工程を有し、
前記導電配線は、第１導電型層の露出部の一部に対し延伸しない部分を有し、
前記第１導電型の電極パッドを起点として、前記第１導電型層の露出部に対して互いに独立した２箇所以上の電気的コンタクトを形成し、
前記第１導電型層の底面から前記第２導電型の電極パッド上面迄の高さと、前記第１導電型層の底面から前記第１導電型の電極パッド上面迄の高さとを等しくし、
前記第１導電型の電極パッドの個数Ｘと、前記第２導電型の電極パッドの個数Ｙとを、Ｘ＜ＹかつＸ＋Ｙ≧３とする発光素子の製造方法。 Forming a laminated structure having a first conductivity type layer, a light emitting layer, and a second conductivity type layer on the substrate in order from the substrate side;
A step of exposing the first conductivity type layer by etching from the second conductivity type layer side to form a groove structure that divides the second conductivity type layer into two parts,
Forming a second conductivity type electrode pad on the divided second conductivity type layer; and
Forming a conductive wiring extending from the divided second conductive type layer to the exposed portion of the first conductive type layer;
Forming a first conductive type electrode pad on the divided second conductive type layer;
The conductive wiring has a portion not extending with respect to a part of the exposed portion of the first conductivity type layer,
Starting from the first conductive type electrode pad, two or more independent electrical contacts are formed with respect to the exposed portion of the first conductive type layer ,
The height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the second conductivity type is made equal to the height from the bottom surface of the first conductivity type layer to the upper surface of the electrode pad of the first conductivity type;
A method of manufacturing a light emitting device , wherein the number X of the first conductivity type electrode pads and the number Y of the second conductivity type electrode pads are X <Y and X + Y ≧ 3 .
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| JP5971090B2 (en) | 2012-11-14 | 2016-08-17 | 豊田合成株式会社 | Semiconductor light emitting element and light emitting device |
| JP6485019B2 (en) * | 2013-12-19 | 2019-03-20 | 日亜化学工業株式会社 | Semiconductor light emitting device |
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