JP5670700B2 - 集積半導体基板構造およびその製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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Description
本発明の第1態様によれば、第1の目的は、請求項1記載の発明に従って達成される。集積半導体基板構造は、基板と、GaNベース素子の区画のための第1素子エリアに存在し、少なくとも部分的に保護層で覆われているGaNヘテロ構造と、CMOS素子の区画のための第2素子エリアに存在する半導体基板層とを備える。ここで、GaNヘテロ構造および半導体基板層の少なくとも1つが、基板の少なくとも1つの溝(trench)に設けられ、GaNヘテロ構造および半導体基板層は、横方向に並置(juxtapose)される。このことは、集積半導体基板構造に少なくとも実質的に平坦化した表面が設けられるという利点を有する。
半導体基板を用意するステップと、
半導体基板上に保護層を形成するステップであって、保護層は、第1素子エリアにおける半導体基板を露出し又は露出したままにしてパターン化されるものであり、
第1素子エリアにおける半導体基板に少なくとも1つの溝を形成するステップと、
該少なくとも1つの溝にGaNヘテロ構造を選択成長させ、保護層を選択成長用マスクとして用いて第1素子エリアを区画するステップと、
保護層を少なくとも部分的に除去し、第2素子エリアを露出するステップと、を含む。
半導体基板を用意するステップと、
半導体基板上にGaNヘテロ構造を成長させるステップと、
GaNヘテロ構造の上部に保護層を付与するステップであって、保護層は、第2素子エリアにおけるGaNヘテロ構造を露出し又は露出したままにしてパターン化されるものであり、
GaNヘテロ構造を通る少なくとも1つの溝を形成し、第2素子エリアにおける基板の基板層を露出し、該少なくとも1つの溝に半導体層を選択成長させることによって、第2素子エリアに半導体基板層を設けるステップと、
保護層を少なくとも部分的に除去し、第1素子エリアを露出するステップと、を含む。
Claims (11)
- ハンドリング層(11)、埋め込み絶縁層(12)および素子層(13)を備えたSOI基板(1)と、
SOI基板(1)の上に設けられたGaNヘテロ構造(20)と、
GaNヘテロ構造(20)の上面から前記ハンドリング層(11)に延びる溝(14)に設置された半導体層(30)と、を備え、
GaNヘテロ構造(20)および半導体層(30)は横方向に並置され、
GaNベース素子(40)がGaNヘテロ構造(20)に形成され、一方、CMOS素子(50)が半導体層(30)に形成されている集積半導体基板構造。 - GaNヘテロ構造(20)と半導体層(30)を互いに電気絶縁するための絶縁層(15)が、溝(14)の側壁に設けられる請求項1記載の集積半導体基板構造。
- 素子層(13)は、GaNヘテロ構造(20)の成長に適した結晶配向を有する請求項1記載の集積半導体基板構造。
- 半導体層(30)は、再結晶化されて、SOI基板(1)のハンドリング層(11)と同じ結晶配向を有する請求項1記載の集積半導体基板構造。
- 半導体基板(1)と、
半導体基板(1)の上面から内部に延びる溝(14)に設置されたGaNヘテロ構造(20)と、を備え、
溝(14)の底部には、GaNヘテロ構造(20)の成長に適した配向を持つ第1側面(14−1)および絶縁マスクで覆われた第2側面(22−1)を有するV字状の小溝が設けられる集積半導体基板構造。 - GaNベース素子の区画のための第1素子エリア(51)と、CMOS素子の区画のための第2素子エリア(52)が設けられる集積半導体基板構造の製造方法であって、
半導体基板(1)を用意するステップと、
半導体基板(1)の上面から内部に延びる溝(14)を形成するステップと、
溝(14)の底部にエッチングマスク(24)を形成し、エッチングを行うことによって、GaNヘテロ構造(20)の成長に適した配向を持つ第1側面(14−1)および絶縁マスクで覆われた第2側面(22−1)を有するV字状の小溝を形成するステップと、
溝(14)にGaNヘテロ構造(20)を選択成長させ、エッチングマスク(24)を選択成長用マスクとして用いて第1素子エリア(51)を区画するステップと、を含む方法。 - GaNベース素子の区画のための第1素子エリア(51)と、CMOS素子の区画のための第2素子エリア(52)が設けられる集積半導体基板構造の製造方法であって、
ハンドリング層(11)、埋め込み絶縁層(12)および素子層(13)を備えたSOI基板(1)を用意するステップと、
SOI基板(1)の上に、GaNヘテロ構造(20)を成長させるステップと、
GaNヘテロ構造(20)の上面から前記ハンドリング層(11)に延びる溝(14)を形成するステップと、
溝(14)内に、半導体層(30)を選択成長させるステップと、を含む方法。 - 下地のハンドリング層(11)と同じ結晶配向が得られるように、半導体層(30)を再結晶化するステップをさらに含む請求項7記載の方法。
- 溝(14)を形成した後、GaNヘテロ構造(20)と半導体層(30)を互いに電気絶縁するための絶縁層(15)を溝(14)の側壁に設けるステップをさらに含む請求項6または7記載の方法。
- 選択成長の後、半導体基板構造の上面を研磨するステップをさらに含む請求項6または7記載の方法。
- 集積回路の製造方法であって、
請求項1〜5のいずれかに記載の集積半導体基板構造を用意するステップと、
GaN素子(40)を第1素子エリアに区画するステップと、
少なくとも1つのCMOS素子(50)を第2素子エリアに区画するステップと、
GaN素子(40)および少なくとも1つのCMOS素子(50)の両方のための相互接続構造を設けるステップ、とを含む方法。
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EP09174721.2A EP2317554B1 (en) | 2009-10-30 | 2009-10-30 | Integrated semiconductor substrate structure and method of manufacturing an integrated semiconductor substrate structure |
EP09174721.2 | 2009-10-30 | ||
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